Glossary

Definitions for wafer.space process, layout, verification, packaging, and tool terms.

This glossary defines terms as used in the wafer.space archive. Foundry manuals and current tool documentation remain authoritative for detailed technical definitions.

Process and allocation

GF180MCU / gf180mcuD — The process family used by wafer.space and the gf180mcuD run variant named in the cited discussion. (archive message; Discord)
MPW — Multi-project wafer. The cited explanation describes Tiny Tapeout as several projects sharing one die, with that die then placed as one project on a multi-project wafer. (archive message; Discord)
Slot — A purchased die-area allocation. Quarter, half-height, half-width, and 1x1 forms appear in the archive. (archive message; Discord)
Reticle — The combined project layout exposed repeatedly across the wafer. (archive message; Discord)

Layout and verification

GDS / GDSII — Layout data read by precheck and emitted as the final fabrication layout. (archive message; Discord)
Precheck — The wafer.space acceptance flow described as reading GDS, running checks, inserting the project ID, and producing fabrication GDS. (archive message; Discord)
DRC — Design-rule check. The archive's explicit tapeout guidance assigns authority to KLayout DRC. (archive message; Discord)
LVS — Layout versus schematic check. The template example was reported DRC- and LVS-clean. (archive message; Discord)
PEX — Parasitic extraction. The archive says Magic can extract pwell and isosub resistance during PEX even though public resistor models were not listed for them. (archive message; Discord)
Seal ring — Outer protective structure inserted by the project-template flow after user GDS streamout. (archive message; Discord)

I/O and packaging

Pad frame / pad ring — The die-edge I/O and power-pad arrangement. CoB compatibility depends on expected bond-pad coordinates and power/ground pads. (archive message; Discord)
CoB — Chip on board. The die is wire-bonded to a small PCB which can connect to a motherboard. (archive message; Discord)
Wire bond — Fine connection from a die bond pad to a PCB bond finger. Early Run 1 failures were thought likely to involve wires lifting from pads. (archive message; Discord)
Mezzanine — The 70-pin board-to-board connector described between the CoB PCB and a motherboard. (archive message; Discord)
WLCSP — Wafer-level chip-scale packaging. It was discussed as having good unit economics at quantity but high low-volume setup and assembly cost. (archive message; Discord)

Analog options

MIM-B — Metal-insulator-metal capacitor option. Community claim, not controlled fact: one message names it as usable, but the selected run option remains unresolved. See Process options and open questions. (archive message; Discord)
High-res poly — High-sheet-resistance polysilicon option. Community claim, not controlled fact: one message names 1 kΩ/square, but the selected run value remains unresolved. See Process options and open questions. (archive message; Discord)

Tool names

KLayout, Magic, Netgen, LibreLane, and OpenROAD are related layout, verification, and implementation tools. They are not interchangeable. See LibreLane and Tooling and Analog Layout, Verification, and PEX for their cited roles. (archive message; Discord) (archive message; Discord)

Sources

1421044969031860327 — 2025-09-26T08:05:22.356Z — Leo Moser (mole99) — archive message; Discord — GDS and precheck.
1423349035892478074 — 2025-10-02T16:40:54.703Z — Leo Moser (mole99) — archive message; Discord — LVS and seal ring.
1425749959227080724 — 2025-10-09T07:41:19.433Z — Leo Moser (mole99) — archive message; Discord — Pad frame.
1429068742108909638 — 2025-10-18T11:28:58.932Z — Andrew Wingate — archive message; Discord — Mezzanine connector.
1445599978696347821 — 2025-12-03T02:18:12.870Z — Tim 'mithro' Ansell — archive message; Discord — Reticle.
1450226544965324943 — 2025-12-15T20:42:32.226Z — RebelMike — archive message; Discord — Slot forms.
1450889190068981913 — 2025-12-17T16:35:39.130Z — Andrew Wingate — archive message; Discord — CoB.
1483013259635327016 — 2026-03-16T08:05:14.151Z — Leo Moser (mole99) — archive message; Discord — DRC.
1497771485966897273 — 2026-04-26T01:29:09.503Z — Tim 'mithro' Ansell — archive message; Discord — Wire-bond failure mode.
1503782063680126997 — 2026-05-12T15:33:02.901Z — BreakingTaps — archive message; Discord — MPW.
1511240045099483146 — 2026-06-02T05:28:24.234Z — tnt — archive message; Discord — MIM-B.
1511722026648338514 — 2026-06-03T13:23:37.590Z — Leo Moser (mole99) — archive message; Discord — LibreLane and implementation tools.
1512712326745423975 — 2026-06-06T06:58:43.532Z — tnt — archive message; Discord — Process variant and high-res poly.
1513436381781950605 — 2026-06-08T06:55:51.705Z — Leo Moser (mole99) — archive message; Discord — PEX.
1515650076645523457 — 2026-06-14T09:32:17.689Z — Leo Moser (mole99) — archive message; Discord — Tool roles.
1533828923555840230 — 2026-08-03T13:28:32.539Z — Tim Edwards — archive message; Discord — WLCSP.