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#🕰️-analog

415 Discord messages from 📐 - Designing/analog/channel.md.

Category: 📐 - Designing Channel ID: 1408135265427394661

Messages: 415

message-1408135402891640905

2025-08-21T17:07:21.94+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards, @Tholin had some questions / thoughts about analog stuff on GF180MCU.
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message-1408137402173624442

2025-08-21T17:15:18.606+00:00 — Tholin (@tholin)

Content

Not really questions as much as I just wanna mess around and find out with some analog circuits on my next GF180 tapeout.
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message-1408150314347139184

2025-08-21T18:06:37.108+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Sure, analog IP is yet another need for GF180MCU.  I would take a look at what's being produced for Chipathon.  I have been running my own track so I haven't been looking at what the analog groups have been doing, but for the record, you can find the Chipathon discussions on fossi-chat.org under the "Chipathon 2025" channel, or on github at https://github.com/sscs-ose/sscs-chipathon-2025/issues.
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message-1408316135874760817

2025-08-22T05:05:32.041+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

There is a bunch of interesting information in the Chipathon page @ https://github.com/sscs-ose/sscs-chipathon-2025/tree/main/resources/Integration

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message-1408453485195690046

2025-08-22T14:11:18.671+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  If nothing else, Chipathon 2025 is surfacing a number of issues in the GF180MCU open PDK that needed to be addressed, and they are getting fixed, which will definitely benefit you and wafer.space for the first shuttle run.
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message-1408486036991901819

2025-08-22T16:20:39.624+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

Yeap! You know I'm a big believer that quality is related to the number of users.
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message-1419667701088911361

2025-09-22T12:52:36.09+00:00 — Tholin (@tholin)

Content

I tried doing analog for the first time and its going quite well, actually.

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message-1419669482619801603

2025-09-22T12:59:40.84+00:00 — tnt (@246tnt)

Content

At 5V with that much headroom, I'd hope so 😅

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message-1419671807291691143

2025-09-22T13:08:55.085+00:00 — Tholin (@tholin)

Content

The opamps I can build here are not nearly rail-to-rail and have some nasty nonlinearities on the output the more you move away from 2.5V in either direction.

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message-1419679392216645843

2025-09-22T13:39:03.472+00:00 — Tholin (@tholin)

Content

As for why I need a sine/cosine wave generator: I am trying to generate the chroma component of a color NTSC signal. Because why do something the easy way when you can loose your sanity doing it the hard way?

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message-1425663911406862337

2025-10-09T01:59:24.034+00:00 — madbrain (@mrmadbrain)

Content

ooh, so it's basically close to a 3.58 mhz bandpass filter? :3
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message-1425700758694658099

2025-10-09T04:25:49.112+00:00 — peterkinget

Content

If you are looking for example projects and designs, mostly in analog, take a look at https://vlsidesignlab.org. The site has several years of project websites and videos of the VLSI design lab class at Columbia University where students design a chip in the spring, it gets fabricated in summer, and they test it in fall. There is quite a bit of design information available, and there is a search and index also. Have fun!
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message-1426213521422815293

2025-10-10T14:23:21.273+00:00 — madbrain (@mrmadbrain)

Content

Question... Is it reasonable to try to implement an Operational Transconductance Amplifier in the target process? - something in the vein of LM13700 ( https://www.google.com/url?sa=t&source=web&rct=j&opi=89978449&url=https://www.ti.com/lit/ds/symlink/lm13700.pdf&ved=2ahUKEwiOqube6ZmQAxWEj4kEHSjgB54QFnoECBkQAQ&usg=AOvVaw3GXAglJwE-LG-Gg1gfRkxv )... if yes, I imagine it might have tighter limits on currents/voltage/wattage?
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message-1426374309911335022

2025-10-11T01:02:16.236+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

@Tim Edwards - Any thoughts on @madbrain's question?
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message-1427200882931400774

2025-10-13T07:46:46.601+00:00 — Valgamaa (@valgamaa)

Reply/reference

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Content

You won't have anything like the supply range of the 13700, which is over 30 volts (from memory). If that isn't an issue then there is nothing to stop you making such a circuit while also including extra circuits like a voltage-controlled input for gm control. I used a similar process for a 4MHz gm-C bandpass filter many years ago with good results, and there are many MOS 'tricks' that you can use to get significantly lower distortion than the 13700 has.
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message-1427201726154408007

2025-10-13T07:50:07.641+00:00 — madbrain (@mrmadbrain)

Content

great to know 👍  the applications I'm looking into are boutique synthesizers so the S-curve shaped distortion is often a feature rather than a bug 😉
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message-1427216446047518780

2025-10-13T08:48:37.137+00:00 — Valgamaa (@valgamaa)

Content

You won't get a tanh curve, but you will get something similar with MOS transistors. DC offsets might need some consideration and the capacitor options on-chip will be too low density to be much use. Making the circuits differential might give the headroom you will want, and with that gyrators become very simple (that's the key to most filters in CMOS) but I doubt you will want to implement standard filter responses like Butterworth etc. I half-wondered if it might be synthesiser-related when I saw mention of the 13700!
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message-1427223856355213353

2025-10-13T09:18:03.892+00:00 — madbrain (@mrmadbrain)

Content

yeah typically for synthesizers the more common filter types are state variable (SVF) and moog-style 4 pole ladder... often deliberately non-linear so that the response doesn't blow up when you crank up the Q-factor... might have to look into having the output current mirrors have a digitally controllable multiplication factor 🤔
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message-1427244764423655456

2025-10-13T10:41:08.764+00:00 — Valgamaa (@valgamaa)

Content

The SSM2044-type topology would map onto this process pretty well, I think. How much experience do you have with MOS circuit design? Most of the blocks you would want for a synthesiser are a really good vehicle to cover most of the circuit topologies that make for good CMOS design. A temperature-insensitive VCO should also be quite practical in this process too.
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message-1427287256338665596

2025-10-13T13:29:59.626+00:00 — madbrain (@mrmadbrain)

Content

I'm kindof out of my depth ngl :3 my usual gig is synths in C++ on desktop computers
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message-1427321156603609193

2025-10-13T15:44:42.079+00:00 — madbrain (@mrmadbrain)

Content

(and reverse engineering... including some time on the CEM synthesizer chips which are really all OTA variants similar to lm13700 inside in different arrangements...)
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message-1428161230907904072

2025-10-15T23:22:51.401+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://hackaday.com/2025/10/15/more-than-100-sub-circuit-designs-from-texas-instruments/

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message-1429228175019347969

2025-10-18T22:02:30.7+00:00 — madbrain (@mrmadbrain)

Content

it's all op amp basic circuits for the most part?
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message-1432427038031220899

2025-10-27T17:53:39.074+00:00 — Mark Anderson (@markemer)

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Content

That rules. My design class just built in IBM8RF but we did not build it as it was too expensive. Hilariously 8RF was either 130 or 90nm, so the stuff we're doing now. Although it was SOI.
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message-1434028768942493696

2025-11-01T03:58:21.482+00:00 — social (@.social.)

Content

hi there. anyone down to talk about silicon production (analog chips) in older processes? i'm talking to a fab and they're telling me the kind of design that i am talking to them about could result in a bunch of crosstalk, so i'm looking for ideas on how to mitigate that. the chip carries analog audio, so this is about capacitive coupling.
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message-1435071254611624000

2025-11-04T01:00:49.434+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

I would just do a tapeout with Tiny Tapeout and see if it matches expectations
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message-1435071454310830150

2025-11-04T01:01:37.046+00:00 — social (@.social.)

Content

tiny tapeout is great, but my ultimate goal is to go into commercial production with a fab
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message-1435071580945518682

2025-11-04T01:02:07.238+00:00 — social (@.social.)

Content

however, i resolved the crosstalk issue. i guess it was a translation problem between russian and english.
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message-1435071716081533133

2025-11-04T01:02:39.457+00:00 — social (@.social.)

Content

they didn't mean to say it was going to create a bunch of crosstalk, they were telling me they had a solution which has low cross talk.
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message-1435071785916956754

2025-11-04T01:02:56.107+00:00 — social (@.social.)

Content

they just didn't know how to say it 🙂
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message-1442548790430007329

2025-11-24T16:13:52.899+00:00 — tnt (@246tnt)

Content

So I'm trying to work on the power gates for TT but hitting some DRC errors. In particular `NP.12` I don't understand.
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message-1442549125844566057

2025-11-24T16:15:12.868+00:00 — tnt (@246tnt)

Content

`NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate.`

Which I understand as, "NPlus can't overlap poly that's used by a pmos if that poly is closer than 0.32um to the actual gate zone"
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message-1442549382921715732

2025-11-24T16:16:14.16+00:00 — tnt (@246tnt)

Content

But then I get this from the DRC. ( Only `COMP` / `Nplus` / `Poly` shown ). And the `Nplus` doesn't overlat `Poly` _at_ _all_ ...

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message-1442707763753914464

2025-11-25T02:45:35.093+00:00 — bailey (@bailey8889)

Reply/reference

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Started a thread.
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message-1449050919206518824

2025-12-12T14:51:01.203+00:00 — dkktvtcdrmpusap (@dkktvtcdrmpusap_57896)

Content

||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​||||​|| _ _ _ _ _ _  https://imgur.com/lUxe13P https://imgur.com/9xq8zso https://imgur.com/DEwAKqa https://imgur.com/hxTkjHU @here

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message-1461780860943597700

2026-01-16T17:55:15.824+00:00 — BreakingTaps (@polyfractal)

Content

Been dabbling with analog recently and was curiosu if any of the automated analog layout tools worked well. ALIGN (https://github.com/ALIGN-analoglayout/ALIGN-public) looked most promising and had a Sky130 PDK, so I threw Claude Code at it. Sorta have a working GF180 PDK now? Takes in a spice netlist, constraints (matching, symmetry, etc) and spits out GDS

Found some pretty serious limitations though, namely that ALIGN was built with finfet nodes in mind so there are a lot of restrictive routing/placement constraints baked into the core. Had to modify the core to get even moderately compact layouts and it's still a lot of wasted space. DRC and LVS match, but haven't run simulations on the generated output yet... could be hot garbage 😅

Still, neato tool. Kinda want to start working on something that's tailored for big legacy nodes that have less restrictive DRC.

(screenshot is a CSA + Discriminator + Krummenacher feedback circuit that i've been playing around with)

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message-1462073625485246616

2026-01-17T13:18:36.33+00:00 — Matt Venn (@mattvenn)

Content

Harald pretl also tested an automatic layout tool on tt05
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message-1462073981690446069

2026-01-17T13:20:01.256+00:00 — Matt Venn (@mattvenn)

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https://tinytapeout.com/chips/tt05/tt_um_tt05_analog_test

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message-1463071530153021483

2026-01-20T07:23:55.343+00:00 — Tim 'mithro' Ansell (@mithro_)

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@BreakingTaps - Take a look at OpenFASoC from Mehdi
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message-1463071629297844368

2026-01-20T07:24:18.981+00:00 — Tim 'mithro' Ansell (@mithro_)

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@BreakingTaps - https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/openfasoc

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message-1463226087860469761

2026-01-20T17:38:04.772+00:00 — Clyde Laforge (@scafir)

Content

Finally got the LVS working end-to-end from xschem to klayout without any manual  conversion steps from a user point of view 🎉
Just need to wait for @Leo Moser (mole99)  to upstream the improvements from wafer space now 🙂

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message-1463229843440144394

2026-01-20T17:53:00.172+00:00 — tnt (@246tnt)

Content

And did you check you didn't break the xschem / magic / netgen flow ? (like if you changed anything in the xschem symbols for instance that could break the other flows ... )
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message-1463231137777451070

2026-01-20T17:58:08.766+00:00 — Clyde Laforge (@scafir)

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The changes are fully contained in the klayout directory, so likelihood of breaking other flows is rather low

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message-1463247695719305372

2026-01-20T19:03:56.487+00:00 — Leo Moser (mole99) (@mole99)

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Awesome Clyde 🥳
I'll start upstreaming the wafer.space changes to the FOSSi repos soon. However, you don't necessarily have to wait for that, since your LVS changes should be standalone?
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message-1463271781820268710

2026-01-20T20:39:39.061+00:00 — Clyde Laforge (@scafir)

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It is slightly dependent, as it adds new GUI options, but let's discuss it when I open the MR, maybe they are not necessary

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message-1463409587779666033

2026-01-21T05:47:14.562+00:00 — BreakingTaps (@polyfractal)

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oh neat! Will give this a closer read tomorrow
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message-1479386867035144244

2026-03-06T07:55:14.78+00:00 — Thomas Dexter (@tdextrous)

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I'm curious if anyone has had success designing inductors in this process? The top metal seems good enough but wondering if metal fill (assuming it is done by the fab and not in the designer's control) would make the final results unpredictable.
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message-1479389805681967130

2026-03-06T08:06:55.408+00:00 — Leo Moser (mole99) (@mole99)

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Started a thread.
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message-1481885014231879680

2026-03-13T05:21:59.485+00:00 — beardothaweirdo (@wspitts2)

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If you like, I can see if I can figure out how we got ASITIC working at our site... I did fix cadence's inductor pcell generator. I could reach out to them and see if they would let me put it in the wild as well. It was broken forever until I found the need to stand it up to do EMX inductors on Sky130.
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message-1481885255936774318

2026-03-13T05:22:57.112+00:00 — beardothaweirdo (@wspitts2)

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ASITIC is opensource inductor simulator.
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message-1483002780330360985

2026-03-16T07:23:35.69+00:00 — nmz787

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anyone here using openEMS/elmer/palace/etc for getting SPICE model and simulating analog front-ends?
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message-1483646099750391869

2026-03-18T01:59:54.992+00:00 — Tim 'mithro' Ansell (@mithro_)

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@nmz787 - There are a few examples mentioned on the Zero to ASIC Course YouTube channel I think.

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message-1483694160891351212

2026-03-18T05:10:53.661+00:00 — Vipul (@vipul.sh)

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Have used openems to generate inductor s2p model for IHP.
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message-1483964549718872124

2026-03-18T23:05:19.381+00:00 — Matt G. (Mobius) (@mguthaus)

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I made a Cocotb Analog-Mixed-Signal (AMS) extension in about less than an hour using Claude.  It can output VCD of Verilog simulations along with real-valued signals from ngspice. Any suggestions to improve it?
https://vlsida.github.io/cocotbext-ams/

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2026-03-19T14:44:43.066+00:00 — Matt G. (Mobius) (@mguthaus)

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Added Xyce support but it isn't event-driven due to API limitations
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message-1485479616000036876

2026-03-23T03:25:39.331+00:00 — Tim 'mithro' Ansell (@mithro_)

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https://epub.jku.at/obvulihs/content/titleinfo/13546624/full.pdf looks kind of interesting, anyone understand it more than I do and could provide a summary / feedback / thoughts?
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2026-03-23T07:01:23.564+00:00 — Simi (@simi150500)

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See here: https://youtu.be/2xSAK-mDGEY?is=s5H5dOhiioJvBlFS

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2026-03-23T07:02:47.778+00:00 — Simi (@simi150500)

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Ghaith did his impressive Master's Thesis at our Integrated Circuit Design department at JKU.
I invited him to the channel for further details. 👍
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2026-03-23T07:08:00.909+00:00 — Ghaith Al Sabagh (@ghaithalsabagh)

Reply/reference

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Hi Tim!
I am the author 🙂

At Wed I have my master exam. After that, I could provide you the information you need 😉
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message-1488714623258464389

2026-04-01T01:40:25.165+00:00 — nmz787

Content

Are there instructions for linking xschem to the pdk symbol+schematic libraries and bsim models ?
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message-1488714714660995263

2026-04-01T01:40:46.957+00:00 — nmz787

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(or maybe the bsim models are more relevant to ngspice and or xyce)
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2026-04-15T18:24:27.487+00:00 — namibj

Reply/reference

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If you haven't figured it out yet I'm happy to share my setup I got a lil help from tnt on with you if you'd write it into a brief blog post like "tutorial/instructions", like this weekend.
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2026-04-15T18:44:06.512+00:00 — namibj

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In other "topic", how high-order of a delta-sigma DAC would be reasonable to pull off for on-die bias generation?

I'd prefer to get by with a modest oversampling ratio to keep decent loop bandwidth even with the digital PLL being "limited" to CMOS logic speeds instead of the core's MCML (there's no way I finish enough of a cell library to make even just the delta sigma modulator (probably MASH?) out of MCML, before the deadline) speeds...
It'd already look at doing the fast side of the time-to-digital converter in the little amount of MCML (as that way it would at least be able to directly count quarter clocks of timing, I think...).
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2026-04-15T19:05:34.481+00:00 — nmz787

Reply/reference

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I would love to... But I'm on vacation away from laptop with my setup until Monday
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message-1494051236700356739

2026-04-15T19:06:12.959+00:00 — nmz787

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And no I didn't figure it out. I spent time trying to kick openAI codex to build something for me lol
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2026-04-15T20:14:34.711+00:00 — namibj

Reply/reference

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wednesday daytime berlin time should work, probably
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message-1495822285607796736

2026-04-20T16:23:43.923+00:00 — namibj

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Anyone happen to have some examples for "parametric cells" that try to do analog "buffer"/"amplifier"?
I.... _kinda_ need to quickly figure out how to automate layout-parasitics-including tuning so I can get it running. I have sufficiently-ish conquered xschem on the matter but that's ignorant of layout parasitics.
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message-1496035164092891236

2026-04-21T06:29:38.109+00:00 — Buzz (@davidbuzz)

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honest Q, is a MEMS device considered analog.?
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2026-04-21T06:32:51.25+00:00 — Buzz (@davidbuzz)

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I'm thinking , naturally of somethuing like a MEMS gyro or a MEMS accelerometer, eg, a ADXL213 https://www.richis-lab.de/images/ADXL213/03.jpg  https://www.richis-lab.de/images/ADXL213/06.jpg  https://www.richis-lab.de/images/ADXL213/07.jpg

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message-1496036118729195550

2026-04-21T06:33:25.712+00:00 — Buzz (@davidbuzz)

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reference: https://www.eevblog.com/forum/projects/mems-nice-die-pictures/
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2026-04-21T06:40:21.64+00:00 — Buzz (@davidbuzz)

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i believe 'laser ablation' of the wafer to make thru-trenches *after* its been processed like regular silicon for the electronic parts, and before packaging,  is the usual process , sometimes they are back-ground to make them thinner too.
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message-1496038414796062820

2026-04-21T06:42:33.137+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Kinda but not really. MEMS generally requires things like undercuts which are not something supported on silicon process technologies - the circuits driving / reading the MEMS structures are frequently analog ADC/DACs. If you are interested in MEMS maybe check out science.xyz - they had credit card orderable MEMS processes.
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2026-04-21T06:59:25.283+00:00 — Buzz (@davidbuzz)

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https://www.analog.com/en/resources/technical-articles/accelerometer-and-gyroscopes-sensors-operation-sensing-and-applications.html
a mems gyro is usually in constant oscillation and a mems accelerometer is usually not, but they are fundamentally compatible technologies.
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2026-04-21T07:00:11.148+00:00 — Buzz (@davidbuzz)

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its basically measuring capacitance change over time
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2026-04-21T07:01:06.25+00:00 — Buzz (@davidbuzz)

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anyway, dont mine me, ive got a thing for sensors. 🙂
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message-1496470324894503052

2026-04-22T11:18:48.529+00:00 — Tim 'mithro' Ansell (@mithro_)

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https://science.xyz/docs/c/mems-pdk

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2026-04-23T05:46:12.044+00:00 — Ghaith Al Sabagh (@ghaithalsabagh)

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I am not that expert, but this one seems to be like silicon technologies.
https://science.xyz/docs/d/mems-soi/index
IHP as far as I know offers LBE (localized backside etching) too.

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2026-04-23T05:48:11.837+00:00 — tnt (@246tnt)

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IHP does  LBE but not on the cost reduced runs, you'll have to go through their full commercial service for that.
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2026-04-23T05:48:44.194+00:00 — Ghaith Al Sabagh (@ghaithalsabagh)

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Actually it depends I think
It is wafer post-processing
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2026-04-23T05:49:05.423+00:00 — Ghaith Al Sabagh (@ghaithalsabagh)

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You can still make a normal wafer on reduced cost, then send it to LBE
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2026-04-23T05:49:09.794+00:00 — Ghaith Al Sabagh (@ghaithalsabagh)

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I assume
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2026-04-23T05:49:25.194+00:00 — tnt (@246tnt)

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No, because on reduced cost the wafer is shared ... you don't get a full wafer 🙂
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2026-04-23T05:50:01.268+00:00 — tnt (@246tnt)

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Unless you can do LBE yourself on individual sliced dies.
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2026-04-23T05:50:36.295+00:00 — tnt (@246tnt)

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And LBE not being on the cost reduced runs is what IHP themselves said because that question was asked at some point.
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2026-04-23T05:52:41.121+00:00 — Ghaith Al Sabagh (@ghaithalsabagh)

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The question is if an open-source community make a run for MEMS. Then they can share the wafer, but after LBE. What I mean is that It would be possible to handle such issue for a whole wafer after discussing with IHP. It would cost somehow more yes
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message-1496750911119167592

2026-04-23T05:53:45.498+00:00 — Tim 'mithro' Ansell (@mithro_)

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Could you potentially get wafers.space wafers LBE? I do offer purchase of full wafers.
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2026-04-23T05:54:53.2+00:00 — Ghaith Al Sabagh (@ghaithalsabagh)

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Do you offer LBE?
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2026-04-23T14:21:00.632+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I do not.
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message-1498189273004904468

2026-04-27T05:09:17.695+00:00 — Joaquin Matres (@joaquinmatres)

Content

For MEMs we have some open source structures here
https://gdsfactory.github.io/gdsfactory/components.html#gdsfactory.components.mems.gear

@namibj For amplifiers
you can check out
https://gdsfactory.github.io/IHP/cells.html
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message-1498369103792967750

2026-04-27T17:03:52.696+00:00 — BreakingTaps (@polyfractal)

Content

I didn't realize gdsfactory had such a wide array of pcells!
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message-1498382259110285643

2026-04-27T17:56:09.168+00:00 — Thomas Pluck 2.1 (@tpluck_)

Content

So looks like Danube River is out of gas and we need someone to measure the test structures, anybody able and willing with a probe station to make it happen?
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message-1498382510206357504

2026-04-27T17:57:09.034+00:00 — Thomas Pluck 2.1 (@tpluck_)

Content

https://wiki.libresilicon.com/index.php?title=Danube_River

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message-1498382945751269578

2026-04-27T17:58:52.876+00:00 — Thomas Pluck 2.1 (@tpluck_)

Content

(unless you're some kind of corporate shill)
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message-1498384841669087495

2026-04-27T18:06:24.898+00:00 — BreakingTaps (@polyfractal)

Content

*keyence enters chat*
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message-1498391898388430848

2026-04-27T18:34:27.351+00:00 — Thomas Pluck 2.1 (@tpluck_)

Content

Attachments

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message-1498429497811402837

2026-04-27T21:03:51.752+00:00 — namibj

Reply/reference

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_looks at beloved https://www.iptest.com/ mousepad_

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message-1498587130979549205

2026-04-28T07:30:14.428+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Probably out of our price range, but CoolCAD did a bunch of the testing for the SKY130 raw data repo in conjunction with NIST.
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message-1498764045962973215

2026-04-28T19:13:14.247+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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still poking at my GF180 pdk for ALIGN. starting to see light at the end of the tunnel, most (synthetic) generated designs are coming out LVS and DRC clean. Still needs some human sanity checking to make sure the schematics are what they are actually supposed to be. But from just skimming designs they are looking better than before, respecting constraints like symmetry now, etc

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message-1498764387941486753

2026-04-28T19:14:35.781+00:00 — BreakingTaps (@polyfractal)

Content

still some issues with spacing but it's a constant battle against overzealous packing and DRC violations 🫠
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message-1498836736904794263

2026-04-29T00:02:05.118+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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When you say ALIGN - do you mean the project that came out of the DARPA IDEA/POSH program?
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message-1498838648894914591

2026-04-29T00:09:40.972+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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possibly? This: https://github.com/ALIGN-analoglayout/ALIGN-public

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message-1498839756002557952

2026-04-29T00:14:04.927+00:00 — BreakingTaps (@polyfractal)

Content

(yes seems to be from that DARPA IDEA/ERI "no humans in the loop" project)
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message-1498840585736421539

2026-04-29T00:17:22.751+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Yeap!
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message-1498840816846897245

2026-04-29T00:18:17.852+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - We should most certainly send GF180MCU support upstream if you get it working.
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message-1498840931435020358

2026-04-29T00:18:45.172+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - I met the people behind ALIGN a few times at the DARPA workshops.
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message-1498867157054783529

2026-04-29T02:02:57.847+00:00 — BreakingTaps (@polyfractal)

Content

will try to tidy things up when I get everything in working order! I did make some changes to ALIGN itself which may be difficult to upstream but we can have a chat with them. There are a number of assumptions baked into how it places cells, mostly assuming you're on a finfet node. So it standardizes row height, adds dummy poly fingers after cells, stuff like that. Ended up wasting a ton of space on a big node like GF180

Loosening some of those rules then puts cells in potential corner-contact between rows, so added some constraints to the ILP solver to avoid corner touches etc etc
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message-1498867254509572277

2026-04-29T02:03:21.082+00:00 — BreakingTaps (@polyfractal)

Content

that said, I think the GF180 PDK itself should be portable to "stock" ALIGN, it'll just be bulky
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message-1498932033752272896

2026-04-29T06:20:45.657+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - They have some demonstration bulk node PDKs
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message-1499081521863069918

2026-04-29T16:14:46.4+00:00 — BreakingTaps (@polyfractal)

Content

yeah there's a sky130 in there. i haven't looked at it for a while but iirc it also had a ton of wasted space
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message-1499085846727626863

2026-04-29T16:31:57.528+00:00 — BreakingTaps (@polyfractal)

Content

The biggest problem was multiple dummy fingers get appended to edges of cells. The hardcoded values in ALIGN uses gateDummy=3, which adds 3.2um per cell of "wasted" poly strips per cell (multiplied by the number of x_cells the transistor is being split into). Cells are also rounded to multiples of M3 pitch (800nm) which can interact badly with the finger widths too and bulk it even more

Row heights are pinned to the tallest cell, so you can also get big empty rows despite the solver trying to minimize area.

None of it is _wrong_ per se, but it's definitely optimized for a node that has discrete diffusion/fin widths and tight gate pitches (at least from my outsider, relative newcomer 🙂 )
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message-1499087085246615663

2026-04-29T16:36:52.814+00:00 — BreakingTaps (@polyfractal)

Content

but luckily, open source! so easy enough to tweak and experiment with 🙂
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message-1499151760202141898

2026-04-29T20:53:52.525+00:00 — namibj

Reply/reference

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Content

got a schematic to go wtih that layout by chance?
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message-1499189666786578463

2026-04-29T23:24:30.159+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

Believe it was this one. Caveat that this schematic was synthetically generated and very possibly nonsensical 🙂

```
* Folded Cascode OTA: W=1.32u, NF=2
.SUBCKT OTA_FOLDED_W1P32U_NF2 VSS VDD INP INN OUT VBIAS VCASN VCASP
* PMOS input differential pair
M1 N1 INP TAIL VDD pfet_03v3 w=1.32u l=280n nf=2 m=1
M2 N2 INN TAIL VDD pfet_03v3 w=1.32u l=280n nf=2 m=1
* Tail current source
M0 TAIL VBIAS VSS VSS nfet_03v3 w=2.64u l=280n nf=2 m=2
* Folded NMOS cascode
M3 N1 VCASN N3 VSS nfet_03v3 w=1.32u l=280n nf=2 m=1
M4 N2 VCASN N4 VSS nfet_03v3 w=1.32u l=280n nf=2 m=1
* NMOS current source
M9 N3 VBIAS VSS VSS nfet_03v3 w=1.32u l=280n nf=2 m=1
M10 N4 VBIAS VSS VSS nfet_03v3 w=1.32u l=280n nf=2 m=1
* PMOS cascode loads
M5 N1 VCASP N5 VDD pfet_03v3 w=1.32u l=280n nf=2 m=1
M6 N5 N5 VDD VDD pfet_03v3 w=1.32u l=280n nf=2 m=1
M7 N2 VCASP OUT VDD pfet_03v3 w=1.32u l=280n nf=2 m=1
M8 OUT N5 VDD VDD pfet_03v3 w=1.32u l=280n nf=2 m=1
.ENDS OTA_FOLDED_W1P32U_NF2
```
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message-1499189834474848288

2026-04-29T23:25:10.139+00:00 — namibj

Content

as long as it reasonably confidently corresponds to the layout I'm fine
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message-1499190093137580082

2026-04-29T23:26:11.809+00:00 — BreakingTaps (@polyfractal)

Content

(there's also a constraint file that goes along with that somewhere, which specifies stuff like symmetry. would need to hunt for that when i get home)
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message-1499190122363617392

2026-04-29T23:26:18.777+00:00 — namibj

Content

i'd happily take a "fresh" pair btw if that's easier to givew with confidence
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message-1499190212117659669

2026-04-29T23:26:40.176+00:00 — namibj

Content

oh I'm going to bed now, they took my teeth yesterday 🙁
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message-1499190287560347668

2026-04-29T23:26:58.163+00:00 — BreakingTaps (@polyfractal)

Content

😩  oof, feel better!
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message-1499190311224873080

2026-04-29T23:27:03.805+00:00 — namibj

Content

thx
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message-1499190413603635200

2026-04-29T23:27:28.214+00:00 — namibj

Content

I'd expect to look at things now sooner than 20 hours from now fyi
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message-1499248900446486631

2026-04-30T03:19:52.564+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - IIRC The ALIGN team had outstanding success with FinFET nodes due to the very limited type of transistors that you are allowed on them and then struggled with extending it back to planar technologies.

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message-1499270078137503854

2026-04-30T04:44:01.719+00:00 — BreakingTaps (@polyfractal)

Content

ahh interesting. that makes sense, tracks with the sorts of limitations i'm seeing. on the upside, claude/codex are helping me beat back the edge cases by just throwing tons of samples at it and iterating on failures. bit tedious but making progress
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message-1499343125955481740

2026-04-30T09:34:17.676+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

"bit tedious but making progress" I think describe all software development a lot of the time 😉

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message-1499411054520701009

2026-04-30T14:04:13.108+00:00 — Thomas Pluck 2.1 (@tpluck_)

Reply/reference

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Welp, that one's dead on arrival - hope there's something left on Run 2 to get this done for real without ideological strings attached
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2026-04-30T14:26:22.557+00:00 — BreakingTaps (@polyfractal)

Content

huh? ideological strings attached?
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message-1499416656668135484

2026-04-30T14:26:28.764+00:00 — BreakingTaps (@polyfractal)

Content

feel like I'm missing a ton of context here 😄
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message-1499427537653203035

2026-04-30T15:09:42.993+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - @Thomas Pluck 2.1 was offering to figure out characterization of existing test structures taped out on the GF180MCU process technology (see https://siliconpr0n.org/archive/doku.php?id=mcmaster:efabless:gf180mcu-mpw18h1-18100001&s[]=gf180mcu) -- The idea that having some data from these structures would mean better/more advanced ones could then be created for Run #2 and allow even better understanding of the process technology. Sadly the people who currently possess the die are unwilling to share them.

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message-1499428040000798792

2026-04-30T15:11:42.762+00:00 — BreakingTaps (@polyfractal)

Content

ahh, booo 🙁

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message-1501422718451581018

2026-05-06T03:17:51.164+00:00 — Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I am interested in designing a metering ASIC for energy. Design block suggestions and toolchains welcome. Looking to use Tiny Tapeout or Wafer Space given space required.
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message-1503513753533284572

2026-05-11T21:46:52.777+00:00 — BreakingTaps (@polyfractal)

Content

world's least optimized pixel array 😂

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message-1503538749345107998

2026-05-11T23:26:12.243+00:00 — namibj

Reply/reference

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Are you doing photoelectronics for Run2/3?
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message-1503539068967850035

2026-05-11T23:27:28.447+00:00 — namibj

Content

(also that's why back illumination and what microlenses are for)
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message-1503556517926928454

2026-05-12T00:36:48.603+00:00 — BreakingTaps (@polyfractal)

Content

If I can get a bit more of it done in the next week or two, yep! Would love to tape this out for Run2.  it's an "event pixel" design, where each pixel fires asynchronously when its threshold is breached. They register changes in a scene rather than a clocked frame
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message-1503560022028980345

2026-05-12T00:50:44.046+00:00 — namibj

Reply/reference

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ahhhhh.
I was about to say, at that lack of density, might almost go for SPAD (but the DRCs likely prevent the necessary field-smoothing rounding).
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message-1503570511114932328

2026-05-12T01:32:24.839+00:00 — BreakingTaps (@polyfractal)

Content

I should be able to get density higher, ALIGN freaked out once I added the photodiode into the circuit. Either needs some tweaks, or just pull the diode out and hand-place them. but otoh 32x32 is plenty for demonstration and it'll probably make the rest of the project easier so 🤷‍♂️ 🙂
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message-1503570675137253548

2026-05-12T01:33:03.945+00:00 — BreakingTaps (@polyfractal)

Content

SPADs would be neat though!
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message-1503570993137057924

2026-05-12T01:34:19.762+00:00 — BreakingTaps (@polyfractal)

Content

think I saw a paper somewhere with a SPAD done in skywater 130? or maybe even GF 180? will try to find it
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message-1503587462063194203

2026-05-12T02:39:46.26+00:00 — namibj

Content

I'm just a little sad that silicon's indirect bandgap means you can't just use a photodiode for bidirectional communications like you can with e.g. a 405nm-pumped COTS blue LED (load modulation in photovoltaic biasing severely varies how much shunt current in the diode produces electroluminescence; this is fairly easy to separate at the end with the 405nm source and can be used as a back-channel there).
Unless you happen to know some clever trick that'd allow one to do vertical surface emitting data back channel from on top of a gf180mcuD die to some "beefier" system. I mean I guess tbf things like osram/ams's `PLPVYL1 940A_E` 20~60ct/each (depending on quantity) VCSEL do exist... (wish there was a SPICE for it, or even just capacitance information, but oh well....)
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message-1503587887407431761

2026-05-12T02:41:27.67+00:00 — namibj

Content

ohhh, it even hits nicely into peak Si photodiode A/W efficiency....
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message-1503622200320725053

2026-05-12T04:57:48.506+00:00 — BreakingTaps (@polyfractal)

Content

could abuse resistive elements or even just big gates and emit IR 😅

I think porous silicon can be used to make an LED without any other materials, but it's a pretty crapp LED iirc (and far red)
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message-1503622825632731157

2026-05-12T05:00:17.592+00:00 — namibj

Reply/reference

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tho apparently you can just buy VCSEL for so cheap if you buy ones marketed to lower power IR illumination; I should get one next time and try to measure capacitance.
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message-1504576302739488798

2026-05-14T20:09:04.249+00:00 — nmz787

Content

AnalogCoder: Analog Circuit Design via Training-Free Code Generation
https://arxiv.org/pdf/2405.14918

LADAC: Large Language Model-driven Auto-Designer for Analog Circuits
https://www.techrxiv.org/doi/full/10.36227/techrxiv.170473941.10097233/v1


Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System
https://par.nsf.gov/servlets/purl/10356326
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message-1504576338089218229

2026-05-14T20:09:12.677+00:00 — nmz787

Content

@BreakingTaps  ^
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message-1504576360075628776

2026-05-14T20:09:17.919+00:00 — nmz787

Content

ever come across them?
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message-1504576802381893773

2026-05-14T20:11:03.373+00:00 — BreakingTaps (@polyfractal)

Content

I've seen MAGICAL before! MAGICAL and ALIGN were both funded by the same DARPA program and were sort of sibling projects. After looking over them, it seemed that MAGICAL is abandoned/not-very-active and looked harder to extend to other PDKs (the paper or project had a note about how it was difficult to port).

Dunno about the other two, will take a look!
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message-1506005315886252055

2026-05-18T18:47:27.533+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Stupid idea, but could the metal layers be used as reflectors and/or diffraction gratings/etc ?
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message-1506005576122110127

2026-05-18T18:48:29.578+00:00 — namibj

Content

sure, kinda static tho
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message-1506005662851793086

2026-05-18T18:48:50.256+00:00 — namibj

Content

and I at least don't know how good the absolute scale tolerance of the litho is
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message-1506011145327349982

2026-05-18T19:10:37.38+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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I was actually looking into using the metal lines as gratings / structural color recently. Unfortunately the min pitch is pretty large. M1 could get you some mid-visible color, but M2+ is all pretty far red. 🙁

I wonder if you could throw a resistive element under a metal reflector layer and use the thermal expansion though? be sort of like a deformable mirror but fully monolithic 🤔
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message-1506011380996771951

2026-05-18T19:11:33.568+00:00 — namibj

Reply/reference

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Just don't do what tholin seems to have accidentally done (crack dies after first power cycle)

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message-1506011476589150268

2026-05-18T19:11:56.359+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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That is why you get 1,000 of them 😉
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message-1506011580851159090

2026-05-18T19:12:21.217+00:00 — Tim 'mithro' Ansell (@mithro_)

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Could you use some type of pattern between the layers or something?
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message-1506011768730943558

2026-05-18T19:13:06.011+00:00 — namibj

Content

I'd guess the silicon could be modulated in transparency via presence of minority carriers, for some wavelength at least?
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message-1506011972599283883

2026-05-18T19:13:54.617+00:00 — BreakingTaps (@polyfractal)

Content

quite possibly! afraid that's approaching the end of my photonics knowledge. probably easy enough to simulate though
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message-1506012123455684811

2026-05-18T19:14:30.584+00:00 — Tim 'mithro' Ansell (@mithro_)

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The simulation itself might be an interesting video? 😛
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message-1506014422156710058

2026-05-18T19:23:38.637+00:00 — namibj

Content

ahhh yeah internet says _Free-Carrier Plasma Dispersion Effect_
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message-1506014631968243773

2026-05-18T19:24:28.66+00:00 — namibj

Content

modulate refractive index usable on 1310/1550 nm light in silicon photonics waveguides.
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message-1506014830111359097

2026-05-18T19:25:15.901+00:00 — namibj

Content

just have a pn/pin junction and either reverse bias the former to desired width of depletion zone or forward bias the latter to desired minority carrier density
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message-1506017568547405864

2026-05-18T19:36:08.795+00:00 — namibj

Content

as silicon should be pretty transparent there normally, it might work having it be in the resonator and to use it to minutely shift the resonance peak to doa  little FM modulation
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message-1506033023378919550

2026-05-18T20:37:33.514+00:00 — BreakingTaps (@polyfractal)

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heh ran some numbers on this, _very roughly_ you could get 5-10nm of vertical displacement so 10-20nm of reflected displacement. Not nothing!
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message-1506034020490674388

2026-05-18T20:41:31.244+00:00 — namibj

Content

consider comparing to carrier density effects in vertical transmission perhaps for the iirc fairly accessible 1310nm
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message-1506329070714228887

2026-05-19T16:13:56.699+00:00 — Matt Venn (@mattvenn)

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or use multiple metal layers with offsets?
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message-1506628278708998382

2026-05-20T12:02:53.444+00:00 — Tholin (@tholin)

Content

Muuuuch better!

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message-1506628714987782297

2026-05-20T12:04:37.461+00:00 — Tholin (@tholin)

Content

And can still drive a 1K load
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message-1506628918122385509

2026-05-20T12:05:25.892+00:00 — Tholin (@tholin)

Content

Yes, I could still make it use less current by optimizing it to drive smaller loads, but this is a nice tradeoff
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message-1506628957087469622

2026-05-20T12:05:35.182+00:00 — Tholin (@tholin)

Content

My next chip is only going to have 2 of these anyways
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message-1506830460804923432

2026-05-21T01:26:17.412+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - Invest in power gating anyway 😛

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message-1507866967300772072

2026-05-23T22:04:59.818+00:00 — BreakingTaps (@polyfractal)

Content

Welp, defeated by DRC again 🙃

working on a 1T pixel design based off of this paper (https://www.mdpi.com/1424-8220/9/1/131). Needs a floating P body which I figured you could build with DNWell -> LVPWell -> NPlus. Got everything dialed into minimum size that would make DRC happy, then arrayed it and discovered another DRC rule: LVPWell to LVPWell must be >1.4um. There goes my pixel density! 😂

Should still work, but I was hoping for <2-3um pitch so I could play with sub-diffraction limit oversampling stuff. But with that DRC limitation might as well make the active area larger and run it as a normal detector.

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message-1507867581388816414

2026-05-23T22:07:26.228+00:00 — BreakingTaps (@polyfractal)

Content

better screenshot

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message-1507924020727644190

2026-05-24T01:51:42.415+00:00 — namibj

Reply/reference

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Can't you use pmos devices instead and not need the dnwell?
Also I still don't quite get where and how STI is litho'd. Like, what patterns/shapes even do that?

Also, https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_04.html says:
> Equi potential min space  0.86V

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message-1507925277055914146

2026-05-24T01:56:41.947+00:00 — namibj

Content

Also maybe look at https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_07.html it feels like you may be doing things similar to those restrictions depending on biasing conditions?

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message-1508120352901959830

2026-05-24T14:51:51.653+00:00 — BreakingTaps (@polyfractal)

Content

Hmm I'll need to double check, but I don't think a normal pmos device would give the floating p-body that's needed. It'd be an nwell in the psub, and then p+ contacts
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message-1508120558665990296

2026-05-24T14:52:40.711+00:00 — BreakingTaps (@polyfractal)

Content

need to look into that equipotential thing, not sure how it's calculated. Would be great to use that spacing! I think because all the floating p-body sections are isolated, they are considered at different potentials by the DRC? not sure
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message-1508133206363471964

2026-05-24T15:42:56.157+00:00 — namibj

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No I mean like, the photodiode works regardless of whether it's illuminated from the P-side or the N-side, right?
Voltages flip, sure, but I'd not think you'd need particularly high performance transistor channels in those pixels so that's not on it's own at least reason to go for N-channel device.
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message-1508134661497290783

2026-05-24T15:48:43.088+00:00 — namibj

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Well I'm pretty sure it's (only) a latchup concern; I'd guess this might cause charge-spillover to adjacent cells similar in visual effect to what we remember from old CCD digital cameras.

Xyce has 2D TCAD on hand you could use to model the latchup behavior.
I guess the biggest hurdle would be that it's potentially gonna blow the 4-electrode limit in their code.

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message-1508135040695926846

2026-05-24T15:50:13.496+00:00 — BreakingTaps (@polyfractal)

Content

Ah I misunderstood. Yes, N or P is fine, although P is preferred because hole accumulation is (apparently) better for imaging. less noisy I think?

But the main thing is that it needs a floating/isolated body of the diode. Light passes through the poly gate, creates electron/hole pairs, the electrons are swept away to drain and the holes remain which then alters the IV curve of the transistor when it is read out. That's how they get a "3T" pixel with one transistor, it acts as integration, readout and reset all in one. But needs the floating/isolated body to do it
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message-1508135227438923879

2026-05-24T15:50:58.019+00:00 — namibj

Content

1 source, 2 gate, 3 drain, 4 substrate, (maybe 5 next_drain), 5 next_gate, 6 next_source
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message-1508135436923568261

2026-05-24T15:51:47.964+00:00 — BreakingTaps (@polyfractal)

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I was a little confused why it was codified in DRC, it seems like a functional problem but not really a design rule / layout issue 🙁
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message-1508136863909675140

2026-05-24T15:57:28.184+00:00 — namibj

Content

> One should notice that in readout mode, some stored holes are displaced under the source due to shrink of charge storage region under the gate and source potential lowering. This shift of the charge storage region to the source and toward the pixel edge should be stopped to avoid electrical crosstalk. One solution to the problem is to employ STI (shallow trench isolation), as shown in Figure 2. It was adopted in our first design configuration.
Yeah I for one don't quite get where the electrodes are in Fig.2 🙁

Have you considered asking those researchers?
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message-1508137149160230972

2026-05-24T15:58:36.193+00:00 — namibj

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Me when I look at one too many sky130 DRC's again and go _huh...._

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message-1508137259025694730

2026-05-24T15:59:02.387+00:00 — namibj

Content

[insert villager sound effect]
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message-1508137372318044361

2026-05-24T15:59:29.398+00:00 — BreakingTaps (@polyfractal)

Content

might give them a ping! can't hurt
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message-1508137475355443462

2026-05-24T15:59:53.964+00:00 — namibj

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worst case they don't answer
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message-1508137560617123952

2026-05-24T16:00:14.292+00:00 — namibj

Content

well, worst worst case they snipe your slot on Run2 😄
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message-1508260092594622636

2026-05-25T00:07:08.192+00:00 — nmz787

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At work we definitely have some DRs that are just for electrical "dummyproofing", and since my team draws mechanical and litho designs, we often get waivers for some of those rules
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message-1508260383562006538

2026-05-25T00:08:17.564+00:00 — nmz787

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However we also can ask the process integration owners and ask questions like "how does the STI actually get patterned" if we're confused or just curious
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message-1508260600273436876

2026-05-25T00:09:09.232+00:00 — nmz787

Reply/reference

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I need that GDS3D isometric view
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message-1508260751381630976

2026-05-25T00:09:45.259+00:00 — nmz787

Content

After 5 years drawing OASIS/GDS... I still get confused over all these layers on top of layers
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message-1508260961054884001

2026-05-25T00:10:35.249+00:00 — namibj

Reply/reference

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same sadly KLayout PDK only has that for sky130A (and maybe ihp I don't know), not gf180mcuD 🙁
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message-1508261057469091892

2026-05-25T00:10:58.236+00:00 — nmz787

Content

It's easy (ish) to make a layerstack
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message-1508261492829589625

2026-05-25T00:12:42.034+00:00 — nmz787

Content

I should really publish my layerstack generator helper... basically just a CLI that takes the list of layers, already arranged in order in a text file, and asks you what Z and how thick you want it... And accumulates your overall height to the next Z default entry (in case you have two layers at the same Z, like the diffusions)
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message-1508261735180669001

2026-05-25T00:13:39.815+00:00 — nmz787

Content

Although I'm sure pointing AI at the existing gds3d layerstacks as examples and asking it to generate the helper I just said, would do it in one or two prompts
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message-1508261977821286470

2026-05-25T00:14:37.665+00:00 — nmz787

Content

I believe I already have a gf180 prop file for gds3d, but am not on my PC right now
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message-1508262778291621909

2026-05-25T00:17:48.512+00:00 — namibj

Reply/reference

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feed it the https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html and https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3_30.html

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message-1508263875508834374

2026-05-25T00:22:10.109+00:00 — nmz787

Reply/reference

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Need the dl;dt too, I think there's a layermap for klayout that I'd start with, but those images would be good to finish the details!
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message-1508264052260868240

2026-05-25T00:22:52.25+00:00 — namibj

Reply/reference

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Sure
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message-1508768433511071826

2026-05-26T09:47:06.111+00:00 — tnt (@246tnt)

Content

https://discord.com/channels/1009193568256135208/1015911926053740544/1508755468275814470
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message-1508768536435101796

2026-05-26T09:47:30.65+00:00 — tnt (@246tnt)

Content

TT will be running an experimental slot in run2 for analog designs. See above for details.
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message-1508825467334033409

2026-05-26T13:33:44.034+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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KLayout has some type of cross-sectioning mode - https://klayoutmatthias.github.io/xsection/

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message-1508925728983351426

2026-05-26T20:12:08.274+00:00 — namibj

Content

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_05.html

I think I'm doing everything right, taking a `nmos_06v6_nvt` PCell that I confirm next to the DUT extracts just fine through magic, and _deleting just the dualgate layer rectangle_ on the DUT copy of the (all flattened) PCell structure, but magic doesn't spell complaints and the DUT just won't spawn in the extracted SPICE?
I also have a tiny `nmos_03v3` and I just confirmed that deleting also the NAT box on the DUT makes it extract as the plain `nmos_03v3` it's then expected to extract as.

Do we or do we not have those available at the GDS level?

I can understand (with much unhappyness) if there's no design support (LVS, other extraction, spice, xschem, etc.), but otherwise I'd quite very like to know where I would have been supposed to read about us explicitly not having `nmos_03v3_nvt`.
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message-1508935131266682941

2026-05-26T20:49:29.953+00:00 — bailey (@bailey8889)

Reply/reference

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Maybe `grep _nvt $PDK_ROOT/gf180mcu/libs.tech/ngspice/*`
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message-1508938134195404958

2026-05-26T21:01:25.907+00:00 — tnt (@246tnt)

Content

I guess you can tape one out and measure it and see if it actually works.
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message-1508938534185205850

2026-05-26T21:03:01.272+00:00 — namibj

Reply/reference

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That's my fallback.
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message-1508983039957401771

2026-05-26T23:59:52.275+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I *believe* the GDSFactory people are hoping to do some test circuits to do some verification circuits.
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message-1508983529722351656

2026-05-27T00:01:49.044+00:00 — namibj

Content

@Thomas Pluck 2.1 `nfet_03v3_nvt` misses models and currently even extraction; it's only implied from some DRCs to exist. Etest if any of that happens would be _awesome_ to capture.
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message-1509140666956120154

2026-05-27T10:26:13.48+00:00 — namibj

Reply/reference

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Oh and if anyone etests that one, don't only do L=1.8, go down towards the L=0.28.
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message-1509202645691138121

2026-05-27T14:32:30.362+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1509228331281813665

2026-05-27T16:14:34.284+00:00 — Thomas Pluck 2.1 (@tpluck_)

Reply/reference

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Plan was that we can generate test structures on a left over Run 2 half slot right?
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message-1509229152761417888

2026-05-27T16:17:50.14+00:00 — Thomas Pluck 2.1 (@tpluck_)

Content

No sense wasting a creative TT slot on device characterization.
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message-1509286622796058817

2026-05-27T20:06:12.064+00:00 — Tim 'mithro' Ansell (@mithro_)

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Correct!
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message-1510078451703480472

2026-05-30T00:32:38.787+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - You might find https://docs.google.com/presentation/d/e/2PACX-1vS2jJzvahcR7M6YPl6omPSDk7ZW6sFhqpsh4mxRzwc5JhHkUPudI62qpevA1WWu2g/pub?start=false&loop=false&delayms=3000 interesting.

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message-1510126061336399902

2026-05-30T03:41:49.808+00:00 — Andrew Wingate (@anfroholic)

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That's a private repo
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message-1510160444483174561

2026-05-30T05:58:27.389+00:00 — Tim 'mithro' Ansell (@mithro_)

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I think that fixes it?
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message-1510160697290653897

2026-05-30T05:59:27.663+00:00 — Andrew Wingate (@anfroholic)

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Yes, fixed
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message-1510338684510146622

2026-05-30T17:46:43.123+00:00 — BreakingTaps (@polyfractal)

Content

ooh neat, thanks for the ping!
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message-1510356928310546563

2026-05-30T18:59:12.784+00:00 — namibj

Content

Oh yes thanks for the link.
If anyone has a link to how that LLM assitance there happens to be practically usable, I'd appreciate to see if it appers to be effective for my MCML efforts that way.
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message-1510747067734036540

2026-05-31T20:49:29.271+00:00 — tnt (@246tnt)

Content

I need a quick&dirty current reference. Nominal would be 30 uA at 3.3V but should be usable at 5V and acceptable range would be 20~60 uA. Anyone got something easy to propose ? 😅
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message-1510766238761095271

2026-05-31T22:05:40+00:00 — Dory (@dorythecat_v2)

Content

Attachments

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message-1510766407187562676

2026-05-31T22:06:20.156+00:00 — Dory (@dorythecat_v2)

Content

ive used this circuit before and on a punch it's good enough
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message-1510766492013297675

2026-05-31T22:06:40.38+00:00 — Dory (@dorythecat_v2)

Content

otherwise, a high enough voltage and a high enough resistor should work
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message-1510766605993246720

2026-05-31T22:07:07.555+00:00 — tnt (@246tnt)

Content

I meant an on-chip reference ... you can't make zener in gf180mcu
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message-1510781231346749555

2026-05-31T23:05:14.511+00:00 — Thomas Dexter (@tdextrous)

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Started a thread.
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message-1510896491609325598

2026-06-01T06:43:14.699+00:00 — Dory (@dorythecat_v2)

Content

Ah sorry I'm dumb then 😭
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message-1510896575948394627

2026-06-01T06:43:34.807+00:00 — Dory (@dorythecat_v2)

Content

Though you could probably still try with a double transistor constant current source
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message-1510896621485948938

2026-06-01T06:43:45.664+00:00 — Dory (@dorythecat_v2)

Content

I don't have any schematics available rn but they shouldn't be hard to find
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message-1511832215779151912

2026-06-03T20:41:28.726+00:00 — namibj

Content

We don't by chance have any decent inductors let alone mutual ones available, I guess?
I'd hope to use some gain peaking on the clock buffers, they aren't _that_ sensitive to precise inductor performance and honestly need so much parasitic resistance anyways that they can have fairly terrible Q so long as they are still very inductive (not capacitive) at the peak operating frequency.

I think I'd mostly want them to sustain higher fan-out than what I'd be having sufficient-margin-above-unity gain with at whatever frequency I can squeeze out of the latches feeding MUX2's feeding the output buffers (final latch stage clocked at half the output bit rate, just like the output MUX2 that converts from 2 parallel SDR streams to the final singular DDR (NRZ) stream).

And possibly even not using a latch on the full clock but rather a 4:1 MUX tree with selective clock phasing on the 3 involved selector bits and the 4 latches feeding directly into the input muxes.

I'll try to get a basic (inductor-free) setup going in the coming hours to figure out if 10 Gbit/s is just wishful thinking or just an issue of thermal density/chip-cooling.
fT of 25GHz at feasible drain current and low-frequency gain sounds like a mere 5 GHz fundamental with desire for clipping to be more square wave than sine wave shouldn't be _that_ bad to handle, that sounds like FO2~FO3 territory after basic parasitics...
Sure it's _intense_ but in theory only a DIV2 and a MUX2 have to be driven at the full speed from the VCO and the MUX2's output has to go to an output buffer.
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message-1511879419852226701

2026-06-03T23:49:03.054+00:00 — BreakingTaps (@polyfractal)

Content

I don't think I've seen anyone post an inductor layout yet. Would probably have to DIY one with GDSFactory's spiral loop generator or something? And then sim it to see how works 😕
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message-1511883505611571260

2026-06-04T00:05:17.175+00:00 — namibj

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Yeah that fasthenry script https://github.com/diadatp/sky130_rf_tools/blob/main/fasthenry/iterate_fh.py should port decently to gf180mcuD, but that's half-finished work (like, for sky130) and not particularly what I quite have time to work on in these rather limited days until the ttgf0p3 deadline.

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message-1512068246294233088

2026-06-04T12:19:22.786+00:00 — namibj

Content

Now that I've done some _Gain-Bandwidth Product_ maths I _really_ want some T-coil's for bandwidth enhancement.

I low key have trouble believing these numbers, for that they suggest it's _technically possible_ to yeet a lane of `25GBASE-KR-S` out of a wafer.space die without necessarily melting said die as long as one ensures good cooling.

Without effective inductive peaking it's gonna involve rather lifetime-limiting hot carrier injection conditions, though, as the `nfet_3v3_dss` probably won't quite reach enough native GBW.

Yes I'm aware that prospect sounds kinda ridiculous.
I'm just getting the numbers/down-clocking-support cooked a little more before I go see how to get anywhere close to the abstract numbers I've been looking at since last night.
Even if that's too much it does suggest `10GBASE-KR` to be actually quite realistic to pull off (even post-layout).
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message-1512185477166534677

2026-06-04T20:05:12.804+00:00 — namibj

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Ok welp I'm not attempting a C4 serializer, yet without C4 (i.e., mere C2), 25GBASE-KR-S would probably risk melting the gf180mcuD die.

Does not seem impossible though...
Might need flip chip though due to severe high frequency impedance of the bond wire.

10GBASE-KR with "only" a C2 architecture looks worryingly "easy" (decent limiting amplifier GBW, no peaking inductors needed, C2 doesn't need any ultra-fast 4:1 MUX unlike C4 (they're tricky to correctly common-mode bias), and overall it might not need _any_ bandwidth extension trickery to function.)....
Hopefully I can be productive Saturday and do some trial layouting for the critical blocks of concern.
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message-1512430287647412295

2026-06-05T12:18:00.171+00:00 — RebelMike (@rebelmike)

Content

Does anyone have a PLL that’s in a state I might be able to use it in my design?
The goal would be to drive HDMI output so I’d want to generate a 126MHz clock.
I’m going to have an option to bring that clock in externally, but it would preferable to be able to run without such a fast external clock.
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message-1512470734847348797

2026-06-05T14:58:43.535+00:00 — dmv (@.dmv)

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Looks like there was a PLL in the ISHI-KAI run1 design.
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1#PLL
Although it went 8 MHz in -> 48/40MHz out, and unclear if the die has been probed yet.

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message-1512472936618004591

2026-06-05T15:07:28.478+00:00 — RebelMike (@rebelmike)

Reply/reference

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Good find, thanks for the link!
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message-1513184279360700416

2026-06-07T14:14:05.804+00:00 — namibj

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Not for Run2; but I plan to have something who's core is silicon validated for Run3.

Provided my health can get in line today so I can at least get basic core parts drawn today.

An amplifier, a partial positive feedback delay cell for the VCO, and a very fast MUX2.

Thanks by the way for giving me a clear purpose of what people might reasonably do with the fast TX I'm working on: digital video out.
That works TX only with less than 10Gbit/s for general homelab hardware.
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message-1513186540375900291

2026-06-07T14:23:04.872+00:00 — namibj

Content

That said, if I manage to get the PBRS hooked up I'd have a few days after the ttgf0p3 deadline to help you hook the serializer design up to your date source, at probably 32 bit wide (3v3 SCL) per clock.

I'd think a TDMS encoder shouldn't be that hard, and it should be easy to make 4 copies of it fed from a single shared VCO.

It'd be 4 control current signals plus a differential pin pair for each line.
But those could use the ttgf analog MUX.

PLL action would have to be done off-chip by adjusting the tail current for the VCO.
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message-1513193511548227644

2026-06-07T14:50:46.929+00:00 — RebelMike (@rebelmike)

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Content

Interesting.  I just finished using up all the pins on the quarter slot 😄  But potentially I could free some back up.

Serialization wise I'm using https://github.com/Wren6991/SmolDVI, and have a super simple stateless TMDS encoder that is only capable of 2bpp on each channel, which is enough for now, and the 8 pins can instead be used for 2bpp/colour VGA output (TT VGA Pmod compatible) if HDMI is not selected (also gives me a fallback if HDMI doesn't work).
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message-1513193875488116970

2026-06-07T14:52:13.699+00:00 — namibj

Reply/reference

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Content

honestly for Run3 I'd suggest to aim for a lane of DP; by then there's decent chance all the biasing for my serializer could live on-die, too.
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message-1513194969718853853

2026-06-07T14:56:34.584+00:00 — namibj

Content

notably by then I should have managed to get at least a few taps of TX FIR EQ working.
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message-1513198205255291032

2026-06-07T15:09:25.996+00:00 — RebelMike (@rebelmike)

Content

DP would be cool!  I'll probably keep things simple for run 2 and then see if there's interest in putting something DP or faster HDMI together for a later run.
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message-1513202066657644745

2026-06-07T15:24:46.626+00:00 — namibj

Reply/reference

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Yeah I'm decently confident in the TX being good enough for it; I don't see myself being able to supply the encoder though.
I do have decent hope for DP 1.3's HBR3 though, but probably not with anywhere near full cable length in practice.
That is 30 fps per lane at 3840x2160, though....
If we can get a performant flip chip strategy measured long enough before Run3's deadline, spec-compliant drive might be possible, though.
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message-1513204904230129704

2026-06-07T15:36:03.156+00:00 — RebelMike (@rebelmike)

Content

I've done a fair amount with VGA and DVI/HDMI, but haven't touched DP, so not sure what's required for the encoder.
I guess I remain sceptical about getting anything like that speed, but then I haven't actually got my hands on any gf180 chips yet.  On sky130 though the output drivers in the default padframe TT uses are really weak - you struggle to get a clean signal above 33MHz.
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message-1513205563830440047

2026-06-07T15:38:40.417+00:00 — namibj

Content

If I get far enough to where the serializer takes some shape on track for getting finished by the deadline, you are free to make the digital feed for the serializer, it's gonna have a couple bits (10~20) of VCO load trim to select a choosen number of PMOS fingers to connect the VDD side of the pull-up-resistors to VDD, some way of setting straight alternating bit pattern to output clock signal instead of data, and probably some way of turning off the output of the divided clock onto the GPIO.
Otherwise, it'd be free to select itself a mode where it takes in 16 bits of GPIO parallel if feasible as DDR even, and feed them to the serializer core instead of feeding the PRBS-31 to it.
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message-1513205873420402799

2026-06-07T15:39:54.229+00:00 — namibj

Content

There's approximately half a normal tt tile space for all the digital stuff.
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message-1513206426015633558

2026-06-07T15:42:05.978+00:00 — namibj

Content

I do feel like I'l get to draw the amplifier (as needed for fan out in general) at least today, tho.
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message-1513208529131929750

2026-06-07T15:50:27.4+00:00 — namibj

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If I've made enough progress in 7 days, I'd welcome you to make a digital SCL section for feeding the analog core with either PRBS-31 or notably a 16-wide input that might as well be DDR w.r.t. the exported GPIO clock.
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message-1513208844044472351

2026-06-07T15:51:42.481+00:00 — namibj

Content

Would allow testing of DP transmission with an external encoder and external PLL.
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message-1513218610275815484

2026-06-07T16:30:30.932+00:00 — RebelMike (@rebelmike)

Content

Generating PRBS31 looks straightforward - are you targetting TT gf0p3 for this?
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message-1513233015201861802

2026-06-07T17:27:45.334+00:00 — namibj

Content

yes
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message-1513233629726249102

2026-06-07T17:30:11.848+00:00 — namibj

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This is more about that I won't have time to do a digital section that can re-use the 16 normal user inputs for data feed, so to get that, I'd be calling upon help/offering collaboration on that aspect after getting the base core part into a state where it is clearly realistic to get to actually have a functioning data serializer component.
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message-1513235954322636991

2026-06-07T17:39:26.075+00:00 — RebelMike (@rebelmike)

Content

Yes, understood - and I'm much more familiar with the digital tooling than the analog side of things.  This should implement ```
module prbs31 (
    input wire          clk,
    input wire          rst_n,
    input wire          en,
    output reg  [30:0]  q
);

    always @(posedge clk or negedge rst_n) begin
        if (~rst_n) q <= '1;
        else if (en) begin
            q[0] <= q[30] ^ q[27];
            q[30:1] <= q[29:0];
        end
    end

endmodule
```
is that roughly what you're after?

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message-1513236128239456406

2026-06-07T17:40:07.54+00:00 — RebelMike (@rebelmike)

Reply/reference

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Started a thread.
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message-1513391093230604348

2026-06-08T03:55:54.073+00:00 — namibj

Reply/reference

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unfortunately that tool so far seems rather reluctant in giving me blocks that are closer to custom drawn than those fully-automatic fire-and-forget "with dnwell + with guard ring + with substrate tap + oh-yeah-source-and-drain-have-to-come-out-the-same-side" 🙁

Seems a little problematic so far due to having to keep an eye on electromigration limits due to transistors driven into very fast not efficient regimes.
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message-1513391431060947054

2026-06-08T03:57:14.618+00:00 — namibj

Content

I'll sleep over it to make the judgement call of whether to continue going with this for now or whether to go for other basic-multifinger-structure-drawing code.
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message-1513398039488761866

2026-06-08T04:23:30.19+00:00 — namibj

Content

ok I gotta confirm with proper PEX but if the model already includes the parasitic capacitance of the finger contacts that's not really avoidable anyways, then that 25GBASE-KR TX seems actually not that infeasible without having to do inductors even, though those would help a lot in power efficiency.
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message-1513400215703523409

2026-06-08T04:32:09.04+00:00 — namibj

Content

2 nH on 10x10 um with access to m2/m3/m4.
Particular gain needed at about 13~15 GHz.
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message-1514544476788621403

2026-06-11T08:19:02.142+00:00 — Thomas Pluck 2.1 (@tpluck_)

Content

FYI, 6 Danube River characterisation chips have arrived at UC Irvine to be probed.

Would be good to know what other test-structures people would like to prioritise/characterise and just how much free-space we'll have on run two try out for the community.
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message-1514732227244851390

2026-06-11T20:45:05.339+00:00 — namibj

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native NMOS both oxides in a way that somehow allows for extracting local mismatch models, with channel dimensions down to litho minimums, not just electrically suggested ">=1.8um, or it'll _leak too much when off_" restrictions that are currently enforced by the SPICE model deck in the openPDK.

Perhaps some way of stress-testing SiN passivation crack propagation susceptibility when insisting on keeping the guard ring metal passivated, such that ACF-style (and/or similar) cheap flip chip packaging will be easy to select as a padframe "option" with hopefully just minor yield impact if one decides to just go for CoB wire bonding instead? Could be nice to combine with some M5-and-up-only (except perhaps a bit of vias down to redistribution/cross-connecting traces below) flip chip bond pad pitch/"resolution" stress testing structure that'll shoot allow us to trial on actual dies how the pad-connected-well-enough/not-shorting-nets yield relates to pad density.

If the DRC checks won't aggressively stop us, someone might be up to draw up a couple thyristors and/or triacs. Triggered crowbars are quite helpful for being able to clamp excess (e.g ESD) voltage without being beholden to the inherent limitations of single-junction plain pn diodes, such as not having to rely on the presence of a low-impedance VDD to sink current into, but instead being able to "just" turn on a strong bipolar "open-collector"-like output "driver" that can even clamp to below VDD  if one e.g. uses thin oxide inputs for low voltage signaling standards that operate with peaks substantially below system VDD. Imagine using a series inductor to tame the ESD pulse enough to not current crowd (excess `dI/dt` causing localized overheating) the thyristor/bipolar clamp but otherwise using the inductor to fairly effectively match the input gate capacitance of the transistor to the output/port nominal impedance. As opposed to massive passive diodes to rails together with dumb lossy ohmic series resistors.

Also: https://ieeexplore.ieee.org/document/7937877 (JFET in what looks like a very plain 250nm CMOS process) / https://www.semanticscholar.org/paper/A-JFET-CMOS-Technology-for-Low-Noise-Sensor-Takao-Asaoka/7aac24f59d2ac537ed6eed35a17e6ac8b60f1a5b (JFET in what sounds possibly less-plain CMOS and from the few numbers I could read due to language barrier, sounding like 700 nm CMOS) / some attempts at CCD structures, those all sound nice to trial at least a little bit when we're already working an area that's not "production suitable chips" and is expected to be fed to a probing station.

From my rough understanding, it should probably be possible to trick the litho steps (normal used for fabricating some of the accessible mosfets) to form "functional" CCD structures.
Not like, _good,_ but c.f. _Reticon SAD-1024_ like CCD structures don't need to worry about photoelectric optimization beyond "better put it in an opaque package".
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message-1515621648479551648

2026-06-14T07:39:19.886+00:00 — Vipul (@vipul.sh)

Content

For layout,drc, lvs for analog with gf180, what is the recommended flow, Klayout or magic?
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message-1515650076645523457

2026-06-14T09:32:17.689+00:00 — Leo Moser (mole99) (@mole99)

Content

The wafer.space precheck uses Klayout DRC. However, if you pass magic DRC, it is very likely that you will also pass KLayout DRC.

As for the layout, it depends on your preference. I think most designs currently being made are using magic. The KLayout PCells for gf180mcu use GDSFactory and are a bit spotty. Regarding LVS, you can either use magic+netgen or LVS with Klayout, which has recently been improved.

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message-1515713521885647091

2026-06-14T13:44:24.213+00:00 — tnt (@246tnt)

Content

So a bit of a question of interpretation for the PDK : Is `Vn.2b` meant to apply to vias attached to different metal  zones ?
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message-1515713556157300746

2026-06-14T13:44:32.384+00:00 — tnt (@246tnt)

Content

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message-1515713738412523582

2026-06-14T13:45:15.837+00:00 — tnt (@246tnt)

Content

i.e. should it apply to the above ( from a MOM cap )
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message-1515714002309611640

2026-06-14T13:46:18.755+00:00 — tnt (@246tnt)

Content

The diagram in the PDK shows them on the same metal but other than that, is not explicit in any way.

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message-1515714188683640852

2026-06-14T13:47:03.19+00:00 — tnt (@246tnt)

Content

The current KLayout deck reports an error. But the current magic techfile generated those vias. I'm not even sure if it would be possible to get magic to realize there is an array there ...
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message-1515750593379958839

2026-06-14T16:11:42.746+00:00 — bailey (@bailey8889)

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Started a thread.
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message-1516079486813339770

2026-06-15T13:58:37.051+00:00 — namibj

Content

I have this basic (well, technically, the PMOS are arranged differently for speed reasons) "ring oscillator" cell; there's 2 of these cells back-to-back acting as a direct quadrature phase clock source, albeit with naturally limited slew rate.

Is there any reason not to make it as big as necessary to directly tap all the clock feeds off of it, especially if I want to use the quadrature clock feeds in similar source-coupled "differential nmos pairs" logic?
Vs. a more "proper" clock tree, at least if this is contained to a single serdes channel worth of area?

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message-1516863290884751362

2026-06-17T17:53:10.504+00:00 — Thomas Pluck 2.1 (@tpluck_)

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Content

We (me @ GDSFactory) actually recently updated these to be XOR clean replicas of the Magic ones - so it should ideally be *stable-r* but naturally, buyer beware.
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message-1520008973795983512

2026-06-26T10:12:59.754+00:00 — dmv (@.dmv)

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Started a thread.
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message-1521885730278867087

2026-07-01T14:30:33.368+00:00 — namibj

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message-1521893037528055829

2026-07-01T14:59:35.552+00:00 — namibj

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Content

@BreakingTaps perhaps you'd come up with info on the matter of photovoltaic mode operation of cells; particularly on the subject of whether multiple photodiodes in photovoltaic mode can be series connected to produce sufficient voltage for CMOS logic; I'd have ideas based on native nmos that wouldn't require more than the 500~700mV to operate but they're all unfortunately large structures due to the unavailability of any pmos devices with threshold voltages "reasonably below" diode forward voltage.

I'd guess there are some available (on gf180mcuD) tactics for bootstrapping a charge pump voltage booster from a singular solar cell?

Maybe substrate-tied dnwell with an lvpwell-to-dnwell photodiode (producing positive voltage relative to substrate) acting in series with a separate (d)nwell-to-psub diode (producing negative voltage relative to substrate) could work.
The negative bias could allow biasing pmos devices to act as resistors for native-nmos devices doing the actual logic, which would massively shrink the area requirements for the logic and probably also comfortably stabilize operating reliability against process variations in native nmos threshold voltage.

No good idea yet about back channel though; forward channel is obvious through just sufficiently deep amplitude modulation of the light, some probably-MIM storage caps for logic voltage supply, and some dynamic logic kind of data demodulator.
Or if there's two beams available obviously just either differential signaling with some kind of clock recovery or a synchronous clock-and-data interface.

My goal is btw. to get a PUF-like structure that can be read out at the die sorter without needing to touch the bond/probe pads during this, to later post-packaging read the same PUF-like from digital logic, being able to match against the database the die sorter created, getting to look up what coordinates on which wafer that die came from. Or realistically just what reticle on which wafer (it's far cheaper to just encode the intra-reticle location with a few bits of mask ROM structure).

I'm aiming towards enabling full traceability that way; if one wants easier IDs one can just put efuse PROM onto the die and burn these coordinates and other tracing information during the first post-packaging e-test of the die, just as part of the test pattern interaction; might require some scripting there but shouldn't be too involved for a vaguely flexible tester platform.
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message-1521894788868210770

2026-07-01T15:06:33.104+00:00 — namibj

Content

Oh, NFC-style with on-die inductor comes to the mind as well, just now!
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message-1521894822271647836

2026-07-01T15:06:41.068+00:00 — namibj

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Content

@Tim 'mithro' Ansell
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message-1521907493809164439

2026-07-01T15:57:02.198+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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hmm, I do recall reading a paper some years ago about an image sensor that was self-powered. I forget the scheme exactly but it basically toggled between energy harvesting and image capture. so in principle it's probably doable.  will see if I can find the paper...
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message-1521944517752655882

2026-07-01T18:24:09.394+00:00 — namibj

Reply/reference

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Hmmm; the NFC idea that came right after I sent that wall-of-text (it's technically the immediately following message in this channel) does feel somewhat more applicable right now at least; if using top metal for the resonant inductor of it and de-tuning by switching a cap into/out of the tank or even just modulating the load it puts onto the tank via some kind of like shunt/series combo LDO regulator, or literally shorting out the tank (with sufficiently limited duty cycle ofc.):
some way probably has enough intensity in the back channel to make it not require high specs from the reader.
After all, for reasons of getting by with a compact coil and not having the global PDN ring enclosing the "regular user area" of the die wreck the Q of the resonant tank, I'd expect this to effectively-need a near-field H-field antenna. probably set up to sweep the frequency band of interest until it hits evidence of exciting the receiver's resonance (process variations cause some shift in resonant frequency), perhaps in a shape of a narrow gap between two coils thick enough for the die to slide into and deep enough to reach in just past the pad&PDN ring, or even just a more-pointy-tip "loop antenna"/H-field-oscilloscope-probe roughly visually aligned to and pointed close to but not touching the die by where that die has it's NFC-antenna.

Light clearly has the benefit of less risk of accidentally scratching the die and not worrying about EMC compliant operation of the reader, but I'd assume a back channel to be FAR more difficult to pull off than just using simple well-trodden NFC tech.

[||If I knew of a low-cost source for single-emitter variants of the triple-emitter https://ams-osram.com/products/lasers/ir-lasers-vcsel/osram-bidos-e1005-l-plpvyl1-940a-e , I'd be far more hopeful in possibly making optically powered bootstrapping (coupled through a simple multimode fiber) a silicon-proven thing on not-my-dime (well, as far as the tapeout masks for the process of silicon-proving the bootstrap mechanic goes)....

...as that should be readily usable for bootstrapping any design variants of the switched-capacitor based MVDC-tamer plans (which I have _not_ given up on bringing towards a hands-on PoC demonstrator). Like, charging the local LV supply capacitors through optically provided power while the higher-voltage supply is not yet connected, as they later harvest from the resonant EM fields once in operation, and it's not necessarily easy to inject such "RF" power and not even necessarily feasible to bootstrap off of that due to the harvesting architecture that's preferred for steady-state possibly requiring synchronous rectification or switching of the power transistor.

E.g. one could have a rectification diode from the harvesting node into the local storage capacitor, a capacitor from that node to the high-voltage drain node of the power switch, and a low-loss clamp shunt transistor that can ground the harvest node to the power transistor's source which also acts as the local ground.

...errr, the last bit of thinking I allotted to the matter this week just revealed that if the power switch has automatic reverse diode behavior for the drain node, it would probably be safe to use this particular harvesting architecture as the voltage amplitude during bootstrap procedure is limited by the drain to-source capacitance (including the harvesting capacitor's contribution) and the bootstrap current amplitude, while the power drain-source leakage even if little prevents the drain voltage from building up much beyond the previously given implied peak-peak voltage amplitude, as long as it exceeds bleed-to-environment enough, and reverse voltage is clamped by the drain-source diode of the power switch....
||]

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message-1521953520352231425

2026-07-01T18:59:55.781+00:00 — RRichmondR (@rrichmondr)

Content

Hi everyone, is ti possible to change the IO configuration on the chip ? for example the full tie list 56 (bidir: 40, in: 14, analog: 2), could we add more analogs ? and still get the chip on board packagin ?
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message-1521954907907817482

2026-07-01T19:05:26.6+00:00 — Andrew Wingate (@anfroholic)

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Yes @RRichmondR you are able to change any of the io pads to whatever you wish. With the cob the ground nets will be shorted and the power traces (currently) have decoupling caps.
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message-1521957940041617502

2026-07-01T19:17:29.517+00:00 — RRichmondR (@rrichmondr)

Content

and is there any information regarding the max io speed  on the digital ones ? i couldn't find anything
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message-1521968788877213846

2026-07-01T20:00:36.081+00:00 — RebelMike (@rebelmike)

Content

Sample size of 1, but on the Tiny Tapeout board I could clock the factory test design at up to 188MHz and it would work correctly.  On the output side I don't have a good enough scope but the drivers are pretty strong - they still seemed pretty good at 100MHz

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message-1521971337126744065

2026-07-01T20:10:43.631+00:00 — tnt (@246tnt)

Content

They're actually a bit too strong ... so if you wiring isn't up to par you get quite a bit of ringing due to the fast edge, so much I actually got some double clocks on spi lines in some conditions.
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message-1522398205340553226

2026-07-03T00:26:56.944+00:00 — namibj

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what happened if you went a little beyond that speed? Minor amount of swalloed clocks? Minor excess count? Sudden breakage? No faster quality clock source on hand to try to feed in and see if it can go faster?
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message-1522506709422047394

2026-07-03T07:38:06.333+00:00 — RebelMike (@rebelmike)

Content

Seems like sudden breakage, when I’ve run this test before on sky chips it’s normally shown one missing count, then two before breaking down. But here it suddenly starts missing lots of clocks. Unfortunately two variables have changed at once though because TT has moved to a new demo board with mezzanine connectors so I can’t test in my old setup, and the demo board has a possibly non-ideal debounce circuit for the manual clock button hanging off the clock line.
Update though, I tried a higher drive strength from the RP2350 that’s generating the clock and got up to 220MHz ok (again sudden breakage at 224MHz)

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message-1523708254683795496

2026-07-06T15:12:37.047+00:00 — tnt (@246tnt)

Reply/reference

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Content

Started a thread.
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message-1524427820720328754

2026-07-08T14:51:54.959+00:00 — Olle (@osvel)

Content

What's your preferred workflow for analog / mixed circuits? I'm currently trying out xschem + ngspice, but have a hard time to load the gf180mcuC pdk lib properly.
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message-1524535424821891246

2026-07-08T21:59:29.776+00:00 — bailey (@bailey8889)

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@Leo Moser (mole99) is wafer.space using gf180mcuC as opposed to gf180mcuD?
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message-1524536182028107947

2026-07-08T22:02:30.308+00:00 — Olle (@osvel)

Content

Sorry, typo by me! 🙂
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message-1524540578702954597

2026-07-08T22:19:58.557+00:00 — Leo Moser (mole99) (@mole99)

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Nope, gf180mcuD :)
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message-1525887844772483132

2026-07-12T15:33:31.819+00:00 — namibj

Content

Ok let's dig into the https://www.tinytapeout.com/news/mini-mosbius/ design files and find out if it can be almost-copy-pasted to gf18mcuD with just a bit of scaling to fit the AFAIK substantially less compact standard cell logic that I'm assuming to make up a large part of the configuration bitstream handling.

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message-1525971997501423796

2026-07-12T21:07:55.393+00:00 — RRichmondR (@rrichmondr)

Content

i have generated the padframe for our mix signal design.
my undesrtanding is that ill place on that gds our analog cells and then upload that gds to the platform am i right or am i missing something ?
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message-1526011624589365479

2026-07-12T23:45:23.227+00:00 — namibj

Reply/reference

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Pretty much?
That's one way at least.

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message-1526011784945991801

2026-07-12T23:46:01.459+00:00 — namibj

Content

There is a point where you need to connect your digital and your analog though.
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message-1526277182643634186

2026-07-13T17:20:37.201+00:00 — RRichmondR (@rrichmondr)

Content

the connection would i have to do it mannually right ? (i ran the drc on klayout and got errors on the IOs of the padframe not the design itself)
one friend is thinking about putting the analog cells as macros and let openroad do the routing
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message-1526311482843861153

2026-07-13T19:36:55.006+00:00 — namibj

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You can pre-route any critical analog connections in the flow with openroad picking up the reminder; @Tholin 's submissions AFAIK rely on the auto-route approach; not sure to what extent they've pre-routed any of the nets though.
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message-1526311953163882646

2026-07-13T19:38:47.139+00:00 — Tholin (@tholin)

Content

I didn’t know you could do this
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message-1526312389191139359

2026-07-13T19:40:31.096+00:00 — namibj

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It's like a power wire just less griddy
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message-1526350366084698204

2026-07-13T22:11:25.493+00:00 — Olle (@osvel)

Content

https://gf180mcu-pdk.readthedocs.io/en/latest/analog/model_parameters/LV/LV_9.html

Is this not part of the public release or is it just undocumented?
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message-1526353847247704084

2026-07-13T22:25:15.467+00:00 — Olle (@osvel)

Content

And one other question... People doing analog designs, are you using deep N-wells / guard rings? Are they really important? 🙂

I saw there was a klayout plugin for sg13g2 (https://github.com/mwolodzk/klayout-sg13g2-tap-guard-ring-plugin) for making these automatically around a selection (for instance when using matched pairs). Thought myself about copying this but using the rules from gf180_fd_pr

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message-1526359496803221706

2026-07-13T22:47:42.426+00:00 — namibj

Reply/reference

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Latter.
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message-1526360384020414576

2026-07-13T22:51:13.955+00:00 — namibj

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If you don't know better, go for them; our PEX flow(s) AFAIK still completely lack support for modeling substrate currents, so we can't "just" "simulate and see" if it behaves without the dnwell.
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message-1526458115833200671

2026-07-14T05:19:35.035+00:00 — Olle (@osvel)

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Good tip, thanks! 🙂 I guess I will use them then. :^)
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message-1526545581001150567

2026-07-14T11:07:08.356+00:00 — Olle (@osvel)

Content

Oh wait, are all 3.3v PCells totally broken? I have tried both in magic and klayout, both seem to produce illegal nfets (w = 0.36u l = 0.28u, nf=1), mostly regarding grid alignment. For example, the gate metal seems to be misaligned in klayout, but too small in magic.
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message-1526545838430486639

2026-07-14T11:08:09.732+00:00 — Olle (@osvel)

Content

Is no-one doing analog stuff using the builtin FETs from gf180_fd_pr?
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message-1526548572877619321

2026-07-14T11:19:01.675+00:00 — tnt (@246tnt)

Content

The metal in magic is too small area that's expected. That's because it's where you should be connecting your stuff to ... so area will get bigger when you actually wire it to something.

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message-1526548805934256189

2026-07-14T11:19:57.24+00:00 — Olle (@osvel)

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ok so its maybe just klayout then that is broken. It doesn't seem to properly align to the grid, which is a problem :^) Will try out magic for a while
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message-1526549286873989150

2026-07-14T11:21:51.905+00:00 — Olle (@osvel)

Content

I must say the grid/pixel based system feels nicer than the object based one in klayout
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message-1526550680066719835

2026-07-14T11:27:24.068+00:00 — tnt (@246tnt)

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Yeah, personally I prefer magic for layout too.  Other prefer KLayout, there is definitely some amount of subjective preference in there, you can make successfull layout in both and there will be things that work well and things that are a bit stickier with both.
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message-1526555503788953750

2026-07-14T11:46:34.133+00:00 — Olle (@osvel)

Content

hm.. `Metal1 spacing < 0.23um (M1.2a)`

This is before drawing anything.

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message-1526555944719224912

2026-07-14T11:48:19.259+00:00 — Olle (@osvel)

Content

Sorry, I'm a bit of a noob :^) I guess I can go into it and quickly fix it up?
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message-1526926130484088892

2026-07-15T12:19:18.423+00:00 — Matt Venn (@mattvenn)

Content

It's because it wants metal on top, without metal over the via you get this DRC
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message-1526943948495392860

2026-07-15T13:30:06.568+00:00 — were491 (@were491.)

Reply/reference

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o yea this wasn't an issue with dbu=0.005u so theoretically you can just design with that and then flatten everything before changing dbu back to 0.001u and then it won't be misaligned
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message-1526967638331494440

2026-07-15T15:04:14.665+00:00 — namibj

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Yeah I do question the sense of a dbu smaller than a mandatory minimum quantization/snapping grid.
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message-1526968280676569179

2026-07-15T15:06:47.812+00:00 — were491 (@were491.)

Content

gf180 pdk said to use 0.005 dbu but waferspace wants 0.001 for some reason
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message-1526969323787386931

2026-07-15T15:10:56.509+00:00 — Leo Moser (mole99) (@mole99)

Content

The dbu for gf180mcu is 0.001, the manufacturing grid is 0.005.
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message-1526969639534592010

2026-07-15T15:12:11.789+00:00 — Olle (@osvel)

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Good tip, will keep in mind! I decided to abandon klayout (for better or for worse) and just later import my design to do their DRC.
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message-1526970400825933927

2026-07-15T15:15:13.295+00:00 — Olle (@osvel)

Content

I figured out the issue in magic also. Seems like picking a too small L causes this. Should probably report it but its a design constraint so don't really know how the pcell generator should work tbh
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message-1526971358133751918

2026-07-15T15:19:01.535+00:00 — namibj

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Yeah; can you justify that choice beyond "it was picked many years ago and _nice round number_ and changing now would break too much"?
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message-1526972599068791014

2026-07-15T15:23:57.397+00:00 — tnt (@246tnt)

Content

The latter is quite a big concern 😅
For instance, I know in TT because we copy the stream directly when including macro to make sure we don't alter them, they need to all have the same unit or they end up at different scales ...
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message-1526993873463939226

2026-07-15T16:48:29.608+00:00 — namibj

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Tbf, scaling all coordinates by an exact integer factor while verifying no quantization errors happen is pretty tame risk-wise; but yeah.

I'm mostly just confused as to who thought this current state would have any decency in UX, vs. the dbu enforcing the manufacturing grid to make it literally impossible to trip the OFFGRID DRC (at least on PDKs that don't have layer-dependent manufacturing grids; I think sky130 might have a coarser grid for m3/m4/m5 than for li/poly/comp).
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message-1527060987365036172

2026-07-15T21:15:10.809+00:00 — were491 (@were491.)

Content

i feel like the issue is forgetting to scale at some place lol
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message-1527061187022295080

2026-07-15T21:15:58.411+00:00 — were491 (@were491.)

Content

also, usually you should set a grid size in klayout anyways right? in this case it's just a pcell bug that could be fixed
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message-1527061281260175421

2026-07-15T21:16:20.879+00:00 — were491 (@were491.)

Content

~~maybe i'm larping too hard though~~
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message-1527097324440911932

2026-07-15T23:39:34.243+00:00 — namibj

Reply/reference

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If only that was something hard-enforced, and not a mouse cursor tool courtesy...
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message-1527414643801198682

2026-07-16T20:40:29.074+00:00 — Olle (@osvel)

Reply/reference

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I am sure the PDK  has more of these issues. A random idea would be to add regression tests to the pcell library (afaik klayout pcells are written in python) and ensure that the vertices all land on grid
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message-1527414770427367568

2026-07-16T20:40:59.264+00:00 — Olle (@osvel)

Content

Could even fuzz the parameters to find edge cases
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message-1527415038158049630

2026-07-16T20:42:03.096+00:00 — Olle (@osvel)

Content

(maybe just do this with AI and file some reports)
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message-1533185310131749044

2026-08-01T18:51:03.141+00:00 — Tholin (@tholin)

Content

Need to make a analog comparator for my next analog layout. Can’t I just re-use my normal opamp schematic for this? As far as I understand, the two are very similar.
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message-1533185406366122114

2026-08-01T18:51:26.085+00:00 — Tholin (@tholin)

Content

Opamp but the output stage is replaced with a schmitt trigger inverter/buffer = comparator
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message-1533185412363976774

2026-08-01T18:51:27.515+00:00 — Tholin (@tholin)

Content

?
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message-1533185516403687465

2026-08-01T18:51:52.32+00:00 — Tholin (@tholin)

Content

Well, maybe not a schmitt trigger depending on the application.
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message-1533185713842028707

2026-08-01T18:52:39.393+00:00 — Tholin (@tholin)

Content

Wait, is there even a difference between the two?
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message-1533186706977849434

2026-08-01T18:56:36.175+00:00 — tnt (@246tnt)

Content

It's the same basic concepts but you optimize for different things.
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message-1533186824955101255

2026-08-01T18:57:04.303+00:00 — tnt (@246tnt)

Content

What are the requirements for your comparator ?
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message-1533187303097241740

2026-08-01T18:58:58.301+00:00 — Tholin (@tholin)

Content

I’m worried about the output not being something I can safely feed into a standard cell because it might settle on a voltage between high and low.
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message-1533187471288832063

2026-08-01T18:59:38.401+00:00 — Tholin (@tholin)

Content

That’s my current concern
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message-1533187637232275476

2026-08-01T19:00:17.965+00:00 — Tholin (@tholin)

Content

I can optimize it for the input voltage ranges I’m using later, when I have some more concrete numbers.
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message-1533187815016366153

2026-08-01T19:01:00.352+00:00 — Tholin (@tholin)

Content

opamps have analog outputs, so can generate non-logic-level voltages
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message-1533187962534101173

2026-08-01T19:01:35.523+00:00 — tnt (@246tnt)

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The general idea is you need enough gain so that any voltage difference at the input will result in the output hitting the rails ...
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message-1533188099574857819

2026-08-01T19:02:08.196+00:00 — tnt (@246tnt)

Content

and then ideally some hysteresis so that noise doesn't create a mess if you have slow transitions.
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message-1533188240583164056

2026-08-01T19:02:41.815+00:00 — tnt (@246tnt)

Content

And as you said above, a schmitt trigger is not a bad way to provide both more gain as a second stage and hysteresis.
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message-1533188297323581641

2026-08-01T19:02:55.343+00:00 — tnt (@246tnt)

Content

This is what I did in the comparator for my 555 clone.
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message-1533188731325120522

2026-08-01T19:04:38.817+00:00 — tnt (@246tnt)

Content

But that's highly dependent on the application ... the "comparator" I did on sky 130 ( for high speed differential input ) works differently and just uses positive feedback and 3 stages to have enough gain to force input to a rail.
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message-1533188863131127930

2026-08-01T19:05:10.242+00:00 — Tholin (@tholin)

Content

Alright
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message-1533188902054002928

2026-08-01T19:05:19.522+00:00 — Tholin (@tholin)

Content

I think i’ll look into how to build a schmitt trigger for this
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message-1533189058694746294

2026-08-01T19:05:56.868+00:00 — tnt (@246tnt)

Content

And then the comparator I'm working on now for clocked sampling works yet another way because if you sample at regular interval you can have sample step and amplify step.
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message-1533189253410980004

2026-08-01T19:06:43.292+00:00 — tnt (@246tnt)

Content

What's the application ?
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message-1533189777493458954

2026-08-01T19:08:48.243+00:00 — tnt (@246tnt)

Content

I have a gf180 schmitt inverter there :
https://github.com/smunaut/tt_tnt_gf_555/blob/main/xschem/inv_schmitt.sch
https://github.com/smunaut/tt_tnt_gf_555/blob/main/mag/inv_schmitt.mag
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message-1533189808774582363

2026-08-01T19:08:55.701+00:00 — Tholin (@tholin)

Content

Overvoltage protection
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message-1533189866098262258

2026-08-01T19:09:09.368+00:00 — Tholin (@tholin)

Content

Sortof, but that’s the basic idea
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message-1533518419369136168

2026-08-02T16:54:42.572+00:00 — namibj

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AFAIK the solution to that is to have so many inverters in sequence that noise will make it statistically improbable to end up with metastable voltages at the end.
Clocked comparators afaik help a lot for that, btw.
You get a deliberate regenerative gain stage, suitable for feeding to a couple stages of DFFs just like you'd have to do for digital signals that cross clock domains btw.
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message-1533521510738690048

2026-08-02T17:06:59.612+00:00 — namibj

Reply/reference

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Ohhh, tell what for (if you can); I'm looking mildly anxiously forward to having to do similar but probably substantially more complicated due to needing it to run at probably 16x interleaving 🙁
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message-1533521796509466635

2026-08-02T17:08:07.745+00:00 — tnt (@246tnt)

Content

I'm slowly working toward my USB 2.0 HS PHY goal 😅

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message-1533538638351171686

2026-08-02T18:15:03.153+00:00 — djsftree

Content

cap_mim_*_m4m5_noshield , just checking wafer space support the mim, HRES poly resistor (one additional mask?)  and Vt NMOS from s10 of pdk.
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message-1533542028875530271

2026-08-02T18:28:31.517+00:00 — tnt (@246tnt)

Content

It supports :
* 2 fF/um^2 MiM
* 1k / sq HRES poly
* Native 6.0v nmos
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message-1533546472606535770

2026-08-02T18:46:10.985+00:00 — namibj

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🙂

Do share what you get from that.
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message-1533547334934331503

2026-08-02T18:49:36.58+00:00 — namibj

Content

[I'll also ask in the substantially non-overlapping chipalooza matrix, as it's more near-term relevant to there; I'll only expect to have such structure for e-test on Run3, but still..]

Regarding the C_Offset capacitance digital trim banks:
Is that what the sky130 PDK calls "accumulation-mode varactors"? <https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#v-accumulation-mode-mos-varactors>

Do we have an appropriate device on gf180mcuD and/or IHP SG13cmos5L?

[edit:]... we do seem to have an `SVaricap` on IHP SG13cmos5L; not so sure yet about the situation on gf180mcuD. Which isn't helped by my somewhat poor understanding of the supposed behavior of these structures that can't be replicated (properly) by "just" using "normal" PMOS devices in their own dedicated nwell, with their guard ring and that.

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message-1533550982523392042

2026-08-02T19:04:06.233+00:00 — Tholin (@tholin)

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Ah, but I'd need a clock source for DFFs
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message-1533557177221124357

2026-08-02T19:28:43.164+00:00 — namibj

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What are you trying to lift the signal into then? Or is the purpose of the S that shall consume the comparator feed secret for the time being?
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message-1533571478648393848

2026-08-02T20:25:32.89+00:00 — djsftree

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thanks!
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message-1533573205699199147

2026-08-02T20:32:24.651+00:00 — tnt (@246tnt)

Content

@namibj There are varactor on gf180. All named "moscap".
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message-1533573398591045734

2026-08-02T20:33:10.64+00:00 — namibj

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oh.

Are they built like the sky130 ones?
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message-1533573552479932498

2026-08-02T20:33:47.33+00:00 — tnt (@246tnt)

Content

Not sure never looked. magic has a pcell.
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message-1533573821343203438

2026-08-02T20:34:51.432+00:00 — tnt (@246tnt)

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What I'm designing ATM looks basically similar to that drawing, except the input stage is pmos because common mode is very low, so nmos don't work there.
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message-1533574030949351524

2026-08-02T20:35:41.406+00:00 — namibj

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yeah that aspect in this one is handled by the CTLE preamp section drawn upper left
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message-1533574146825654314

2026-08-02T20:36:09.033+00:00 — namibj

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https://people.engr.tamu.edu/spalermo/ecen689/lecture10_ee689_rx_circuits.pdf
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message-1533574860637208668

2026-08-02T20:38:59.219+00:00 — namibj

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Time-interleaved or not for the USB-HS target?
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message-1533575152032551104

2026-08-02T20:40:08.693+00:00 — namibj

Content

If you happen to have some reading material you can link on the clock recovery part of the subject matter, please do.
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message-1533575396795351222

2026-08-02T20:41:07.049+00:00 — tnt (@246tnt)

Content

Yes, my VCO is running at 240 MHz with 4 phase 0 90 180 270.

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message-1533575465086750721

2026-08-02T20:41:23.331+00:00 — tnt (@246tnt)

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Ok, gotta go sorry ...

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message-1533576154647232582

2026-08-02T20:44:07.735+00:00 — namibj

Content

I otherwise feel like I'd put like 4 extra ones next to the time-interleaved full data rate army either in a box or a cross pattern (not sure yet) and adjust to where those offset ones reach a notably-but-limited BER, comparing the information in the digital domain (slow side).
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message-1534302254075482184

2026-08-04T20:49:23.329+00:00 — Brunny (@brunny95)

Content

Hi, I am checking a little bit this page: https://mithro.github.io/gf180mcu-project-template/
I have a question about the analog pins: would it be possible to have more using the standard pads? I see that we can have only 6 of them with the 0.5×1 (Half Width)
Because we would like to have the chip on board packaging too
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message-1534307980059869225

2026-08-04T21:12:08.51+00:00 — Tholin (@tholin)

Content

My next submission is going to be a entire analog die. So I’m not going to need the LibreLane flow at all. I am going to do the routing to the pads myself, since I need the wires to be quite thick.
Not sure how to accomplish this. I’ll keep everyone updated on my progress.

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message-1534312011234807838

2026-08-04T21:28:09.617+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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I'm not 100% about the power pads, but analog/bidir/input can be changed in the template to whatever you want. You just can't change the pad position/size/number if you want to use the COB packaging.

Pretty sure you can change the power pads too, I don't think the COB pcb ties them together. but not 100% on that part

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message-1534315483904475158

2026-08-04T21:41:57.566+00:00 — Brunny (@brunny95)

Content

Honestly, if that was the case, it would not make sense to write down the number of bidir/analog/input pads and power pads inside the project template. But I would be very happy if this is the case 😍
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message-1534316983565291641

2026-08-04T21:47:55.113+00:00 — Brunny (@brunny95)

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My idea would be to use the flow of librelane for the generation of the pads; if the pads are "free" a possible ideas would be to parallelize these standards pads, like using 2 or more pads for the same signal, and avoid to manually layout them.
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message-1534564700904226986

2026-08-05T14:12:15.529+00:00 — tnt (@246tnt)

Content

Did anyone look at the IOs drivers ?  Are the final driver transistors nmos/pmos used as ESD diodes ?   I don't see any separate ESD structures.
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message-1534567408621322377

2026-08-05T14:23:01.099+00:00 — tnt (@246tnt)

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Started a thread.
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message-1534588263732609205

2026-08-05T15:45:53.345+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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I can say from experience (Run1) and because I also did it for Run2: you can definitely change bidir/analog/input to whatever you want 🙂 I think that page you found on Tim's github is just the result of a script that dumps out the default configs for comparison. I wouldn't read too much into it
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message-1534603565421695208

2026-08-05T16:46:41.552+00:00 — Essen (@essen__)

Reply/reference

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Same understanding here, and as @BreakingTaps says you are free to do whatever you want and switch out they types between {analog/bidir/input} just keep the power pins in place for CoB packing.
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message-1534604255216799924

2026-08-05T16:49:26.012+00:00 — Brunny (@brunny95)

Content

Great news guys, thanks a lot to both!
For the power pins, I have to check their current specifications, I hope they are fine

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message-1535354391572389898

2026-08-07T18:30:12.456+00:00 — namibj

Reply/reference

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they're in the PDK on the page for that padring-member-class cell.

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message-1536089526433353920

2026-08-09T19:11:22.265+00:00 — Tholin (@tholin)

Content

https://cdn.discordapp.com/attachments/1148704591781843145/1536088828261961900/image.png?ex=6a7a21b3&is=6a78d033&hm=1b3649929bbef12f43b949979d36500a43156094f8b878ef615b10d7107f1a07&

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message-1536089550131175485

2026-08-09T19:11:27.915+00:00 — Tholin (@tholin)

Content

Working comparator
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message-1536120281662496849

2026-08-09T21:13:34.883+00:00 — Tholin (@tholin)

Content

O- oh!

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message-1536122198459293736

2026-08-09T21:21:11.883+00:00 — tnt (@246tnt)

Content

Working oscillator?
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message-1536128629828882473

2026-08-09T21:46:45.241+00:00 — Tholin (@tholin)

Content

Technically, yes
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message-1536128700985384960

2026-08-09T21:47:02.206+00:00 — Tholin (@tholin)

Content

Now, "is it supposed to be an oscillator" is a different and no less interesting question entirely!
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message-1536158241585762325

2026-08-09T23:44:25.234+00:00 — namibj

Content

I have a feeling the strong ARM latch with it's nominal/supposed output into an RS latch from which the stabilized output can then be recovered afterwards, would also work suitably for this task here, though ofc replacing the _strongly regenerative, made possible through clocked gain_ core of a strong ARM latch with a sufficciently weakly regenerative one that _just_ manages to provide the desired width of dead-band/hysteresis, and is then followed with a sufficcient quantity of differential gain stages to ensure it still correctly/properly operates the RS latch.

One would probably need to rely on CMOS inverter [-pair] (weakened by channel elongation to reduce bandwidth to what the following parts can actually utilize, and to curb power waste in that place, unless a current-starved-inverter style turns out to not break the regenerative core's operating principles) inputs in place of the strong ARM latch's natural nmos-diff-pair, but I doubt you need it to resolve double-hysteresis-flip signals (i.e., twice as much input amplitude as would be required to merely meet the input hysteresis, and where one would thus have a fairly weak but reasonably-above-noise-floor input signal) in under 2 ns (let's say 3ns given the use of 5V devices).
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message-1536301232044507177

2026-08-10T09:12:36.816+00:00 — Tholin (@tholin)

Content

Are there any DRC rules dictating a maximum width for a single transistor?
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message-1536301291935109204

2026-08-10T09:12:51.095+00:00 — Tholin (@tholin)

Content

Can I have one wide FET that stretches the entire width of the core area?
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message-1536302470576472064

2026-08-10T09:17:32.105+00:00 — Tholin (@tholin)

Reply/reference

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I am also still trying to figure out how to go about making an entirely analog die. Any suggestions, @Leo Moser (mole99) ? I want to do the whole core area by hand, only calling upon LibreLane for filler insertion and DRC checks.
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message-1536303631765078048

2026-08-10T09:22:08.954+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Well, for the first part you can either use magic or KLayout to draw the layout (I suppose that wasn't the question 😉), and for the second part you could use a custom LibreLane flow, either through the API or by modifying the flow through the config.

The [gf180mcu-precheck](https://github.com/wafer-space/gf180mcu-precheck) is basically just that: it first reads in a GDS into LibreLane's current state using a custom step, and then runs e.g. Magic.DRC and KLayout.DRC on it. In your case, you can also add filler generation.

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message-1536305938326229092

2026-08-10T09:31:18.881+00:00 — Tholin (@tholin)

Reply/reference

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The problem is that I’d rather not have to figure out how to draw the padring and sealring by hand. I need a template. A gf180-analog-template, if you will :P
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message-1536306043838275635

2026-08-10T09:31:44.037+00:00 — Tholin (@tholin)

Content

I guess a LibreLane flow that aborts after just those steps?
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message-1536307136286433330

2026-08-10T09:36:04.497+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Now I understand! Yes that one already exists, you can find more information on running the flow in the project template README: https://github.com/wafer-space/gf180mcu-project-template#building-a-standalone-padring-for-analog-design

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message-1536307660654252143

2026-08-10T09:38:09.516+00:00 — Tholin (@tholin)

Content

Idk how you manage to always be one step ahead
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message-1536307677624401931

2026-08-10T09:38:13.562+00:00 — Tholin (@tholin)

Content

Thank you
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message-1536310962561351801

2026-08-10T09:51:16.752+00:00 — Leo Moser (mole99) (@mole99)

Content

Haha, well, it's a common problem with analog designs.
You're welcome!
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message-1536315073100914769

2026-08-10T10:07:36.781+00:00 — Tholin (@tholin)

Content

I think I’m going to go for a quarter slot this time and hope it gets squeezed into some spare space like some projects did on run 2.

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message-1536316043989884928

2026-08-10T10:11:28.259+00:00 — Leo Moser (mole99) (@mole99)

Content

If you have the time to create additional variations of your design, such as half-slot versions, chances are even higher.
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message-1536316184914436209

2026-08-10T10:12:01.858+00:00 — Tholin (@tholin)

Content

That would be a lot of work since I am doing the whole layout by hand, but I can try

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message-1536316400455520276

2026-08-10T10:12:53.247+00:00 — Tholin (@tholin)

Content

I probably can adapt it quite easily for half-slot, but I’d feel bad taking up a full slot since this is a pretty simple circuit that is already going to have a lot of unused space on the quarter slot.
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message-1536316405010665582

2026-08-10T10:12:54.333+00:00 — Tholin (@tholin)

Content

I think
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message-1536316542344765502

2026-08-10T10:13:27.076+00:00 — Tholin (@tholin)

Content

Most of the die area is going to be a big power FET, but I don’t expect it to be too large.
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message-1536316590973386782

2026-08-10T10:13:38.67+00:00 — Tholin (@tholin)

Content

In typical fashion, I will fill the remaining area with art
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message-1536316678772756491

2026-08-10T10:13:59.603+00:00 — Tholin (@tholin)

Content

Which should be easier this time since I don’t have to worry about keeping LibreLane out of trouble around the artworks.
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message-1536317672323547177

2026-08-10T10:17:56.484+00:00 — v (@vaticori)

Reply/reference

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Are you also trying to submit this for Chipalooza?
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message-1536317791009775666

2026-08-10T10:18:24.781+00:00 — Tholin (@tholin)

Content

I don’t know what Chipalooza is
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message-1536318629262401566

2026-08-10T10:21:44.636+00:00 — Leo Moser (mole99) (@mole99)

Content

@Tim Edwards is hosting Chipalooza, see here for more: https://opencircuitdesign.com/chipalooza/
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message-1536319823959556166

2026-08-10T10:26:29.474+00:00 — Tholin (@tholin)

Content

Huh, interesting
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message-1536319845891575880

2026-08-10T10:26:34.703+00:00 — Tholin (@tholin)

Content

But does look a lot more is involved there
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message-1536319924153356338

2026-08-10T10:26:53.362+00:00 — Tholin (@tholin)

Content

Like, I see a bunch of review steps
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message-1536353858425585727

2026-08-10T12:41:43.923+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

You can handle it!  Anyway, Chipalooza for GF will launch in a week and I will announce on the Wafer.Space discord.

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message-1536354810302038116

2026-08-10T12:45:30.868+00:00 — Tholin (@tholin)

Content

I’m reading the FAQ right now. So, I need to make a layout that is integrated onto a multi-project die?
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message-1536355016703742023

2026-08-10T12:46:20.078+00:00 — Tholin (@tholin)

Content

Hmmm, not sure what I’m building now is suitable, then, but I can maybe take some of its component modules and do something with those.
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message-1536374922643902545

2026-08-10T14:05:26.024+00:00 — namibj

Reply/reference

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KLayout has them as PCells.
Well, the sealring; you could also take a template GDS and flatten and delete everything but the top metal/pad-opening structures from inside the sealring, leaving only the literal pads themselves (I'd suggest considering to keep the existing via structure of how the pad electrical connection is escaped downwards, as there are some minor DRC aspects around the interaction between (especially upper-level) vias and pads if those pads are wedge-bonded (like all of Run1 has been)
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message-1536375611214274742

2026-08-10T14:08:10.192+00:00 — namibj

Reply/reference

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For the record, `FC01` was done entirely in KLayout using the IEEE Chipathon docker tag.
Took me a few tries to get the coordinate origin and exact precise size of the pad ring right, but that was it.
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