Public

Digital Design

Digital flow from RTL through checked GDS, with dated wafer.space evidence.

Scope

This page is the entry point for the digital flow. It covers the path from RTL to a checked GDS. Detailed RTL, timing, tool-version, signoff, and fault work belongs on the linked pages.

Current summary

  • Confirmed fact — 2026-06-03: Project Template 1.5.0 used open_pdks through Ciel. It added variables for standard-cell, pad, and SRAM libraries, plus a parallel DRC runner and Precheck 1.6.0 with CoB selection. Evidence (Discord)
  • Confirmed fact — 2026-07-14: Project Template 1.5.8 fixed a critical buffer-cell error in gf180mcu_as_sc_mcu7t3v3. Designs using that library were told to rebuild. Evidence (Discord)

Flow map

  1. Start with an RTL design and a repeatable simulation. The project-template example had cocotb RTL and gate-level tests by 2025-10-02. Evidence (Discord)
  2. Run synthesis and read the first Yosys error or warning, not only the later checker failure. The detailed check appears in yosys-synthesis.log near Executing CHECK pass and may also appear in reports/pre_synth_chk.rpt. Evidence (Discord)
  3. Run placement, clock-tree synthesis, routing, and static timing analysis in LibreLane/OpenROAD. For a post-route hold failure, begin at 54-openroad-stapostpnr/summary.rpt and the failing corner's min.rpt. Evidence (Discord)
  4. Produce the final GDS and run the release precheck. In the 2025-11-03 guidance, precheck covered Magic and KLayout DRC, off-grid and angle rules, density, layout checks, and project-ID handling. Evidence (Discord)

Dated decisions and limits

  • Confirmed fact — 2026-03-26: Project Template 1.4.0 moved to LibreLane 3.0. Evidence (Discord)
  • Confirmed fact — 2026-06-18: Template 1.5.3 corrected a 0.5 um north/south bond-pad offset. Precheck 1.7.0 added a golden pad-mask comparison for CoB. Evidence (Discord)
  • Decision — 2026-03-27: A DRC pass was stated to be mandatory for tapeout, with no waiver system. Evidence (Discord)
  • Open question: The archive does not define one maximum supported clock rate. Timing depends on the design, library, constraints, corner, and ECO work. One 9-track-library suggestion did not by itself close the reported timing problem. Evidence (Discord)

Sources

  • 1423349035892478074 — 2025-10-02T16:40:54.703+00:00 — Leo Moser (mole99) (@mole99) — template example, filler and seal ring, DRC/LVS result, and cocotb RTL/GL tests. Evidence (Discord)
  • 1440439686526144552 — 2025-11-18T20:33:03.343+00:00 — aedancullen — Yosys log and report locations. Evidence (Discord)
  • 1445872535160885409 — 2025-12-03T20:21:15.395+00:00 — Lofty (@ravenslofty) — post-route timing reports and ECO path. Evidence (Discord)
  • 1434849326584037460 — 2025-11-03T10:18:57.669+00:00 — Leo Moser (mole99) (@mole99) — intended precheck coverage. Evidence (Discord)
  • 1486728700518203616 — 2026-03-26T14:09:04.287+00:00 — Leo Moser (mole99) (@mole99) — LibreLane 3.0 transition. Evidence (Discord)
  • 1511722026648338514 — 2026-06-03T13:23:37.59+00:00 — Leo Moser (mole99) (@mole99) — Template 1.5.0 and Precheck 1.6.0. Evidence (Discord)
  • 1517130928248586290 — 2026-06-18T11:36:40.224+00:00 — Leo Moser (mole99) (@mole99) — CoB offset and golden-mask fixes. Evidence (Discord)
  • 1526579676183662662 — 2026-07-14T13:22:37.281+00:00 — Leo Moser (mole99) (@mole99) — critical 3.3 V SCL buffer fix. Evidence (Discord)
  • 1486979241148158012 — 2026-03-27T06:44:37.828+00:00 — Tim 'mithro' Ansell (@mithro_) — DRC required and no waiver. Evidence (Discord)
  • 1445875652225011933 — 2025-12-03T20:33:38.561+00:00 — Lofty (@ravenslofty) — case-specific 9-track suggestion. Evidence (Discord)