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Thread: Is there a DRC violation waiver system?

34 Discord messages from ℹ️ - Information/⁉️-questions/threads/is-there-a-drc-violation-waiver-system.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1486057912555012167

Messages: 34

message-1486057912555012167

2026-03-24T17:43:35.974+00:00 — nmz787

Content

Is passing DRC strictly required to tapeout? Is there any waiver system? For example I want to make topmetal "pads" smaller than design rule pad sizes, as I want to post-process dies/wafers to add additional layers to the design.
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message-1486068233760145551

2026-03-24T18:24:36.741+00:00 — nmz787

Content

@Matt Venn  your comments were helpful 🙂
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message-1486068361367388261

2026-03-24T18:25:07.165+00:00 — nmz787

Content

Though I assume your "yes" was in regards to "strictly must pass DRC"
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message-1486070350071726302

2026-03-24T18:33:01.309+00:00 — Matt Venn (@mattvenn)

Content

I thought I was in the tt discord
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message-1486070459870085201

2026-03-24T18:33:27.487+00:00 — Matt Venn (@mattvenn)

Content

Where the answer is no, but I don't know for wafer.space
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message-1486085485435818226

2026-03-24T19:33:09.861+00:00 — tnt (@246tnt)

Content

For last run, they wouldn't even waive the antenna rule 😅
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message-1486106831280668733

2026-03-24T20:57:59.107+00:00 — nmz787

Content

that makes sense though, because of charging during plasma steps
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message-1486107121480106045

2026-03-24T20:59:08.296+00:00 — nmz787

Content

a discharge event will cause spallation and can cover not only your wafer with particles, but the entire chamber... leading to later batches to get particle contam

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message-1486713628412481717

2026-03-26T13:09:10.817+00:00 — Leo Moser (mole99) (@mole99)

Content

Tim wants wsrun-2 to follow the DRC rules much more strictly, as per the PDK docs.

The only rule I can find for the pad layer is for the top metal overlap: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_1.html
All the other rules are guidelines: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_2.html
However, as there is no mention of a minimum pad width anywhere, wafer.space has to assume a minimum width of 40x40 according to PAD.1.
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message-1486979241148158012

2026-03-27T06:44:37.828+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Passing DRC is strictly required for tapeout, there is no waiver system and there won't be any support for waivers.
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message-1486980111726018680

2026-03-27T06:48:05.39+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) - What about the rules @ https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_3.html and https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_5.html ?
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message-1486980170215850035

2026-03-27T06:48:19.335+00:00 — nmz787

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Content

Oh  i thought 4 microns was allowed (some rule or guideline about "gold")
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message-1486980276021100554

2026-03-27T06:48:44.561+00:00 — nmz787

Content

But that still is larger than ideal for "a via" to an additional layer
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message-1486980345785225368

2026-03-27T06:49:01.194+00:00 — nmz787

Content

Ideally we'd know exactly the fab minimum CD limit
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message-1486982050664677547

2026-03-27T06:55:47.669+00:00 — nmz787

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Content

It looks like there's 4 different bonding processes...
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message-1486982170747736236

2026-03-27T06:56:16.299+00:00 — nmz787

Content

Which one is offered for "bare wafer" purchase option  needs clarification though
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message-1487680502692319412

2026-03-29T05:11:11.609+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

None of these bonding processes are really on offer, we are using an external wire bonding house.
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message-1487730443016081449

2026-03-29T08:29:38.31+00:00 — Leo Moser (mole99) (@mole99)

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Content

Unfortunately, they don't apply to our use case and specify different numbers. While the solder bump (solder ball) rules specify a min. passivation opening of 40um, the probe guidelines specify min. probe passivation opening of 50um.

There's an interesting note in the bond pad guidelines:

> These are just default numbers for DRC purpose only, however, these are VARIABLE and the customer is advised to use the appropriate value acceptable to their assembly house.

So I suppose there's no min. limit for the passivation opening specified, because they assume that you are going to use sane numbers anyway, in order to do the bonding process.
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message-1487731209059565679

2026-03-29T08:32:40.949+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Do you see a maximum size for the passivation opening?
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message-1487736715090198609

2026-03-29T08:54:33.689+00:00 — Leo Moser (mole99) (@mole99)

Content

No, I haven't seen one.
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message-1487848899132526753

2026-03-29T16:20:20.449+00:00 — nmz787

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Content

Minimum is likely more important for the litho operating point for that layer
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message-1487949821544497212

2026-03-29T23:01:22.227+00:00 — Tim 'mithro' Ansell (@mithro_)

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Well, if there is no maximum, then you could just have a completely open top of the chip with no passivation.
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message-1487951655407194266

2026-03-29T23:08:39.454+00:00 — nmz787

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Content

Wouldn't "Min Probe pad top layer metal overlap of pad opening" flag?
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message-1487952149454520491

2026-03-29T23:10:37.244+00:00 — Tim 'mithro' Ansell (@mithro_)

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Dunno, that is why I was asking.
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message-1488092010068840468

2026-03-30T08:26:22.613+00:00 — Leo Moser (mole99) (@mole99)

Content

Even if there's no rule against it, I'm not sure if that doesn't lead to planarity issues at any of the processing steps.
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message-1488699583902253056

2026-04-01T00:40:39.503+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) - I'm not sure they do any planarization of the last layers?
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message-1488803137685815468

2026-04-01T07:32:08.649+00:00 — Leo Moser (mole99) (@mole99)

Content

Neither am I, but I'm also not sure that a chip-sized hole in the passivation layer won't cause problems.
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message-1488805927468400735

2026-04-01T07:43:13.785+00:00 — tnt (@246tnt)

Content

That's what nmz said above, PM.4 ?  You need a 2um overlap of TopMetal for any passivation opening.
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message-1488827323976388658

2026-04-01T09:08:15.11+00:00 — Leo Moser (mole99) (@mole99)

Content

Right. Technically, you could cover the entire chip with TopMetal (no upper density limit?) and open up almost the entire inside area. However, this would be pretty useless since you would then have TopMetal everywhere. Even then, I don't think it would be accepted for manufacture. The rules seem targeted at "normal" bonding applications.

So I guess it's fair to say the min. pad opening is 40x40um, and there's no way around this by opening up the whole chip.
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message-1488854877726572685

2026-04-01T10:57:44.436+00:00 — nmz787

Content

Assuming this is "bond pad" rules, then I think each pad would also need to meet "PAD.5 MetalTop (2) overlap of Top_Via (3)" which just says 0.5... not > or <= etc... so I feel they must mean 'exactly 0.5'.
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message-1488854951705972838

2026-04-01T10:58:02.074+00:00 — nmz787

Content

Which then cascades to via size rules
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message-1488855042139226192

2026-04-01T10:58:23.635+00:00 — nmz787

Content

And presumably they aren't letting topvia be some wild numbers???
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message-1488855179620126852

2026-04-01T10:58:56.413+00:00 — nmz787

Content

(i am used to a big CSV file with all the Design Rules, so these multiple webpages and clicking around isn't easy for me)
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message-1488856045978910810

2026-04-01T11:02:22.969+00:00 — nmz787

Content

I guess these are the via size rules? https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_15.html
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