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Thread: Failing Hold Checks

22 Discord messages from ℹ️ - Information/⁉️-questions/threads/failing-hold-checks.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1445866342438932643

Messages: 22

message-1445866342438932643

2025-12-03T19:56:38.935+00:00 — Trevor Peyton (@trev5514)

Content

Has anyone been able to pass timing for hold checks on an 11MHz+ design? I have done everything I could think of, yet the corners still end up failing. The path is always pad -> reg nothing else.

I've tried these settings:

PL_RESIZER_HOLD_SLACK_MARGIN from 0.1, 0.3, 0.5 even 0.7 and none seem to make a difference (I do get less hold errors but all still fail)
I've tried PL_RESIZER_ALLOW_SETUP_VIOS

and

set_input_delay -min 0, .5, 1, 1.5

Any ideas?
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message-1445869250244902994

2025-12-03T20:08:12.21+00:00 — Leo Moser (mole99) (@mole99)

Content

Perhaps an unbalanced clock tree? You can view the clock tree in OpenROAD GUI.
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message-1445870302926999744

2025-12-03T20:12:23.189+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

sure; I've passed hold checks on a 60MHz design :p
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message-1445870444174376973

2025-12-03T20:12:56.865+00:00 — Lofty (@ravenslofty)

Content

I do often need to ECO some hold buffers in though
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message-1445871889712021636

2025-12-03T20:18:41.508+00:00 — Trevor Peyton (@trev5514)

Content

With the exception of the right spot which I'll look into it looks very balanced.

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message-1445872139713511555

2025-12-03T20:19:41.113+00:00 — Trevor Peyton (@trev5514)

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Content

Do you manually place them in? Did you change your input/output delays or do you use the templates default 0 for min?
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message-1445872535160885409

2025-12-03T20:21:15.395+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

read `54-openroad-stapostpnr/summary.rpt` to find the failing corners, then look at `54-openroad-stapostpnr/<corner>/min.rpt` to find the failing paths, and then [follow the docs](https://librelane.readthedocs.io/en/latest/usage/using_ecos.html)
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message-1445872687925690498

2025-12-03T20:21:51.817+00:00 — Lofty (@ravenslofty)

Content

it's manual in that you have to point the tooling at the cell you want to insert a hold buffer for, but there's no physical placement or such

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message-1445873529651204217

2025-12-03T20:25:12.5+00:00 — Trevor Peyton (@trev5514)

Content

Thank you, I have been looking at those corners but I didn't know about the ECO step!
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message-1445873775194279936

2025-12-03T20:26:11.042+00:00 — Lofty (@ravenslofty)

Content

(the downside of having a 60MHz design is that I have basically given up on meeting slow corner setup without major cheating)
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message-1445874188090081450

2025-12-03T20:27:49.484+00:00 — Trevor Peyton (@trev5514)

Content

My original target was 90MHz and now I'm just trying to get any passing. I'm currently failing 10MHz...
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message-1445874418621485189

2025-12-03T20:28:44.447+00:00 — Lofty (@ravenslofty)

Content

are you using the 9-track libraries?
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message-1445875058063970425

2025-12-03T20:31:16.902+00:00 — Trevor Peyton (@trev5514)

Content

Whatever the default one is.
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message-1445875652225011933

2025-12-03T20:33:38.561+00:00 — Lofty (@ravenslofty)

Content

7-track. Try adding `STD_CELL_LIBRARY: gf180mcu_fd_sc_mcu9t5v0` to your `librelane/config.yaml`

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message-1445876161984069644

2025-12-03T20:35:40.097+00:00 — Trevor Peyton (@trev5514)

Content

I'll give it a go after I try ECO. Surely 10MHz is possible with the 7-track? At this point - what do I know haha!
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message-1445881315307159684

2025-12-03T20:56:08.745+00:00 — Trevor Peyton (@trev5514)

Content

@Lofty Did you ever run into unconnected ECO pins after the eco step?
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message-1445884346933186621

2025-12-03T21:08:11.541+00:00 — Trevor Peyton (@trev5514)

Content

Looks like the disconnected pins are pwr/gnd: eco_buffer_0/VDD, eco_buffer_0/VNW, eco_buffer_0/VPW, and eco_buffer_0/VSS
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message-1445885538736541748

2025-12-03T21:12:55.689+00:00 — Greg (@greg.hashtag.9468)

Content

What does your I/O connect to? If it's not actually driven synchronously alongside your clock input. You may be able to further relax the timing.
With a `input_delay -min 0` you're telling the tools, the external i/o arrives with the clock. So it tries to add 4ns of delay to ensure a leaf in your clock tree.
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message-1445885936578728008

2025-12-03T21:14:30.542+00:00 — Trevor Peyton (@trev5514)

Content

Everything is synchronous with the clock input.
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message-1445907135476011179

2025-12-03T22:38:44.753+00:00 — BreakingTaps (@polyfractal)

Content

(oof, did not know about ECO or 9T stuff either. probably would have saved a lot of agony fussing with settings 😅 )
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message-1445907388228960383

2025-12-03T22:39:45.014+00:00 — Trevor Peyton (@trev5514)

Content

Maybe, ECO isn't working for me still and neither is the 9T
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message-1445910109375959070

2025-12-03T22:50:33.786+00:00 — Trevor Peyton (@trev5514)

Content

For anyone that runs into the ECO issue:

"+OpenROAD.DetailedRouting": "Odb.InsertECOBuffers"
 "+Odb.InsertECOBuffers": "OpenROAD.DetailedRouting"

I haven't confirmed yet, but I added the Odb.InsertECOBuffers step but I didn't add the routing after which likely left the ECO buffers unconnected.
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