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#📝-project-template

1,521 Discord messages from 📐 - Designing/project-template/channel.md.

Category: 📐 - Designing Channel ID: 1423348662318272592

Messages: 1,521

message-1423349035892478074

2025-10-02T16:40:54.703+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Major update to the [gf180mcu-project-template](https://github.com/wafer-space/gf180mcu-project-template)!

The example design now runs through the complete flow, including:

- Sealring insertion
- Filler generation

... and is DRC and LVS clean, according to the open source PDK.

There is now also a [cocotb](https://www.cocotb.org/) testbench available in the repository. We use the newly released cocotb 2.0.0.
You can run RTL as well as GL simulations, after implementing the design.

To ensure your design will be accepted for tapeout, you will be able to run the [gf180mcu-precheck](https://github.com/wafer-space/gf180mcu-precheck).
At the moment it is still a work in progress.

Further updates will follow, but you can use the current state as a stable basis for implementing your design.
If you encounter any issues, please report them so that we can improve both the template and the PDK.

PS: Special thanks to @Tim Edwards for his help in solving the uncovered PDK and tool-related issues.

Leo

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message-1423350222997815368

2025-10-02T16:45:37.731+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Tim Edwards has only barely begun to address all the issues that have surfaced over the past few weeks. . .
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message-1423350882266910891

2025-10-02T16:48:14.913+00:00 — Tholin (@tholin)

Content

Its that bad?
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message-1423351030476705955

2025-10-02T16:48:50.249+00:00 — Leo Moser (mole99) (@mole99)

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Content

Haha, I also have to upstream a number of LibreLane related patches 😄
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message-1423351582279467058

2025-10-02T16:51:01.809+00:00 — Leo Moser (mole99) (@mole99)

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Also I forgot to mention that it is now possible to adjust the padring directly from the LibreLane configuration file.
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message-1423356248396529729

2025-10-02T17:09:34.298+00:00 — htamas (@h.tamas)

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Started a thread.
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message-1423370092233756862

2025-10-02T18:04:34.926+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tholin :  Well, it means there's a lot to do if we want people to have successful tapeouts.
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message-1423371509937733744

2025-10-02T18:10:12.933+00:00 — Tholin (@tholin)

Content

Bad time for me to be designing analog layouts?
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message-1423372893454340157

2025-10-02T18:15:42.789+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tholin :  Great time for you to be designing analog layouts!  That will help flush out a lot of issues.  Make sure that you spot-check designs against the documented rules occasionally and let me know about anything that looks wrong.  Feel free to post a layout to me if you want me to double-check it for issues.
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message-1423373178717081751

2025-10-02T18:16:50.801+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

See what @Tim Edwards said! 🙂
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message-1423374124025380885

2025-10-02T18:20:36.18+00:00 — Tholin (@tholin)

Content

Alright, sounds good.
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message-1423374134691233884

2025-10-02T18:20:38.723+00:00 — Tholin (@tholin)

Content

I'll keep going.
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message-1423839895746777170

2025-10-04T01:11:24.812+00:00 — Evansika (@xintingjiang_36756)

Content

I'm curious what is the current problem of this template, is this made the nov gf180 mpw shuttle
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message-1423843050928734371

2025-10-04T01:23:57.066+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Evansika - It should be usable but just keep it up to date as you go.

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message-1423936630435348600

2025-10-04T07:35:48.159+00:00 — Leo Moser (mole99) (@mole99)

Content

Exactly. You can already get started with your design, just make sure to keep it up to date with the upstream template.

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message-1426404329589440582

2025-10-11T03:01:33.485+00:00 — asc (@asc9742)

Content

@Leo Moser (mole99) Hi Leo, I am trying to replace all 56 user pads with analog pads (gf180mcu_fd_io_asig_5p0). Got this error "No shape in terminal analog[0\].pad/ASIG5V found on layer Metal5". Any ideas on this issue? Attached a screenshot + the yaml and system verilog files.

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message-1426484568977969203

2025-10-11T08:20:24.046+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Hi @asc, there was a port missing for the bondpad BTerm in the `gf180mcu_fd_io__asig_5p0` cell.
If you update your PDK, it should run through now.

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message-1426613389794218025

2025-10-11T16:52:17.322+00:00 — asc (@asc9742)

Content

Thank you @Leo Moser (mole99) Ran into a new problem with the global routing. I had exchanged all user pads with analog pads, including the clk and rst pad. Could that be causing an issue?

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message-1426802036200177767

2025-10-12T05:21:54.13+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Yes, that will be a problem. The SDC expects at least one clock. Can you share a repository with your current state? I will take a look tomorrow.
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message-1427264381766602849

2025-10-13T11:59:05.903+00:00 — Leo Moser (mole99) (@mole99)

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Started a thread.
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message-1428379167623483543

2025-10-16T13:48:51.563+00:00 — Leo Moser (mole99) (@mole99)

Content

The [precheck](https://github.com/wafer-space/gf180mcu-precheck) has been updated to finish cleanly with the example project.
The precheck is your gateway to fabrication and will need to be completed via the online platform (coming soon).
You can, of course, run it locally to more easily debug failures.

If you are working on a design, please give it a try and let us know how it goes (SRAMs should still throw errors, that's being worked on next).
Most importantly: please let us know if you can "cheat" your way through the precheck 😉
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message-1428383834310705192

2025-10-16T14:07:24.188+00:00 — Tholin (@tholin)

Content

@Leo Moser (mole99) I just updated my project with the changes from the template and since one of the commits reads "Update LibreLane", I tried running LL on example_project again to see if the error during GLB is gone. Instead, it now fails even earlier during STA.
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message-1428390852098785294

2025-10-16T14:35:17.359+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1428484368317288482

2025-10-16T20:46:53.363+00:00 — Alf (@jalf_47390)

Content

@Leo Moser (mole99) Is there any ESD protection in the IO pins in the template or is it required to be added? If it is in there already, what did you include? Same for all pins differences between them?
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2025-10-17T04:56:22.454+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1429637487839412244

2025-10-20T01:08:58.481+00:00 — BreakingTaps (@polyfractal)

Content

how much memory does the `make librelane` step need (roughly)? I fired up an old linux laptop to play around with everything and it crashed after eating 16gb RAM + 4gb swap 🙂  Curious if I should just increase swap and let it run, or if it really needs like 32 or 64gb?
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message-1429680116857835631

2025-10-20T03:58:22.031+00:00 — BreakingTaps (@polyfractal)

Content

more swap did the trick 🙂

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message-1429718961460740197

2025-10-20T06:32:43.306+00:00 — Leo Moser (mole99) (@mole99)

Content

It depends on your design 😁
Yesterday, I implemented the example template on my laptop, which also has 16 GB of RAM, and it had to use swap as well.

The step that uses the most memory atm is most likely the filler generation.
There you can easily trade off memory consumption by changing the number of tiles (threads) and their size.
I will add some LibreLane configuration variables so that this can be easily tweaked directly from the config.
In the meantime, you can pass the `--jobs` argument to LibreLane to limit the global thread limit across all steps.

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message-1429736124485468221

2025-10-20T07:40:55.29+00:00 — Leo Moser (mole99) (@mole99)

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Never mind, none of that will be necessary anymore 😅

I've just fixed an embarrassing bug in the filler generation script: https://github.com/wafer-space/gf180mcu/commit/57a5725eb4a722cb148ff8cf84c5f22ce0be8d64
Now, filler generation uses only a fraction of the memory and completes much faster.
Always double check how functions are supposed to be used (the naming actually said it all 😄).

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message-1429736638183112796

2025-10-20T07:42:57.765+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Please update your project templates and pull the latest changes from the PDK!
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message-1429829395748618331

2025-10-20T13:51:32.892+00:00 — BreakingTaps (@polyfractal)

Content

awesome, thanks @Leo Moser (mole99)!

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message-1429956671538462871

2025-10-20T22:17:17.805+00:00 — Matt Venn (@mattvenn)

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when will the submission system be open?

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message-1430078825949302794

2025-10-21T06:22:41.686+00:00 — Leo Moser (mole99) (@mole99)

Content

That's for @Tim 'mithro' Ansell to say.
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2025-10-21T08:53:49.173+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Matt Venn - Hopefully in the next week.
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message-1432095138141966388

2025-10-26T19:54:47.974+00:00 — Tholin (@tholin)

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That's quite a lot of VDD and VSS pads on the template. Like 10 each. That seems a bit excessive. What is the max current per pad?
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2025-10-27T02:50:36.777+00:00 — Tim 'mithro' Ansell (@mithro_)

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message-1432199929308381245

2025-10-27T02:51:12.135+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - That was from @tnt in the #📦-cob channel.
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message-1432280680670298132

2025-10-27T08:12:04.76+00:00 — Tholin (@tholin)

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Ah, I see. Thank you.
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message-1434260033691980037

2025-11-01T19:17:19.295+00:00 — Tholin (@tholin)

Content

Getting some *extreme* hold violations when integrating a macro into chip_top that is not present when hardening the macro itself. Checking the logs, the worst slack is simply from the reset pad.

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message-1434261004640059584

2025-11-01T19:21:10.787+00:00 — Mark Anderson (@markemer)

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Is that in ns? If so, oof. And could it be a bad capacitance extraction on the pads themselves?
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message-1434262926935588874

2025-11-01T19:28:49.098+00:00 — tnt (@246tnt)

Content

That's probably because the macro has its own clock tree. So the clock that its internal FF sees is delayed by many ns compared to the clock on its input pin.
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message-1434263095223783486

2025-11-01T19:29:29.221+00:00 — tnt (@246tnt)

Content

If the CTS inside your top level project isn't setup to feed the macro an "early clock" (i.e. from the root of its clock tree instead of a leaf), that could explain why you see so many hold violations.
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message-1434263338614915323

2025-11-01T19:30:27.25+00:00 — tnt (@246tnt)

Content

(Just a theory of course ... can't do more than theorize without more data)
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message-1434267229641380091

2025-11-01T19:45:54.943+00:00 — Tholin (@tholin)

Content

Attachments

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message-1434267241695940679

2025-11-01T19:45:57.817+00:00 — Tholin (@tholin)

Content

I don't have a repo for this yet
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message-1434267407622602912

2025-11-01T19:46:37.377+00:00 — Tholin (@tholin)

Content

There is no CTS in the top level
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message-1434267463641464953

2025-11-01T19:46:50.733+00:00 — Tholin (@tholin)

Content

Actually, there is no standard cells in the top level
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message-1434267496206176286

2025-11-01T19:46:58.497+00:00 — Tholin (@tholin)

Content

Just macros
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message-1434285105123295467

2025-11-01T20:56:56.79+00:00 — Tholin (@tholin)

Content

I guess this calls for a custom SDC file. I started by copying the SDC file provided by efabless for user project macros and will progressively modify it.
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message-1434309402193563881

2025-11-01T22:33:29.663+00:00 — Tholin (@tholin)

Content

Literally nothing I do is changing the hold violations. Its refusing to budge.
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message-1434577038181662871

2025-11-02T16:16:59.055+00:00 — Tholin (@tholin)

Content

Almost got it. Commit soon. Just trying to clean up my SDC file.
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message-1434577181945626694

2025-11-02T16:17:33.331+00:00 — Tholin (@tholin)

Content

What’s the point of `set_driving_cell`? Does it automatically determine slew rates and delays, or do I still need to specify those manually?
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message-1434583563667378278

2025-11-02T16:42:54.852+00:00 — Tholin (@tholin)

Content

Doesn’t matter. I cannot `set_driving_cell -lib_cell gf180mcu_fd_io__bi_24t` inside my macro SDC files anyways:

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message-1434605559377825935

2025-11-02T18:10:19.038+00:00 — Leo Moser (mole99) (@mole99)

Content

Do you use the LibreLane version from the template or [this branch](https://github.com/librelane/librelane/pull/806)?
Otherwise the pad cells are not read in.
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message-1434607148691750922

2025-11-02T18:16:37.96+00:00 — Tholin (@tholin)

Content

I cannot use the LibreLane version from the template for my macros. Python error.

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message-1434607243642404976

2025-11-02T18:17:00.598+00:00 — Tholin (@tholin)

Content

I mean, the PDK Version
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message-1434607507182977086

2025-11-02T18:18:03.431+00:00 — Tholin (@tholin)

Content

The error during GPL I reported before persists, so I cannot use the LibreLane version.
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message-1434608290259664957

2025-11-02T18:21:10.131+00:00 — Tholin (@tholin)

Content

But I also don’t understand what `set_driving_cell` even does. Right now my approach has been to determine values to set on `set_input_delay` , `set_clock_latency`, `set_input_transition` and `set_clock_transition` by manually interpreting the values in the liberty files for the IO pads.
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message-1434608455112589353

2025-11-02T18:21:49.435+00:00 — Tholin (@tholin)

Content

Except when it comes to the internal bus inside the chip, where I have to rely on STA for numbers.
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message-1434608875151163474

2025-11-02T18:23:29.58+00:00 — Tholin (@tholin)

Reply/reference

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Actually, it seems fine now, at least on this one macro, but there is still a big difference in behavior.
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message-1434609128352907403

2025-11-02T18:24:29.948+00:00 — Tholin (@tholin)

Content

I just got to `Stage 37 - Resizer Timing Optimizations (Post-Clock Tree Synthesis)` on this CPU macro and on Iteration 0 its starting with a TNS of **-5042** compared to main librelane, where I got -250.
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message-1434609145411145881

2025-11-02T18:24:34.015+00:00 — Tholin (@tholin)

Content

I changed nothing about the config.
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message-1434609175060807761

2025-11-02T18:24:41.084+00:00 — Tholin (@tholin)

Content

Just switched LL versions.
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message-1434623827673088214

2025-11-02T19:22:54.539+00:00 — Tholin (@tholin)

Content

Yeah, I’m getting severe performance degradation in the wafer.space template LL version in two ways. The timings of the design are worse, and also the flows take forever to run. After one hour, it is still stuck in Timing Optimizations. This whole flow used to take < 15 minutes. @Leo Moser (mole99)
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message-1434699626266628247

2025-11-03T00:24:06.332+00:00 — Tholin (@tholin)

Content

@Leo Moser (mole99) This page linked in the README of the template no longer exists.

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message-1434699690670293082

2025-11-03T00:24:21.687+00:00 — Tholin (@tholin)

Content

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message-1434803442999758869

2025-11-03T07:16:38.17+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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The wafer.space gf180mcu PDK requires the LibreLane version in the template (or from the branch).
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message-1434803668594458634

2025-11-03T07:17:31.956+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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The issue is still open at OpenROAD's side: https://github.com/The-OpenROAD-Project/OpenROAD/issues/8229
However, as mentioned before, you can simply disable timing driven placement.
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message-1434803878431428668

2025-11-03T07:18:21.985+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

`set_driving_cell` automates exactly that. It takes the values directly from the LIB.
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message-1434804194950385685

2025-11-03T07:19:37.449+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Thanks for reminding me. The LibreLane docs have recently been updated.
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message-1434817588004651058

2025-11-03T08:12:50.602+00:00 — Tholin (@tholin)

Reply/reference

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Thank you. I could find 0 information about this command online.
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message-1434820197088235530

2025-11-03T08:23:12.656+00:00 — tnt (@246tnt)

Content

https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf

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message-1435004359841681409

2025-11-03T20:35:00.478+00:00 — Leo Moser (mole99) (@mole99)

Content

This is the ✨ magic ✨ line for the `gf180mcu_fd_ip_sram__sram512x8m8wm1` SRAM:

```
add_pdn_stripe -grid macro -layer Metal4 -width 2.36 -offset 1.18 -spacing 0.28 -pitch 426.86 -starts_with GROUND -number_of_straps 2
```

It adds a power/ground pair on each side of the SRAM macro, directly above the pins. Since this uses the local coordinate system of the macro, you can move the macro around as you wish, the PDN straps will follow. As the PDN straps go all the way across the macro, connecting them to the PDN above is very easy.

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message-1435004439797956719

2025-11-03T20:35:19.541+00:00 — Leo Moser (mole99) (@mole99)

Content

(top left)

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message-1435004487654969427

2025-11-03T20:35:30.951+00:00 — Leo Moser (mole99) (@mole99)

Content

(top right)

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message-1435004532836008006

2025-11-03T20:35:41.723+00:00 — Leo Moser (mole99) (@mole99)

Content

If you rotate the SRAM by 90 or 270 degrees, you need to use this line:

```
add_pdn_stripe -grid sram_macros_WE -layer Metal4 -width 2.36 -offset 1.18 -spacing 0.28 -pitch 479.88 -starts_with GROUND -number_of_straps 2
```

Unfortunately, the connection to VSS is not as good on the right side. It is better to use the first orientation.

Don't forget the PDN connect:

```
add_pdn_connect \
    -grid macro \
    -layers "$::env(PDN_VERTICAL_LAYER) Metal3"
```
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message-1435004562065850599

2025-11-03T20:35:48.692+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1435004601316151296

2025-11-03T20:35:58.05+00:00 — Leo Moser (mole99) (@mole99)

Content

Now I just need to make magic DRC happy, and then I can push the the example usage of the SRAM to the template repo.
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message-1435004633788715160

2025-11-03T20:36:05.792+00:00 — Tholin (@tholin)

Content

Awesome
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message-1435004753900732638

2025-11-03T20:36:34.429+00:00 — Tholin (@tholin)

Content

I re-used my setup from GFMPW with a wrapper macro for the SRAM that just added the Metal4 strips.
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message-1435004839334641674

2025-11-03T20:36:54.798+00:00 — Tholin (@tholin)

Content

Which is not optimal
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message-1435005053751525518

2025-11-03T20:37:45.919+00:00 — Leo Moser (mole99) (@mole99)

Content

Well, if I remember correctly, Efabless used your solution too :)
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message-1435005104637087744

2025-11-03T20:37:58.051+00:00 — Tholin (@tholin)

Content

Yeah. That’s where I got it from.

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message-1435007091634081833

2025-11-03T20:45:51.788+00:00 — Leo Moser (mole99) (@mole99)

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message-1435507284083216394

2025-11-05T05:53:26.961+00:00 — Greg (@greg.hashtag.9468)

Content

I've setup a new system following the readme. And then just run the stock template as a sanity check, it does complete. But I'm seeing KLayout DRC errors. (along with timing/cap/slew warnings at some corners)
```
...
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    "DF.12": 3,
    "NW.2b_MV": 16,
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}
```
Is this expected? Or does it indicate something I should debug with my environment first?
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message-1435533621879636013

2025-11-05T07:38:06.381+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1435939978277289994

2025-11-06T10:32:49.296+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 It's update time!

The project template has been updated with support for the foundry SRAMs!
Two SRAMs of type `sram512x8m8wm1` are instantiated in `chip_core` and placed inside the chip in two different orientations (north and east).
If you add more SRAMs, make sure to update the LibreLane config (`librelane/config.yaml`) and the PDN configuration (`librelane/pdn_cfg.tcl`).

In addition, an issue has been fixed with filler generation, the way how the KLayout DRC deck was invoked (connectivity rules), and an error in the seal ring generator. With these changes the template is now DRC clean for both the magic and KLayout DRC deck.
Furthermore, the design is LVS clean and the there are no setup and hold violations for this example.

Please update your projects to the latest template, and don't forget to update the PDK as well (`make clone-pdk`).
Let me know if you have any questions.

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message-1436124590433898517

2025-11-06T22:46:24.264+00:00 — Tholin (@tholin)

Content

Updated my AS2650v2 wafer.space port to use the new method for instantiating SRAMs.

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message-1436124616027541604

2025-11-06T22:46:30.366+00:00 — Tholin (@tholin)

Content

Works!
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message-1436230350459113503

2025-11-07T05:46:39.419+00:00 — Leo Moser (mole99) (@mole99)

Content

Great to hear 👏🏻
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message-1436325234985930822

2025-11-07T12:03:41.653+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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message-1436325351360954449

2025-11-07T12:04:09.399+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) - Has performance / RAM usage changed much in the latest updates?
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message-1436330854979731617

2025-11-07T12:26:01.564+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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RAM usage has gone down drastically during the filler generation step after I fixed a bug there. However, that was already before this update.
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message-1439926964969275474

2025-11-17T10:35:40.998+00:00 — tnt (@246tnt)

Content

How long does the template build (default) take for people ?
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message-1439927022875967528

2025-11-17T10:35:54.804+00:00 — tnt (@246tnt)

Content

Just wondering if my vm is slow or something ...
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message-1439927826559270964

2025-11-17T10:39:06.417+00:00 — Leo Moser (mole99) (@mole99)

Content

The CI takes around 50mins without DRC: https://github.com/wafer-space/gf180mcu-project-template/actions/runs/19297076321/job/55181634117
Locally, it's faster for me. The DRC can then take an additional 1–1.5 hours.

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message-1439972280255119401

2025-11-17T13:35:45.004+00:00 — tnt (@246tnt)

Content

Here full run took 3h30 😅
Looking at timestamps, klayout drc was 2h 48 min of that.
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message-1439972534648049805

2025-11-17T13:36:45.656+00:00 — Tholin (@tholin)

Content

What? My top-level DRC runs don't take nearly as long.
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message-1439972729301372988

2025-11-17T13:37:32.065+00:00 — Tholin (@tholin)

Content

I'm also still struggling with analog pads not getting wired up.
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message-1439983108387504268

2025-11-17T14:18:46.632+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Just had a full run (inlcuding DRC) in 48:05 using the template 😁
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message-1439983731615072389

2025-11-17T14:21:15.221+00:00 — tnt (@246tnt)

Content

Huh ... that's worrying ...
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message-1440038098594431016

2025-11-17T17:57:17.319+00:00 — Tholin (@tholin)

Content

Something changed. KLayout DRC is so much slower now.
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message-1440052055824929002

2025-11-17T18:52:44.982+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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There haven't been changes to the PDK for two weeks: https://github.com/wafer-space/gf180mcu
Although a number of changes are coming up.

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message-1440088467034869820

2025-11-17T21:17:26.091+00:00 — Tholin (@tholin)

Content

And why are my analog signals not getting routed?

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message-1440092074958393345

2025-11-17T21:31:46.287+00:00 — Tholin (@tholin)

Content

I CTRL+F’d for "analog" in the global routing logs and found nothing. Its skipping it.
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message-1440092580753969342

2025-11-17T21:33:46.878+00:00 — tnt (@246tnt)

Content

Are they defined any differently in your netlist ?
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message-1440092978302685365

2025-11-17T21:35:21.661+00:00 — Tholin (@tholin)

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No
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message-1440302165473103977

2025-11-18T11:26:35.769+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Z80 design is finally green on github \o/
@Leo Moser (mole99) is there a way to download artifacts / GDS from github job for local inspection? *I feel quite dumb for asking, but I couldn't figure how to do it so far*

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message-1440303048307114004

2025-11-18T11:30:06.253+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Ah, when building locally on Mac it is necessary to increase file-descriptor count otherwise Magic streamout fails `ulimit -n 1024`
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message-1440303545113907371

2025-11-18T11:32:04.701+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Leo Moser (mole99) I tried to add `ulimit` to flake.nix as shell hook, but failing so far even with ChatGPT *"help"* 😓
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message-1440306419986464939

2025-11-18T11:43:30.124+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Hi ReJ! Congrats 👏
Just so you know, the CI only runs the implementation, as the DRC requires too much memory. So you need to make sure to run DRC locally.

Yes, there are ways to upload artifacts: https://docs.github.com/en/actions/tutorials/store-and-share-data
I haven't added this to the CI yet since I though it would quicky fill up the available storage space. But perhaps with a compression of the artifacts and a short retention time, it could be fine?

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message-1440307007667179520

2025-11-18T11:45:50.238+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

For some reason I get hold violations when I build locally (MacOS could be a problem here 😉 ), but it is fine building on github. Investigating atm.
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message-1440310351068663981

2025-11-18T11:59:07.367+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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The Nix flake in the template uses LibreLane's create-shell: https://github.com/librelane/librelane/blob/dev/nix/create-shell.nix
It seems that mkShell has a `shellHook` that could be used for that. However, I'm not sure how to override this from the template.

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message-1440311244614668360

2025-11-18T12:02:40.405+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Strange. There may be slight differences between the Linux and mac version of OpenROAD. If your hold violations are only just over the limit, perhaps that could make the difference.
Make sure your clock tree is good, and you could increase the `PL_RESIZER_HOLD_SLACK_MARGIN`.
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message-1440315995083374673

2025-11-18T12:21:33.005+00:00 — Tholin (@tholin)

Content

All of my configs contain
```
GRT_RESIZER_HOLD_SLACK_MARGIN: 0.1
PL_RESIZER_HOLD_SLACK_MARGIN: 0.1
PL_RESIZER_HOLD_MAX_BUFFER_PCT: 100
```
by default now since I had hold violations screw me over before.

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message-1440322064731865170

2025-11-18T12:45:40.122+00:00 — bailey (@bailey8889)

Content

@ReJ aka Renaldas Zioma If you're just running a batch job with no editing, you probably don't need file locking. Disabling this with the magic command `locking disable` may allow you to load large designs without changing the ulimit. http://opencircuitdesign.com/magic/commandref/locking.html

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message-1440366765631737987

2025-11-18T15:43:17.647+00:00 — LukeW (@luke_w)

Content

Is it expected to get some antenna violations from building the project template?
```
* Antenna
Failed 𐄂
Pin violations: 17
Net violations: 11
Check the report directory of OpenROAD.CheckAntennas.
```

checking the CI run here I do see the same violations: https://github.com/wafer-space/gf180mcu-project-template/actions/runs/19297076321/job/55181634117

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message-1440367730724180058

2025-11-18T15:47:07.743+00:00 — tnt (@246tnt)

Content

Yes
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message-1440367858734333963

2025-11-18T15:47:38.263+00:00 — LukeW (@luke_w)

Content

Ok, thanks 🙂 are they concerning or just something to waive?
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message-1440373072594075779

2025-11-18T16:08:21.344+00:00 — Leo Moser (mole99) (@mole99)

Content

That is something that requires a closer look into OpenROAD and LibreLane in order to find a proper solution. For large ratios you can manually insert ECO diodes.

So far, most (all?) Tiny Tapeout designs seem to work just fine, and almost all of them have some antenna violations.

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message-1440373327947497514

2025-11-18T16:09:22.225+00:00 — Leo Moser (mole99) (@mole99)

Content

Search for `INSERT_ECO_DIODES` in https://librelane.readthedocs.io/en/latest/reference/step_config_vars.html
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message-1440392460374380674

2025-11-18T17:25:23.751+00:00 — LukeW (@luke_w)

Content

Thanks, I guess I'll worry about that later then 😅

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message-1440392594667339807

2025-11-18T17:25:55.769+00:00 — LukeW (@luke_w)

Content

In `chip_core.sv` in the example project, why does it have `keep` attributes on the SRAM? Are they just left in from initial hacking or are they required?

```
    logic [7:0] sram_0_out;

    (* keep *)
    gf180mcu_fd_ip_sram__sram512x8m8wm1 sram_0 (
        `ifdef USE_POWER_PINS
        .VDD  (VDD),
        .VSS  (VSS),
        `endif

        .CLK  (clk),
        .CEN  (1'b1),
        .GWEN (1'b0),
        .WEN  (8'b0),
        .A    ('0),
        .D    ('0),
        .Q    (sram_0_out)
    );
```
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message-1440392850616483881

2025-11-18T17:26:56.792+00:00 — LukeW (@luke_w)

Content

I will happily cargo cult it into my own memory wrappers, I was just curious
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message-1440393268373356554

2025-11-18T17:28:36.393+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

The former. You should be able to remove the `(* keep *)` and since Yosys sees that the outputs of the macro are being used, it will keep it. I'll remove it the next time I push another change to the template :)
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message-1440393372199162037

2025-11-18T17:29:01.147+00:00 — LukeW (@luke_w)

Content

ok nice thanks, I thought that would be the case but wasn't sure if there were hidden gotchas

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message-1440393685962588261

2025-11-18T17:30:15.954+00:00 — LukeW (@luke_w)

Content

flow related question (if the answer is "RTFM" I can attempt to do that): in our ASIC flow at work, if I hand-instantiate a cell then the buffer width can be changed during layout but otherwise it'll remain the same cell with the same hierarchical path. Is that the case here or do I need to add `(* dont_touch keep *)` etc to my cell wrappers?
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message-1440394697498562761

2025-11-18T17:34:17.123+00:00 — Leo Moser (mole99) (@mole99)

Content

Cell attributes are currently not retained. You can set `SYNTH_WRITE_NOATTR` to false and they should be passed on to OpenROAD.
However, there's `RSZ_DONT_TOUCH_RX` and `RSZ_DONT_TOUCH_LIST` if you want to keep a cell or net untouched.
I think if you just set the `(* keep *)` attribute on a stdcell, Yosys will instantiate the stdcell and OpenROAD is free to change it's buffer width.

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message-1440394841656922294

2025-11-18T17:34:51.493+00:00 — LukeW (@luke_w)

Content

nice, thanks
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message-1440395016152416287

2025-11-18T17:35:33.096+00:00 — LukeW (@luke_w)

Content

so it sounds like just putting `(* keep *)` on my cells is what I want; quite happy for the tools to change the drive as I don't fancy going and fixing all the transition violations myself 🙂

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message-1440397289217855501

2025-11-18T17:44:35.037+00:00 — htamas (@h.tamas)

Reply/reference

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Content

FYI time driven placement (enabled by default) ignores the `RSZ_DONT_TOUCH_*` setting and resizes the cells nonetheless. You can work around it by setting `PL_TIME_DRIVEN` to 0.
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message-1440397970099929261

2025-11-18T17:47:17.372+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Yes, that is actually a "bug" in LibreLane as `dont_touch` does not prevent placement. So we could actually keep the attribute throughout GPL. See here: https://github.com/librelane/librelane/issues/695

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message-1440439604451872871

2025-11-18T20:32:43.775+00:00 — LukeW (@luke_w)

Content

Some incredibly minor DRCs (SRAM VDD/VSS *completely unconnected* while I figure out how the hierarchical paths are escaped) but in theory here is a processor, JTAG and 4 kB of RAM. Thanks for making the template, it made it super fast to get started 😄

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message-1440440213775319162

2025-11-18T20:35:09.049+00:00 — LukeW (@luke_w)

Content

Also I may have mixed up the SRAM dimensions and there is only a 15 um routing channel between the two rows 🤔
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message-1440475988063424522

2025-11-18T22:57:18.304+00:00 — LukeW (@luke_w)

Content

I'm guessing it's expected that the `librelane-magicdrc` makefile target crashes out during klayout/magic XOR, since klayout was skipped?
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message-1440476423059013804

2025-11-18T22:59:02.015+00:00 — LukeW (@luke_w)

Content

i.e.

```
Reading /home/luke/proj/riscboy-180/librelane/runs/RUN_2025-11-18_22-06-42/56-magic-streamout/chip_top.magic.gds ..
ERROR: In /nix/store/g3fml7j9yabcq2cmqm5yh19fxrm1h919-python3-3.12.10-env/lib/python3.12/site-packages/librelane/scripts/klayout/xor.drc: 'source': Stream has unknown format: /home/luke/proj/riscboy-180/librelane/runs/RUN_2025-11-18_22-06-42/56-magic-streamout/chip_top.magic.gds in Layout::read
Total elapsed: 0.010s  Memory: 413.00M
ERROR: RuntimeError: 'source': Stream has unknown format: /home/luke/proj/riscboy-180/librelane/runs/RUN_2025-11-18_22-06-42/56-magic-streamout/chip_top.magic.gds in Layout::read in Executable::execute
  /nix/store/g3fml7j9yabcq2cmqm5yh19fxrm1h919-python3-3.12.10-env/lib/python3.12/site-packages/librelane/scripts/klayout/xor.drc:78:in `execute'
  :/built-in-macros/drc_interpreters.lym:31:in `instance_eval'
  :/built-in-macros/drc_interpreters.lym:31:in `execute'
/home/luke/proj/riscboy-180/librelane/runs/RUN_2025-11-18_22-06-42/56-magic-streamout/chip_top.magic.gds
/home/luke/proj/riscboy-180/librelane/runs/RUN_2025-11-18_22-06-42/57-klayout-streamout/chip_top.klayout.gds
```

if it's a known issue with that target then I won't bother debugging 🙂
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message-1440478026574856404

2025-11-18T23:05:24.323+00:00 — LukeW (@luke_w)

Content

Does this YAML config go anywhere other than `chip_top.sdc`?

```
# Clock
CLOCK_PORT: clk_PAD
CLOCK_NET: clk_pad/Y

CLOCK_PERIOD: 40 # 25 MHz
```

I saw the warning about multiple clocks in there but hoping I can just ignore that and write a normal `.sdc` file.
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message-1440602669537558573

2025-11-19T07:20:41.521+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1440603218169172058

2025-11-19T07:22:52.325+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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From what I know, this is only passed on to the SDC file.
Yes, you should be able to fully customize your SDC.

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message-1440610129904009306

2025-11-19T07:50:20.211+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Content

DRC is passing (minus some antenna violations).
Tiny Z80 looks so lonely in there.

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message-1440611454196776984

2025-11-19T07:55:35.947+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Leo Moser (mole99)  However I ran into some problems with `gf180mcu-precheck` repository. It:
- crashes on my Ubuntu machine (*perhaps running out of memory, investigating*) during the Density check
- fails to find qrcode library on OSX machine (*Error: Couldn't load the qrcode library.  *)
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message-1440612198236950558

2025-11-19T07:58:33.34+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Congrats! 👏
You did enable the environment within the precheck, right?
Because I specifically request the `qrcode` Python module 😅
https://github.com/wafer-space/gf180mcu-precheck/blob/1b639dff3d87a50e0759541701c7d162e1765630/flake.nix#L47
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message-1440613393382768740

2025-11-19T08:03:18.285+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Content

ah, this might be the problem `pkgs.stdenv.isLinux`

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message-1440613812658110546

2025-11-19T08:04:58.248+00:00 — Leo Moser (mole99) (@mole99)

Content

You're absolutely right! It's a leftover from a different flake, I completely overlooked it.
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message-1440613881881038952

2025-11-19T08:05:14.752+00:00 — Leo Moser (mole99) (@mole99)

Content

Pushing a fix shortly...

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message-1440614893429592084

2025-11-19T08:09:15.924+00:00 — Leo Moser (mole99) (@mole99)

Content

@ReJ aka Renaldas Zioma You can give it another try now.

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message-1440657952662098023

2025-11-19T11:00:22.045+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Content

Worked like a charm. Precheck passed!

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message-1440717107729006732

2025-11-19T14:55:25.712+00:00 — BreakingTaps (@polyfractal)

Content

is there an additional log to get more information about librelane build failures? Trying a test build of what I have to see the end-to-end workflow, and it's failing to wire up power pins to my sram macos (deep in the bowels of my project)

```
Connecting power net VDD to i_chip_core.u_core.tta_0.lsu_fu_0.sram_512x32_0.gf180mcu_fd_ip_sram__sram512x8m8wm1_0/VDD…
[INFO] Made 0 connections.
[06:50:13] ERROR    The following error was encountered while running the flow:  __main__.py:189
    Odb.SetPowerConnections failed with the following errors:
         add_global_connections failed to make any connections for 'i_chip_core.u_core.tta_0.lsu_fu_0.sram_512x32_0.gf180mcu_fd_ip_sram__sram512x8m8wm1_0/VDD' to VDD.
```

I've gone through and added the conditional stuff where needed
```
`ifdef USE_POWER_PINS
.VDD  (VDD),
.VSS  (VSS),
`endif
```
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message-1440718077145780338

2025-11-19T14:59:16.839+00:00 — BreakingTaps (@polyfractal)

Content

ah... yosys is deleting my sram module (and a bunch of other stuff)

`Deleting now unused module tta::sram::sram_512x32.  `

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message-1440718373267968030

2025-11-19T15:00:27.44+00:00 — BreakingTaps (@polyfractal)

Content

ok new question.... why? 😂  I know there's a "keep" annotation to force it, but I don't think any of this is dead code? but I have no idea how synthesizing works
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message-1440718399096488086

2025-11-19T15:00:33.598+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

You can find all log files and artifacts in the `librelane/runs/*` directory.
Making the power connections in the RTL is one way, the other is to use `PDN_MACRO_CONNECTIONS`.

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message-1440718587252703373

2025-11-19T15:01:18.458+00:00 — BreakingTaps (@polyfractal)

Content

aha! `PDN_MACRO_CONNECTIONS` looks much more convenient
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message-1440718760406421585

2025-11-19T15:01:59.741+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes, if Yosys removes the SRAM instances, it's because it recognises that none of the outputs are being used. Optoimizing it away 😁
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message-1440718835069227210

2025-11-19T15:02:17.542+00:00 — Leo Moser (mole99) (@mole99)

Content

So there is probably an issue in your RTL.
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message-1440719811884744905

2025-11-19T15:06:10.433+00:00 — BreakingTaps (@polyfractal)

Content

hm, it seems to be deleting basically my entire project 😄

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message-1440720685709393920

2025-11-19T15:09:38.769+00:00 — BreakingTaps (@polyfractal)

Content

if a module doesn't have an output, does it get optimized away? I've only wired up inputs to my processor so far (clock, reset, uart loading, etc). so it can run programs but no output
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message-1440721609139818540

2025-11-19T15:13:18.932+00:00 — Tholin (@tholin)

Content

Yes. Yosys checks input to output paths to see what it can optimize away, in my experience.

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message-1440721681357476024

2025-11-19T15:13:36.15+00:00 — Tholin (@tholin)

Content

If it sees 0 outputs, it just goes "this whole design is just void"
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message-1440721771828478092

2025-11-19T15:13:57.72+00:00 — BreakingTaps (@polyfractal)

Content

argh
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message-1440721786349162567

2025-11-19T15:14:01.182+00:00 — BreakingTaps (@polyfractal)

Content

gotcha, thanks!
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message-1440732179671027742

2025-11-19T15:55:19.143+00:00 — BreakingTaps (@polyfractal)

Content

wired in a temporary output, got the ball moving again! Just to confirm, it looks like the sram macros have to be placed manually on the die? (I see the placement stuff in pdn_cfg.tcl for the two macros in the demo chip_top)
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message-1440732347073826957

2025-11-19T15:55:59.055+00:00 — BreakingTaps (@polyfractal)

Content

and in the config toml
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message-1440732937166524478

2025-11-19T15:58:19.744+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes exactly. Placement is defined in `config.yaml` and connection to PDN in `pdn_cfg.tcl`.
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message-1440733407674896454

2025-11-19T16:00:11.922+00:00 — BreakingTaps (@polyfractal)

Content

great, thank you! out of curiosity, is there a reason placements are done by hand instead of being auto-placed by librelane? because they are so large you want a human to do it?
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message-1440734102645903411

2025-11-19T16:02:57.616+00:00 — BreakingTaps (@polyfractal)

Content

(entirely new to this whole world, so lacking a lot of background context 🙂 )
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message-1440738136282894538

2025-11-19T16:18:59.31+00:00 — Leo Moser (mole99) (@mole99)

Content

No problem! In our case, manual placement is mostly fine, since there are only a handful of SRAM macros to place.
There was some effort to integrate OpenROAD's automatic macro placer into LibreLane, but it wasn't completed: https://github.com/librelane/librelane/issues/537
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message-1440742594534703286

2025-11-19T16:36:42.24+00:00 — BreakingTaps (@polyfractal)

Content

Makes sense. Juice probably isn't worth the squeeze given the nature of projects here. Easier to do it by hand 🙂
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message-1440742679959830673

2025-11-19T16:37:02.607+00:00 — LukeW (@luke_w)

Reply/reference

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Content

Not my domain (I do frontend) but I can take a couple of guesses at the reasons:

1. Difficult to move large macros later in pnr due to the number of ripups, so there's a high likelihood of automatic placement backing itself into a corner and making the design unroutable.

2.  Desire for consistency between implementation runs -- implementation is usually iterative with new RTL updates  regularly coming in, and you want to know whether issues are due to RTL changes etc as opposed to just the tools having a bad day

3. The power connections to macros like SRAMs etc are usually hand-tuned for best results, and you don't want to rip this up every time

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message-1440742862307201134

2025-11-19T16:37:46.082+00:00 — LukeW (@luke_w)

Content

At least that's for the commercial projects I've worked on. Different dynamics for the new open-source stuff
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message-1440742955701899376

2025-11-19T16:38:08.349+00:00 — BreakingTaps (@polyfractal)

Content

Ahh interesting!
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message-1440743215333638165

2025-11-19T16:39:10.25+00:00 — tnt (@246tnt)

Content

I'd love to have suggestions though. Like it would just do a rough electrostatic-style placement  of all standard cells and macro to sort of see how things arrange themselves and make sure I'm not placing those macro at a very inconvenient spot.

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message-1440743282551558256

2025-11-19T16:39:26.276+00:00 — tnt (@246tnt)

Content

And then I can lock it there and never move it while refining RTL.
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message-1440743339795157103

2025-11-19T16:39:39.924+00:00 — LukeW (@luke_w)

Content

Yeah, like BRAM locking on FPGA 😅
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message-1440743947029975144

2025-11-19T16:42:04.7+00:00 — LukeW (@luke_w)

Content

It's a really interesting question, I never thought about it. I just sort of accepted the layout folks at work spent days gently massaging the RAMs into place
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message-1440759548792143903

2025-11-19T17:44:04.45+00:00 — BreakingTaps (@polyfractal)

Content

still not 100% confident yosys didnt optimize away half the design and my laptop locked up so I'm not sure if it actually completed successfully before I had to go to work...but it did finish enough to generate an output GDS 🥳

so much unused space 😂

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message-1440762626924609678

2025-11-19T17:56:18.334+00:00 — asic destroyer (@logic_destroyer)

Content

My custom ASIC KianV SV32 SoC is now finalized!
RV32IMA + Zicntr/Zicsr/Zifencei/SSTC with full MMU — running uLinux, Linux, and xv6.
With huge help from @Leo Moser (mole99)  — and thanks to
@Tim 'mithro' Ansell

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message-1440765608374435946

2025-11-19T18:08:09.167+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

Started a thread.
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message-1440765650959339613

2025-11-19T18:08:19.32+00:00 — asic destroyer (@logic_destroyer)

Content

It will run mailine linux/uLinux/XV6 Unix or newer

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message-1440771256067686582

2025-11-19T18:30:35.682+00:00 — asic destroyer (@logic_destroyer)

Content

I’ve shared a Python script to render the chip layout from GDS. It’s pretty slow and memory-hungry, but it works. I’ll put it on my GitHub repo later.

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message-1440772076347588668

2025-11-19T18:33:51.252+00:00 — BreakingTaps (@polyfractal)

Content

definitely will try that when I get home!
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message-1440776133326143540

2025-11-19T18:49:58.511+00:00 — Tholin (@tholin)

Content

This script generates 3D models and is multithreaded
https://github.com/AvalonSemiconductors/gfmpw1-multi/blob/main/gds2gltf.py

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message-1440777208070406245

2025-11-19T18:54:14.75+00:00 — asic destroyer (@logic_destroyer)

Content

Richtig geil...danke
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message-1440780450455879811

2025-11-19T19:07:07.795+00:00 — Leo Moser (mole99) (@mole99)

Content

And here is my entry in the list of layout renderers. It simply uses KLayout (`pip install klayout`) to render the layout and can therefore load both GDS and OAS. I disabled the filler layers to make the layout stand out better.
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message-1440780471087661096

2025-11-19T19:07:12.714+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1440780616185413673

2025-11-19T19:07:47.308+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1440780832716357824

2025-11-19T19:08:38.933+00:00 — Leo Moser (mole99) (@mole99)

Content

You can run it as `python3 lay2img.py librelane/runs/<timestamp>/final/gds/chip_top.gds image --width 4069 --height 6144` in the root of your repository.
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message-1440785965433225346

2025-11-19T19:29:02.668+00:00 — Tholin (@tholin)

Content

Rendering the AS2650-2 with @asic destroyer ’s script shows some missing wires.

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message-1440786225685598378

2025-11-19T19:30:04.717+00:00 — Tholin (@tholin)

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Watch your RAM use running this, btw. It gets intense.

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message-1440805198070284378

2025-11-19T20:45:28.086+00:00 — Tim 'mithro' Ansell (@mithro_)

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Super cool!

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2025-11-19T20:47:14.722+00:00 — Tim 'mithro' Ansell (@mithro_)

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Started a thread.
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2025-11-19T20:50:05.024+00:00 — Tim 'mithro' Ansell (@mithro_)

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What MCU is that Hazard3?
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2025-11-19T20:52:30.361+00:00 — Tim 'mithro' Ansell (@mithro_)

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Started a thread.
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2025-11-19T20:54:48.207+00:00 — Tim 'mithro' Ansell (@mithro_)

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Automatic macro placement stuff was one of the big things that Google's ML team did for the TPU

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message-1440807778670219445

2025-11-19T20:55:43.349+00:00 — Tim 'mithro' Ansell (@mithro_)

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https://github.com/google-research/circuit_training

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message-1440807955883757660

2025-11-19T20:56:25.6+00:00 — LukeW (@luke_w)

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Yep, it's Hazard3. There will be at least two of them once I'm done (one for main game firmware and one for audio processing)
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2025-11-19T20:56:43.759+00:00 — Tim 'mithro' Ansell (@mithro_)

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What about one for graphics? 😛
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message-1440808075081814047

2025-11-19T20:56:54.019+00:00 — LukeW (@luke_w)

Content

RISCBoy PPU is already quite programmable
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message-1440808138784636938

2025-11-19T20:57:09.207+00:00 — LukeW (@luke_w)

Content

and can do affine blits and stuff at 1 pix/clk
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message-1440808196150263891

2025-11-19T20:57:22.884+00:00 — LukeW (@luke_w)

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so I'm planning to use that with external parallel async SRAM
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message-1440808302824128664

2025-11-19T20:57:48.317+00:00 — LukeW (@luke_w)

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serial SPI LCD

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message-1440808342405775433

2025-11-19T20:57:57.754+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Leo Moser (mole99) - Maybe LibreLane needs container limits to stop locking computers up or something?
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message-1440808499461226546

2025-11-19T20:58:35.199+00:00 — LukeW (@luke_w)

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would love to do DVI out but if I only have 13 days til final GDS then now is not the time for custom layout 😅

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message-1440808727077978243

2025-11-19T20:59:29.467+00:00 — LukeW (@luke_w)

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I'll probably have some std cell-based DCOs on board to play with generating internal clocks but nothing of the quality you'd need for DVI
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message-1440808757973094543

2025-11-19T20:59:36.833+00:00 — Tim 'mithro' Ansell (@mithro_)

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Sleep is for the weak 😉
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message-1440808799861473412

2025-11-19T20:59:46.82+00:00 — LukeW (@luke_w)

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sleep is for two weeks from now
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message-1440810948859269253

2025-11-19T21:08:19.181+00:00 — Tholin (@tholin)

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Oh. Tapeout is that soon?
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message-1440810972125073509

2025-11-19T21:08:24.728+00:00 — Tholin (@tholin)

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Uhhhhh
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message-1440810993876865297

2025-11-19T21:08:29.914+00:00 — Tholin (@tholin)

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Yeah, sleep is indeed for two weeks from now
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message-1440811759643525161

2025-11-19T21:11:32.487+00:00 — Tim 'mithro' Ansell (@mithro_)

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Dammit, there is too many cool things to look at in this channel and I need to be finishing the GDS prechecking on platform.wafer.space

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message-1440812231402065981

2025-11-19T21:13:24.963+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

Ja, Leo ist richtig geil!

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message-1440830200366497923

2025-11-19T22:24:49.098+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

We definitely need a gallery or something!

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message-1440837674217766993

2025-11-19T22:54:31.003+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

hehe well I think we can blame my laptop for this one. the display/linux controlling it seems to get flaky in memory-constrained circumstances
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message-1440837751304884247

2025-11-19T22:54:49.382+00:00 — BreakingTaps (@polyfractal)

Content

(i also forgot to boost swap before starting it)
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message-1441095243041865820

2025-11-20T15:58:00.196+00:00 — asic destroyer (@logic_destroyer)

Content

How we can do the same here, excluding gf180mcu_fd_sc_mcu7t5v0__oai21_1  @Leo Moser (mole99)
https://discordapp.com/channels/1009193568256135208/1438584424554827788
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message-1441113806041383023

2025-11-20T17:11:45.96+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Since the last announcement, a number of important changes have been made to both the PDK and the template.

### PDK

1. [#3](https://github.com/wafer-space/gf180mcu/pull/3): The seal ring generator has been updated.
    - Now actually includes the glass cut.
    - Pplus does not overlap comp, as required by DRC.
2. [#3](https://github.com/wafer-space/gf180mcu/pull/3): Filler generation has been updated to ensure 10um spacing to the seal ring. (This was only a problem for smaller slot sizes).

### Template

1. The core ring now [connects to all vss pads again](https://github.com/wafer-space/gf180mcu-project-template/commit/c119e25b04b1dc3619bcd66cb508f901fd976410). (thanks @tnt!)
2. [#22](https://github.com/wafer-space/gf180mcu-project-template/pull/22): Magic has been updated with fix that significantly reduces peak memory usage.
3. [#21](https://github.com/wafer-space/gf180mcu-project-template/pull/21): The `render-image` Make target renders the GDS layout.
4. [#21](https://github.com/wafer-space/gf180mcu-project-template/pull/21): The CI has been updated.
    - Commands in the nix shell are now only executed once. (thanks @Egor Lukyanchenko!)
    - Create a summary and upload artifacts (gds and image) ([Example](https://github.com/wafer-space/gf180mcu-project-template/actions/runs/19543720582))
5. [#23](https://github.com/wafer-space/gf180mcu-project-template/pull/23): Workaround for a PDN issue.
6. [#24](https://github.com/wafer-space/gf180mcu-project-template/pull/24): Fix antenna violations using `DRT_ANTENNA_REPAIR_ITERS` (disable if any issues occur).
7. The [PDK version](https://github.com/wafer-space/gf180mcu-project-template/commit/b20168925c46fdd292e6084f31bfd8d312379d7e) has been pinned.

Please update your repository in line with the template and clone the latest PDK.

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message-1441135690678145144

2025-11-20T18:38:43.664+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Pinned a message.
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message-1441173471253237901

2025-11-20T21:08:51.255+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) Is the environment of the leo/gf180 branch of libre lane good ? That's what I'm using since TT is not based at all on the template .
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message-1441188569279369409

2025-11-20T22:08:50.905+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Does the template have a CHANGELOG file or something? Seems like this would be great to include in that.
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message-1441188716428136468

2025-11-20T22:09:25.988+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) - BTW Did you see that I made the `git describe` version number work?
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message-1441308312556798013

2025-11-21T06:04:39.927+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Yes, the template uses `leo/gf180mcu` as well.
Unfortunately, I still need to rebase from time to time, so any commit hashes that you reference might break.
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message-1441309725151985795

2025-11-21T06:10:16.716+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) I meant the nix environment of the `leo/gf180mcu`.  Digging a bit I think the magic version is different.
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message-1441310110055006259

2025-11-21T06:11:48.484+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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@Leo Moser (mole99) it might be a red herring, but I think I started getting KLayout DRC violations when running a **precheck**. This started after merging the latest template changes.

I get 12 drc errors and if I read it correctly (`drc.klayout.lyrdb` file) errors are in **sealring**

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message-1441310617146495106

2025-11-21T06:13:49.384+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Right! I override the magic version in the template. There is no change in functionality, but it reduces peak RAM usage.
I can update nix-eda as a whole in the `leo/gf180mcu` branch once the latest Yosys hang is fixed.
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message-1441311164343783476

2025-11-21T06:15:59.846+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

ReJ, yes that is expected. Sorry! I still need to sync the precheck with the latest changes to the template. I started a run yesterday but didn't get to push the changes yet.
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message-1441311257704665110

2025-11-21T06:16:22.105+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes, we can use versions and a changelog for the template from now on.
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message-1441311475749748867

2025-11-21T06:17:14.091+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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I would prefer tags in the format `x.y.z`, like in the gf180mcu repository.
I'll update the tag.
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message-1441311766129934386

2025-11-21T06:18:23.323+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

with `git-describe` you get `v0.0-<commits>-<hash>` which some people map to `v0.0.<commits>`
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message-1441312059844202669

2025-11-21T06:19:33.35+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But I don't really care that enough, do what you prefer 🙂
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message-1441312271858012300

2025-11-21T06:20:23.898+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, `git-describe` is really neat 😁
I'm generally following the conventions in LibreLane to keep things simple.
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message-1441312391513112596

2025-11-21T06:20:52.426+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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no worries! Happy to hear it is expected

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message-1441314857751154852

2025-11-21T06:30:40.423+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Random piece of information, template project also works fine with gf180mcu_fd_sc_mcu**9t**5v0

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message-1441377382412845147

2025-11-21T10:39:07.464+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

You could give this PR a try: https://github.com/wafer-space/gf180mcu-precheck/pull/3

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message-1441435181008293938

2025-11-21T14:28:47.723+00:00 — tnt (@246tnt)

Content

Antenna check is taking forever 😥  It's been an hour and I think it's still at Metal1.
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message-1441436146935529514

2025-11-21T14:32:38.018+00:00 — Tholin (@tholin)

Content

I mean, you do have a lot of Metal1 in the layout if the whole core area has a standard cell grid in it.
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message-1441436258671788145

2025-11-21T14:33:04.658+00:00 — Tholin (@tholin)

Content

My flows are faster than average, I believe, because I only have macros in the top-level and no cell grids.
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message-1441436447319261204

2025-11-21T14:33:49.635+00:00 — tnt (@246tnt)

Content

Well the top level of TT doesn't have any cell grid 😅
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message-1441436600868278394

2025-11-21T14:34:26.244+00:00 — tnt (@246tnt)

Content

and this test sample is only maybe ... 15~20% filled.
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message-1441437376353140809

2025-11-21T14:37:31.134+00:00 — Tholin (@tholin)

Content

That’s probably already denser than my chip.
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message-1441437508352348291

2025-11-21T14:38:02.605+00:00 — Tholin (@tholin)

Content

But antenna check takes a few seconds for me, so something seems wrong there.
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message-1441438545670832212

2025-11-21T14:42:09.921+00:00 — tnt (@246tnt)

Content

Are you talking about KLayout.Antenna or OpenROAD.CheckAntennas step ?
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message-1441438859593388124

2025-11-21T14:43:24.766+00:00 — Tholin (@tholin)

Content

Both, I guess.
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message-1441438956645384355

2025-11-21T14:43:47.905+00:00 — Tholin (@tholin)

Content

A step getting stuck for that long would be quite memorable and I don’t remember anything other than STA and DRC taking forever.
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message-1441439080897445949

2025-11-21T14:44:17.529+00:00 — tnt (@246tnt)

Content

Well https://github.com/AvalonSemiconductors/ws-submission-2025/blob/main/librelane/config.yaml#L6
It's disabled in your default config so you'd have to enable it to see it.
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message-1441443103922978836

2025-11-21T15:00:16.693+00:00 — Tholin (@tholin)

Content

I just pushed to the repo
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message-1441443169341538476

2025-11-21T15:00:32.29+00:00 — Tholin (@tholin)

Content

Has my analog pad fixes now
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message-1441477448813514752

2025-11-21T17:16:45.153+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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@tnt Should we enable it?
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message-1441477726254010368

2025-11-21T17:17:51.3+00:00 — asic destroyer (@logic_destroyer)

Content

@Leo Moser (mole99)

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message-1441477883502530580

2025-11-21T17:18:28.791+00:00 — tnt (@246tnt)

Content

It's been running here for 4h ....
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message-1441477921226363117

2025-11-21T17:18:37.785+00:00 — tnt (@246tnt)

Content

so I get why it's disabled 😅

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message-1441505073581789215

2025-11-21T19:06:31.411+00:00 — LukeW (@luke_w)

Content

Does anyone know which step in the (template) flow is responsible for adding buffers on a high fanout net? I have a reset net with a fanout of ~1k and in my powered  netlist `./25-openroad-globalplacementskipio/chip_top.pnl.v` still has the reset synchroniser output going directly to all ~1k loads without buffering. This makes the following STAs meaningless because the reset net has like a 100 ns rise time
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message-1441515202679144510

2025-11-21T19:46:46.376+00:00 — LukeW (@luke_w)

Content

ah, somewhat answered my own questions:

1. the buffers are added in the `repairdesignpostgpl` step
2. my issue with insane violations was actually because removing the clock variables from your `.yaml` and just defining clocks in your `.sdc` completely skips CTS, so I had like a 450 ns clock rise/fall, and all the flop timings are derated according to slew

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message-1441526234793119836

2025-11-21T20:30:36.637+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Does anyone have a design which currently fails precheck quickly?
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message-1441526427546554539

2025-11-21T20:31:22.593+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I need some test cases for the manufacturability checking testing
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message-1441526545578594385

2025-11-21T20:31:50.734+00:00 — Tholin (@tholin)

Content

What if you just run precheck against a corrupted GDSII file so it fails just loading?
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message-1441528156736458862

2025-11-21T20:38:14.864+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Yeah, I can do those ones pretty easy, I'm other an otherwise compliant design that just has DRC violations.
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message-1441576949980856400

2025-11-21T23:52:08.08+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) - I believe your pull request to the precheck is now merged and the docker image got updated.
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message-1441696808806912081

2025-11-22T07:48:24.651+00:00 — tnt (@246tnt)

Content

Antenna check is going on 18h, so I think I'll give up on it 😅
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message-1441702972756332614

2025-11-22T08:12:54.251+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Thanks!
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message-1441703271667466280

2025-11-22T08:14:05.517+00:00 — Leo Moser (mole99) (@mole99)

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Yeah, I also remember it taking forever during my testing 😅
For the second shuttle, I can look into rewriting/improving the KLayout antenna checks (there have been some updates to KLayout), or using a magic antenna check. But I don't see how we can possibly enforce zero antenna violations on the first shuttle.
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message-1441713124112859238

2025-11-22T08:53:14.523+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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message-1441776246475456592

2025-11-22T13:04:04.067+00:00 — Noritsuna Imamura (@noritsunaimamura)

Content

I ran a precheck on the GDS with PDK updated to 1.1.0 and new Filler and Sealing.
It has been successfully completed.
It took 4 hours and 36 minutes on Ubuntu24.04. The PC specifications are: "Ryzen 3 Pro 4350G (4-core, 8-thread) & MEM: 64GB".

However, when running on WSL, Klayout crashed when signals such as SIGKILL were sent  or no response.
When I used about 14GB of memory, Klayout has crashed.

- Precheck Log
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/tree/main/precheck_log/RUN_2025-11-22_16-51-07
- Project GitHub
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1

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message-1441789668965355641

2025-11-22T13:57:24.238+00:00 — tnt (@246tnt)

Content

Interesting I'm getting quite a few `Error while reading cell "tt_gf_wrapper" (byte position 137203656): Warning: cell "Metal1_fill_cell" placed on top of   itself.  Ignoring the extra one.` during the pre-check, maybe something's wrong somewhere in fill generation ?
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message-1441793003474653365

2025-11-22T14:10:39.247+00:00 — Leo Moser (mole99) (@mole99)

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You can ignore those for now. From what Tim had looked into it, these are most likely real overlapping cells generated by KLayout during filler generation.
I still need to prepare a reproducible for Matthias.

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message-1441802322689654785

2025-11-22T14:47:41.121+00:00 — Leo Moser (mole99) (@mole99)

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Hi @Noritsuna Imamura, with which error does KLayout crash?
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message-1441802821115707453

2025-11-22T14:49:39.955+00:00 — Noritsuna Imamura (@noritsunaimamura)

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It's like this.

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message-1441805192302428283

2025-11-22T14:59:05.29+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Could you please open an issue in the [precheck repo](https://github.com/wafer-space/gf180mcu-precheck) with all the details and a link to the GDS? Unfortunately, I cannot look into it right now, but I would like to try and see if it crashes on my end as well.

You should be able find the full KLayout log in the run directory.

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message-1441806069876920382

2025-11-22T15:02:34.52+00:00 — tnt (@246tnt)

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It worries me a bit that 30 min into the execution of the klayout drc step, it hasn't even started with the "Executing rule XXX" phase of the check 🤔
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message-1441840716744622081

2025-11-22T17:20:14.977+00:00 — Tholin (@tholin)

Content

Is there a way for me to run the KLayout DRC checks on a GDSII file without running the full chip_top flow? I just want to know if my DACs still have DRC errors without waiting 4+ hours for DRC to run on the full chip.
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message-1441841361669197995

2025-11-22T17:22:48.739+00:00 — tnt (@246tnt)

Content

`klayout -b -zz -r ${PDK_ROOT}/gf180mcuD/libs.tech/klayout/tech/drc/gf180mcu.drc -rd input=your.gds -rd report=drc.klayout.lyrdb -rd feol=True -rd beol=True -rd dummy=True -rd offgrid=True -rd conn_drc=True -rd wedge=True -rd run_mode=deep -rd thr=16`
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message-1441841588560072745

2025-11-22T17:23:42.834+00:00 — tnt (@246tnt)

Content

That's the command run by the pre-check.
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message-1441843380903477339

2025-11-22T17:30:50.162+00:00 — Tholin (@tholin)

Content

Its so annoying to me that I can spend days putting something together in magic until its DRC clean, and then KLayout comes in "Actshually, there is 107 DRC errors"

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message-1441845685186986137

2025-11-22T17:39:59.546+00:00 — tnt (@246tnt)

Content

I think that's pretty much the deal of being on this first run is that you're beta testing stuff ...
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message-1441846563751071775

2025-11-22T17:43:29.012+00:00 — tnt (@246tnt)

Content

Although I'm looking at some of the error in KLayout and ... they might be false positive.

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message-1441846910372810936

2025-11-22T17:44:51.653+00:00 — Tholin (@tholin)

Content

I have tons of DRC errors for this. So uhm. Is it too long? Too short? What is the limit?

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message-1441847062261141656

2025-11-22T17:45:27.866+00:00 — Tholin (@tholin)

Content

Am I about to have to dive into some source code just to know what this is about?
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message-1441847302061949150

2025-11-22T17:46:25.039+00:00 — Tholin (@tholin)

Content

No errors in magic

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message-1441847482647707769

2025-11-22T17:47:08.094+00:00 — tnt (@246tnt)

Content

Yes, looking at that now. I think there is a missing marker layer.

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message-1441847606459240660

2025-11-22T17:47:37.613+00:00 — tnt (@246tnt)

Content

5V and 6V transistors have no difference except the channel length.
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message-1441847745332903996

2025-11-22T17:48:10.723+00:00 — Tholin (@tholin)

Content

What is the marker layer?
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message-1441847745433436355

2025-11-22T17:48:10.747+00:00 — tnt (@246tnt)

Content

And there is a marker layer (purely informational, doesn't mean anything for manufacturing) to tell klayout that a given transistor is meant to be 5V and not 6V.
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message-1441847863121543221

2025-11-22T17:48:38.806+00:00 — tnt (@246tnt)

Content

v5_xtor
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message-1441848247613128706

2025-11-22T17:50:10.476+00:00 — tnt (@246tnt)

Content

112/1
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message-1441848310460842064

2025-11-22T17:50:25.46+00:00 — Tholin (@tholin)

Content

`string MASKHINTS_V5_XTOR` does not have an effect. Will actually have to draw this in KLayout.
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message-1441848509241233549

2025-11-22T17:51:12.853+00:00 — tnt (@246tnt)

Content

Yeah, MASKHINTS only works if support for maskhints for that particular layer is in the tech file.
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message-1441848622697418935

2025-11-22T17:51:39.903+00:00 — tnt (@246tnt)

Content

@Tim Edwards it seems `magic` isn't creating that layer at all, I see no support for writing it in the tech file ?
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message-1441848697204899972

2025-11-22T17:51:57.667+00:00 — Tholin (@tholin)

Content

But also, these are supposed to be 6V devices
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message-1441848829505699860

2025-11-22T17:52:29.21+00:00 — Tholin (@tholin)

Content

But also, magic extracts them as 5V?
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message-1441848942366036059

2025-11-22T17:52:56.118+00:00 — Tholin (@tholin)

Content

There is weird things going on here
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message-1441850470187536434

2025-11-22T17:59:00.379+00:00 — Tholin (@tholin)

Content

Oh no, the transistors are indeed too small for 6V devices - and magic doesn’t see a problem with that.
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message-1441850522976915547

2025-11-22T17:59:12.965+00:00 — Tholin (@tholin)

Content

In other words, I’d like to report a bug...
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message-1441852922995675247

2025-11-22T18:08:45.174+00:00 — tnt (@246tnt)

Content

I'm guessing the `mv` devices (which are the ones used in your design) are meant to be the 5V one and the `hv` would be the 6V ones.
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message-1441853249891074148

2025-11-22T18:10:03.112+00:00 — tnt (@246tnt)

Content

Ah no, I think magic doesn't differentiate between 5V and 6V devices at all.
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message-1441853347463172209

2025-11-22T18:10:26.375+00:00 — tnt (@246tnt)

Content

both are `mvnfet` / `mvpfet` and it's just whatever length you use that will dictate which one it is ...
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message-1441855117111591029

2025-11-22T18:17:28.292+00:00 — Tholin (@tholin)

Content

hv is 10V
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message-1441855383793831946

2025-11-22T18:18:31.874+00:00 — Tholin (@tholin)

Content

GF180mcu has LV, MV 5V, MV 6V, Native Vt, HV LDMOS
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message-1441855468631883836

2025-11-22T18:18:52.101+00:00 — Tholin (@tholin)

Content

Which are 3.3V, 5V, 6V, 6V and 10V respectively.
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message-1441855945272463541

2025-11-22T18:20:45.741+00:00 — Tholin (@tholin)

Content

Here is another DRC error that I’m seeing a lot of in KLayout but that isn’t represented in magic.

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message-1441855963434057829

2025-11-22T18:20:50.071+00:00 — Tholin (@tholin)

Content

Even though it totally could be.
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message-1441857146110087238

2025-11-22T18:25:32.043+00:00 — tnt (@246tnt)

Content

I think there are also drc not checked by klayout because anything wider than 30u must be slitted and it didn't spot that.
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message-1441861413160095807

2025-11-22T18:42:29.387+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) I think the KLayout deck has issues.
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message-1441861490931011734

2025-11-22T18:42:47.929+00:00 — tnt (@246tnt)

Content

"M3.2b : Space to wide Metal3 (length & width > 10um) : 0.3µm"

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message-1441861616063742152

2025-11-22T18:43:17.763+00:00 — tnt (@246tnt)

Content

That's a 0.28u trace ... hardly "wide Metal3".

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message-1441866121195163861

2025-11-22T19:01:11.87+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tholin :  Sorry, I was not following this conversation until Sylvain flagged me.
I keep trying to remind people that the magic DRC deck for GF180MCU was designed in a hurry for what was a digital-only tapeout from Efabless.  I made a "good first pass" at the analog rules and layers but there were no analog designs to validate it with.  I have made some corrections since then, but it is more or less in the same state.  I suppose the same goes for the klayout deck---No real validation in practice.
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message-1441868660208701582

2025-11-22T19:11:17.218+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tholin :  I found the GF handling of "5V" devices to be awkward and looked for some method to be consistent.  It has never seemed reasonable to me that the same device can be either "5V" or "6V", and requires a marker layer to specify the _intent_ of it.  But mostly the issue of the way it is currently implemented in magic comes from early on struggling with what was _meant_ by a 5V or 6V transistor, along with largely unreadable documentation trying (badly) to explain it.  There were no 5V devices in the device model files originally.  I added those to the model files recently.  I could certainly redo the magic tech file to separate the 5V and 6V transistor types (now that there is a device model for each of them) and use the V5_XTOR ("FET5VDEF" in the magic techfile) to distinguish them (and apply the device length rules separately for each of them).
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message-1441869215614369853

2025-11-22T19:13:29.637+00:00 — tnt (@246tnt)

Content

IMHO it's fine to only have `mv` to represent 5V/6V , but the `V5_XTOR` layer still need to be generated if length is too small to be 6V to comply with the DRC requirement ...  I'm not sure if that's something doable in the magic tech file ?
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message-1441869284392435864

2025-11-22T19:13:46.035+00:00 — Tim Edwards (@rtimothyedwards_19428)

Reply/reference

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Content

So it's not so much a bug as an implementation decision.  Given that (at the time I implemented it) there was only one device model, I just had magic extract that one device model and discarded the information from the V5_XTOR mask.  Either way, it's the same device, same model (my 5V model is just a copy of the 6V model, with a restriction on device length applied to the 6V model).
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message-1441869633022853200

2025-11-22T19:15:09.155+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@tnt :  It can be done.  I assume the purpose is to have magic-generated GDS pass DRC in klayout?
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message-1441869809917755453

2025-11-22T19:15:51.33+00:00 — tnt (@246tnt)

Content

Yes. But also potentially any DRC GF themselves are running since this is in the design manual.
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message-1441869864212893887

2025-11-22T19:16:04.275+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

But I think that just implementing, say, "mvpfet" = 5V pfet and "hvpfet" = 6V pfet would be more consistent with the PDK overall.
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message-1441870016361271500

2025-11-22T19:16:40.55+00:00 — tnt (@246tnt)

Content

Sure, I have no strong opinion on that.
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message-1441870158426800349

2025-11-22T19:17:14.421+00:00 — tnt (@246tnt)

Content

The 10V one are `ld` if I read the tech file correctly.
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message-1441874492967092356

2025-11-22T19:34:27.856+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Are there any published rules for V5_XTOR?  I can't find any in the open PDK documentation.  In the vendor libraries, it appears to cover entire cells, although I would assume it is only meaningful over the gate of the device.
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message-1441878065776169080

2025-11-22T19:48:39.68+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tholin :  The magic tech file _does_ implement rule V1.3d;  where do you see it not flagging the rule?  (Note that the DRC documentation has no rule"V1.3d", only "V1.3".  The "d" seems to have been invented by Mabrains when they make the klayout DRC deck.)
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message-1441878313898479748

2025-11-22T19:49:38.837+00:00 — tnt (@246tnt)

Content

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html
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message-1441878385478598778

2025-11-22T19:49:55.903+00:00 — tnt (@246tnt)

Content

AFAICT it's just the gate over comp that needs to be covered.
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message-1441878911112974346

2025-11-22T19:52:01.224+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@tnt : Thanks, I missed PL.11.  But PL.12 suggests that the diffusion as well as the gate must be covered.
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message-1441879301623386236

2025-11-22T19:53:34.329+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Rule PL.12 might be intended to prevent mixing 5V and 6V devices in the same circuit.
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message-1441879307382161440

2025-11-22T19:53:35.702+00:00 — tnt (@246tnt)

Content

At least the klayout DRC only checks the gate.
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message-1441879378484133948

2025-11-22T19:53:52.654+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

But GF might flag PL.12.
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message-1441879984317661277

2025-11-22T19:56:17.096+00:00 — tnt (@246tnt)

Content

Yes. Without exactly a drawing for what PL.12 means, I'm not sure tbh.
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message-1441880247715758160

2025-11-22T19:57:19.895+00:00 — tnt (@246tnt)

Content

I like also how there is a drawing for PL.19 but then no PL.19 rule 😅
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message-1441880397335101626

2025-11-22T19:57:55.567+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

I'll start counting the issues in the rules and illustrations, and get back to you next week.

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message-1441881926397984999

2025-11-22T20:04:00.124+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

It occurs to me that there must (?) also be "cap_nmos_05v0", "cap_pmos_05v0", "cap_nmos_05v0_b", and "cap_pmos_05v0_b" devices, but the devices themselves are just modeled as ideal capacitors (?!) and the models have no restriction on length and width.  Also, moscap-connected transistors in the SRAM are just transistors in the netlist.  Maybe the moscap device should just be quietly removed from the PDK. . .
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message-1441887955172987030

2025-11-22T20:27:57.496+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@tnt :  Okay, I have reworked the GF tech file for magic, and pushed the change.  There is also a pending commit to add the 3.3V SRAM library to the open_pdks installation of GF180MCU, so it will all be mirrored to github by tomorrow.

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message-1441888106092695653

2025-11-22T20:28:33.478+00:00 — tnt (@246tnt)

Content

Oh wow, that was fast 😅
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message-1441888119971512362

2025-11-22T20:28:36.787+00:00 — tnt (@246tnt)

Content

Thanks !
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message-1441888604631863320

2025-11-22T20:30:32.339+00:00 — LukeW (@luke_w)

Content

Is anyone else using clock gates (ICGs) in their designs? I'm getting ~2ns SRAM address hold violations with CPU on a gated clock and SRAM on an ungated version of the same clock. I saw TritonCTS had a `-balance_levels` switch (off by default, enabled by `CTS_BALANCE_LEVELS: True`), but it didn't seem to help with overall clock skew:

> -balance_levels Attempt to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter). The default value is False, and the allowed values are bool.
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message-1441889551462305905

2025-11-22T20:34:18.081+00:00 — LukeW (@luke_w)

Content

Related note: based on a tip in the Caravel report I found I could reduce overall clock skew by about 40% (2.8 -> 1.7 ns in post-CTS STA) by forcing Triton to always use the largest available clock buffer. Is there any reason not to make this the default? If you're tight on timing then it may even save area overall as you should need fewer fixups and resizes

```
# Force use of chonky bois to reduce clock skew (default list is 2, 4, 8)
CTS_CLK_BUFFERS:
  - "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16"
```
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message-1441899103134023742

2025-11-22T21:12:15.377+00:00 — LukeW (@luke_w)

Reply/reference

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Content

Actually there is something suspicious in my CTS report:

```
Total number of Clock Roots: 6.
```

I have four defined clocks with two gates on one of those clocks. If I rebuild with the ICG cells removed, I get

```
Total number of Clock Roots: 4.
```
Is Triton treating each gate as a new root? Normally ICGs are just buffers for CTS purposes, and you'd explicitly define a root if you wanted a root
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message-1441899248940748922

2025-11-22T21:12:50.14+00:00 — BreakingTaps (@polyfractal)

Content

re: DRC, I assumed these were checks that GF provided, but I guess they are "implemented" based on written rules that GF publishes? What happens if we submit a design that validates fine but doesn't meet GF's internal checks?
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message-1441899333422419969

2025-11-22T21:13:10.282+00:00 — BreakingTaps (@polyfractal)

Content

or do they just YOLO it and you get back a bad wafer?
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message-1441899457011515402

2025-11-22T21:13:39.748+00:00 — tnt (@246tnt)

Content

GF definitely didn't provide the decks for KLayout and Magic 😅
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message-1441899602952458512

2025-11-22T21:14:14.543+00:00 — tnt (@246tnt)

Content

If it's the same as for Sky130, the fab runs their own deck and comes backs with a list of violations that need fixing.
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message-1441899950345551924

2025-11-22T21:15:37.368+00:00 — tnt (@246tnt)

Content

They usually only bother reporting the MR ( Manufacturing Rule ), i.e. the rules that would actually prevent manufacturing the thing at all.  There are also a bunch of rules that are not MR. i.e. they would affect the performance or function, but are not manufacturing risk, so they don't care so much, it's sort of your problem.
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message-1441900452584362145

2025-11-22T21:17:37.111+00:00 — BreakingTaps (@polyfractal)

Content

👍  makes sense, thanks
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message-1441957360242262218

2025-11-23T01:03:44.954+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Actually I don't think GF had any concept of "MR" rules (or rather, no _documented_ "MR" rule set);  we (Efabless) went through the usual iteration of them sending us a document highlighting all the errors, and coming to an agreement on which rules to waive and which rules to pass back to the user to fix.  Because the two tapeouts were all-digital, we didn't have any user project errors that I recall.  The errors were things in the GF IP (like the I/O cells) which were being flagged by GF's own DRC deck;  none of which would meet the definition of an "MR" rule.

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message-1442116601007837275

2025-11-23T11:36:30.911+00:00 — RebelMike (@rebelmike)

Reply/reference

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Yes, the default is to find roots automatically. In OpenLane 2 there didn’t seem to be a way to explicitly specify roots, I don’t know if things have improved since then.

If the gated clock only feeds a small number of cells, I believe you can avoid getting a full clock tree built for it by explicitly instantiating a buffer after the gate, which should reduce the skew.
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message-1442131010706870343

2025-11-23T12:33:46.451+00:00 — urish

Reply/reference

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Started a thread.
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message-1442141559096086690

2025-11-23T13:15:41.383+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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That's right. From the first round of DRC with GF, it seems the whole rule deck is checked, including recommended rules.
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message-1442141808594391114

2025-11-23T13:16:40.868+00:00 — tnt (@246tnt)

Content

Do they allow to waive the recommended ?
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message-1442142072542072883

2025-11-23T13:17:43.798+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes. But it's going to be a back and forth.
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message-1442142614685093919

2025-11-23T13:19:53.055+00:00 — Leo Moser (mole99) (@mole99)

Content

In other words, if we don't have any DRC violations, we don't need a waiver file, and submitting to the foundry would be faster and less complicated.
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message-1442145087667568642

2025-11-23T13:29:42.66+00:00 — tnt (@246tnt)

Content

Does the klayout deck test for recommended rules ?
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message-1442146344688029900

2025-11-23T13:34:42.357+00:00 — Leo Moser (mole99) (@mole99)

Content

The ones that were violated weren't checked at least. I would need to go through the whole deck to see which are implemented and which are not.
The other way is to go backwards: see which DRC rules are triggered and trying to fix them/add them to the deck.
With actual designs in the reticle we should see a more complete list of DRC violations that are not yet caught by the open source rule decks.
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message-1442297480539537408

2025-11-23T23:35:15.952+00:00 — asc (@asc9742)

Content

Hi all, have people had success running LVS of their designs including the generated padframe? Would like some assurance it is possible before committing to running the long netgen LVS script.
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message-1442298109664297121

2025-11-23T23:37:45.947+00:00 — Tholin (@tholin)

Content

I should do that sometime. I am super worried about VDD/VSS shorts and I believe LVS could detect them.
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message-1442298122863644694

2025-11-23T23:37:49.094+00:00 — Tholin (@tholin)

Content

Though I’m not sure.
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message-1442319744509415546

2025-11-24T01:03:44.096+00:00 — Tholin (@tholin)

Content

First DRC, LVS, STA clean GDSII

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message-1442321213648277574

2025-11-24T01:09:34.366+00:00 — asc (@asc9742)

Content

What flow are you using for LVS? Did you create your own padframe schematic using the io spice files from GF or is there a way to get it from the project template?
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message-1442321393168679023

2025-11-24T01:10:17.167+00:00 — Tholin (@tholin)

Content

The LVS that runs when you do `make librelane`
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message-1442321648199143484

2025-11-24T01:11:17.971+00:00 — asc (@asc9742)

Content

I see.
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message-1442321895440646165

2025-11-24T01:12:16.918+00:00 — bailey (@bailey8889)

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@Tholin Be aware that the librelane LVS abstracts any macros and standard cells.
I can advise on a setup to run full device level LVS along with soft connection and ERC checks.
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message-1442322196713443350

2025-11-24T01:13:28.747+00:00 — Tholin (@tholin)

Content

I’m mostly just interested in checking for VDD/VSS shorts

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message-1442322234709639369

2025-11-24T01:13:37.806+00:00 — Tholin (@tholin)

Content

I accidentally created such shorts before and the flow did not fail.
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message-1442486467761930401

2025-11-24T12:06:14.017+00:00 — LukeW (@luke_w)

Content

Is it possible to get librelane installed as an editable package (like a submodule of my repo) but still use the rest of the `nix-shell` setup? I wanted to look at adding a yosys extraction for mux + flop -> scan flop but librelane is quite hardcoded.
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message-1442487562458370210

2025-11-24T12:10:35.013+00:00 — Tholin (@tholin)

Content

I have a similar complaint. nix-shell currently pulls binaries, but I’d actually like the option to have everything be built from source.
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message-1442490574304186459

2025-11-24T12:22:33.093+00:00 — tnt (@246tnt)

Content

@Tholin you can just remove the cachex entry I think. Then it will be everything from source.
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message-1442494109230305331

2025-11-24T12:36:35.885+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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You can clone the [leo/gf180mcu](https://github.com/librelane/librelane/tree/leo/gf180mcu) branch (same one used for wafer.space). Next, you can make any changes inside the repo and then start LibreLane with `nix-shell`.
That's basically the same step as in: https://librelane.readthedocs.io/en/latest/installation/nix_installation/installation_linux.html#cloning-librelane
You can also apply patches in the in the Nix flake of the template, but it's a bit finicky.
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message-1442494358120042628

2025-11-24T12:37:35.225+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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That's what Nix is for. It builds all the binaries for you. In the case of the wafer.space template we point to a specific branch of LibreLane and the binaries are already cached.
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message-1442499017010315438

2025-11-24T12:56:05.991+00:00 — LukeW (@luke_w)

Reply/reference

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ah, so the shell I get from running `nix-shell` in that branch of the librelane repo is a suitable environment for running the makefile in the project template? If so then got it, thanks
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message-1442499282803490928

2025-11-24T12:57:09.361+00:00 — LukeW (@luke_w)

Content

I probably would move to putting patches in the flake (should just be a few lines to add a flag to pass an extraction file) but I need to develop the patch 🙂

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message-1442501319134023720

2025-11-24T13:05:14.86+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Yes. The project template uses that branch with an override to get a newer magic version. But it should also work with the magic version specified in LibreLane.
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message-1442548921393086585

2025-11-24T16:14:24.123+00:00 — BreakingTaps (@polyfractal)

Content

very silly newbie question: does part of the librelane build process spit out the max frequency the chip is expected to run at? or is there some other way to tell?
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message-1442551933054353670

2025-11-24T16:26:22.159+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, you can find the report in the console or inside `54-openroad-stapostpnr/summary.rpt`.
It contains a list of all corners and whether there are any setup violations for the target frequency. If there is a setup violation at a corner, it means that you will not be able to run the chip at the target frequency at that particular corner (PVT - Process, Voltage and Temperature). Using the setup worst slack, you can calculate the maximum frequency for each corner, which could even be above the target frequency.
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message-1442553993783021871

2025-11-24T16:34:33.475+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

There is also `54-openroad-stapostpnr\nom_tt_025C_3v30\clock.rpt` (and actually for each corner) which tells you `fmax` for that corner.
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message-1442564198751273072

2025-11-24T17:15:06.529+00:00 — BreakingTaps (@polyfractal)

Content

thanks!
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message-1442565671274938452

2025-11-24T17:20:57.606+00:00 — BreakingTaps (@polyfractal)

Content

aha, and found the target frequency in the yaml. cheers!

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message-1442955982153191565

2025-11-25T19:11:54.971+00:00 — LukeW (@luke_w)

Content

Anyone else getting occasional crashes in the detailed router? e.g.

```
 [INFO DRT-0076]   Complete 3000 pins.
Signal 6 received
Stack trace:
 0# handler(int) in /nix/store/g74fz644z0828i5dksxm95mzdb91aq2g-openroad-2025-10-28/bin/.openroad-wrapped
 1# _sigtramp in /usr/lib/system/libsystem_platform.dylib
 2# pthread_kill in /usr/lib/system/libsystem_pthread.dylib
 3# abort in /usr/lib/system/libsystem_c.dylib
 4# malloc_vreport in /usr/lib/system/libsystem_malloc.dylib
 5# malloc_report in /usr/lib/system/libsystem_malloc.dylib
 6# ___BUG_IN_CLIENT_OF_LIBMALLOC_POINTER_BEING_FREED_WAS_NOT_ALLOCATED in /usr/lib/system/libsystem_malloc.dylib
```

Probably  won't have time to file reproducibles til after tapeout but I've made note of my git hashes. I'll just back out the RTL changes for now. Wondering if there is any way to work around it without undoing RTL commits
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message-1442975525332324565

2025-11-25T20:29:34.428+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

Wie hast Du das geschafft?
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message-1442975866119258233

2025-11-25T20:30:55.678+00:00 — LukeW (@luke_w)

Content

Keine Ahnung
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message-1442979829908508672

2025-11-25T20:46:40.719+00:00 — asic destroyer (@logic_destroyer)

Content

MacOSX?
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message-1442982438493225023

2025-11-25T20:57:02.654+00:00 — LukeW (@luke_w)

Content

Yeah it is on MacOS on an M4. The tools do just seem to behave slightly weirdly there, like I also get klayout/magic XORs and I'm not the only person to see that (but fine on Linux)
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message-1442983717814407271

2025-11-25T21:02:07.668+00:00 — asic destroyer (@logic_destroyer)

Content

I don’t have these issues on my Debian or Ubuntu machines. Leo and I have generated over 60 chips in the last 3 weeks.
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message-1442984119155032064

2025-11-25T21:03:43.355+00:00 — LukeW (@luke_w)

Content

yep I'll go back to my Linux box when I need to close DRC. M4 is just faster

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message-1443145256852783170

2025-11-26T07:44:01.576+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Started a thread.
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message-1443201665200033894

2025-11-26T11:28:10.374+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Those CAP violations, I think I am getting them even with vanilla project template, how serious are they?

(So far I couldn’t find a way to get rid of them)
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message-1443201868389023875

2025-11-26T11:28:58.818+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Attachments

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message-1443203373087330374

2025-11-26T11:34:57.566+00:00 — tnt (@246tnt)

Content

If they don't lead to slew rate violation, then, they really don't matter AFAIK.

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message-1443204034826600491

2025-11-26T11:37:35.337+00:00 — Tholin (@tholin)

Content

I heard there is a way to use the 9-track cells now?
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message-1443204106545139832

2025-11-26T11:37:52.436+00:00 — Tholin (@tholin)

Content

I’d like to use them in the multiplexer of my die, since that thing is very performance critical.
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message-1443206274023162032

2025-11-26T11:46:29.203+00:00 — tnt (@246tnt)

Content

You didn't use your cell library ? Or do you want 5V support ?
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message-1443209137184968838

2025-11-26T11:57:51.834+00:00 — Tholin (@tholin)

Content

I need 5V support

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message-1443209655013740604

2025-11-26T11:59:55.294+00:00 — Leo Moser (mole99) (@mole99)

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You should be able to change it via: `STD_CELL_LIBRARY: gf180mcu_fd_sc_mcu9t5v0`. But there have been no changes to the 9t library.
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message-1443211496984281250

2025-11-26T12:07:14.454+00:00 — tnt (@246tnt)

Content

Several people hardened TT projects with 9t without issues.
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message-1443217154102005952

2025-11-26T12:29:43.216+00:00 — LukeW (@luke_w)

Reply/reference

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...so by omission you're saying there *have* been changes to the 7t library? I'm using 9t, do I need those changes?
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message-1443217991759167572

2025-11-26T12:33:02.929+00:00 — LukeW (@luke_w)

Content

The thing I came here to post was: there are several bugs in the vendor RAM model that seem to be simulation related and not functional details of the RAM macro. What's our policy on patching the models? In particular:

* It drops the first access because it fails to correctly initialise `cen_dly` and `cen_flag_dly`; can be fixed by just using `always_comb` to get a time=0 evaluation
* It registers its inputs on a 100 ps delayed version of the clock, making it unsuitable for RTL simulations which just have an NBA delay on the input for the next cycle
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message-1443220644123771084

2025-11-26T12:43:35.302+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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No, there have been no changes to the 7t or 9t library :) I only mentioned this because Tholin wrote: "I heard there is a way to use the 9-track cells **now**?" It already worked before.
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message-1443220771131621408

2025-11-26T12:44:05.583+00:00 — LukeW (@luke_w)

Content

ah. phew, ok
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message-1443220797379317858

2025-11-26T12:44:11.841+00:00 — LukeW (@luke_w)

Content

heart rate returning to normal

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message-1443221214960287877

2025-11-26T12:45:51.4+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

I think it would be great to fix those issues. Preferably in the FOSSi upstream repository.
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message-1443221407780573234

2025-11-26T12:46:37.372+00:00 — Leo Moser (mole99) (@mole99)

Content

Let me just quickly check where open_pdks gets the SRAM sources from, I don't see a FOSSi fork for that.
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message-1443221569580040285

2025-11-26T12:47:15.948+00:00 — LukeW (@luke_w)

Content

Ok sure, added to my list of post-tapeout tasks 🙂 actually I'm curious, is anyone else using the vendor RAM models for RTL sims? I have a behavioural model in my RAM wrapper which I was using until now, but I wanted to run RTL sims with all my manually-instantiated cells enabled so that pulled in the vendor model.

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message-1443221569676513452

2025-11-26T12:47:15.971+00:00 — Leo Moser (mole99) (@mole99)

Content

Aha, it's still the original google repo: https://github.com/RTimothyEdwards/open_pdks/blob/486fb8633c3d95ae475a5ccd68d0066c25919bb5/gf180mcu/Makefile.in#L184
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message-1443221682058956872

2025-11-26T12:47:42.765+00:00 — Tholin (@tholin)

Content

The analog IO pads are still broken and cannot be used with LibreLane, but the fix is easy. Should be possible to upstream.
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message-1443221884899557508

2025-11-26T12:48:31.126+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes, I did use it for some very simple tests.
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message-1443222063077920838

2025-11-26T12:49:13.607+00:00 — LukeW (@luke_w)

Content

Huh. And were you driving the inputs from posedge flops or did you have some behavioural delay and/or negedge stuff going on?
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message-1443223379854491708

2025-11-26T12:54:27.551+00:00 — Leo Moser (mole99) (@mole99)

Content

There are two things going on in my case:

I was testing the FPGA fabric in my chip and to prevent logic loops during configuration I added delays to it.
In the testbench I was waiting two clock cycles before I read the output. I don't remember if the two clock cycles were really necessary, but I was simply happy to get the correct data out again. 😆
I didn't have time to take a closer look since then.
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message-1443223478911242322

2025-11-26T12:54:51.168+00:00 — LukeW (@luke_w)

Content

One of the issues I think I saw (not fully diagnosed) is a read where the address changes on the posedge can give you the data from the address after the posedge
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message-1443223536939307060

2025-11-26T12:55:05.003+00:00 — LukeW (@luke_w)

Content

ah ok if the address is stable over the edge then you won't see issues
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message-1443223719496519782

2025-11-26T12:55:48.528+00:00 — LukeW (@luke_w)

Content

I'm always nervous about patching vendor models but this one does seem quite broken

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message-1443225542290571347

2025-11-26T13:03:03.116+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1443237097543565542

2025-11-26T13:48:58.103+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Project Template Update!

Version [1.1.2](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.1.2) has been tagged. Notable updates include:

- Support for different slot sizes ◻️◽▫️
  - This will likely be an option for future shuttles. For the first shuttle, however, smaller slot sizes are still experimental.
  - You can try this out by setting the `SLOT` variable. See the [README](https://github.com/wafer-space/gf180mcu-project-template?tab=readme-ov-file#choosing-a-different-slot-size) for more information.
  - The CI now also runs for all slot sizes in the upstream repo `wafer-space/gf180mcu-project-template`: https://github.com/wafer-space/gf180mcu-project-template/actions/runs/19697592187
- Better SRAM power connections ⚡
  - `pdn_cfg.tcl`: better connectivity for the SRAM orientations. Please make sure to update your PDN config!
- The PDK has been updated to 1.1.2
  - NP.12 and PP.12 reimplemented
  - Wide metal check fixed

Please update your projects and PDKs.
The latest precheck tag is [1.0.1](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.0.1).

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message-1443237159917191300

2025-11-26T13:49:12.974+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1443239004173762720

2025-11-26T13:56:32.679+00:00 — tnt (@246tnt)

Content

Will quarter slots be 1/4 of the price ? 😅
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message-1443240626698063892

2025-11-26T14:02:59.519+00:00 — Leo Moser (mole99) (@mole99)

Content

I assume the cost of packaging will not go down by much. However, regarding the area, that's for @Tim 'mithro' Ansell to say.
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message-1443284987611844692

2025-11-26T16:59:15.985+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

▫️<-- that would be great for retro stuff (Z80)!
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message-1443285624772886608

2025-11-26T17:01:47.896+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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@Tholin I am hardening with both mcu7t5v0 and mcu9t5v0 in parallel. I need (imho ridiculously high) **0.5** slack margins for HOLD violation in case of 7t, but otherwise both work and pass precheck.
And with @htamas help, we tried both in TT.
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message-1443293927380619275

2025-11-26T17:34:47.392+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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I've been using the vendor verilog as well. I assumed it was correct (looking to be a mistake?) and didn't trust myself to write a correct behavior stub. 😅  I've been getting data in/out but if there was a timing discrepancy I probably chalked it up to my own timing issues and just worked around it in my code
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message-1443328191220420878

2025-11-26T19:50:56.528+00:00 — LukeW (@luke_w)

Reply/reference

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Oh interesting. Do you have the address changing every cycle, on a posedge?
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message-1443330531856089261

2025-11-26T20:00:14.579+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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yep. I'm using it for both instruction memory and generic SRAM. so most (all?) of the tests are probably incrementing the address each cycle to fetch a new instruction. the few tests that check branching also jump around but don't hold the same address over multiple clocks. and the general sram tests are just random accesses as well
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message-1443330766338654440

2025-11-26T20:01:10.484+00:00 — LukeW (@luke_w)

Content

Huhhhh
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message-1443330820960944363

2025-11-26T20:01:23.507+00:00 — BreakingTaps (@polyfractal)

Content

I do have a somewhat mystery clock delay at the beginning of the core bootup, which I attributed to my own jank code. will have to check when I get home but iirc it's two cycles before things start looking correct
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message-1443330884215374017

2025-11-26T20:01:38.588+00:00 — LukeW (@luke_w)

Content

and you're using the RAM model in both gate sim and behavioural RTL sim?
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message-1443331212004298863

2025-11-26T20:02:56.739+00:00 — BreakingTaps (@polyfractal)

Content

emmm, maybe? I'm using Spade HDL (transpiles to verilog), so copied/pasted the macro verilog into the spade setup so it can reference for tests.

Not sure if that's gate sim or behavioural? probably behavioural (cocotb tests)
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message-1443331374739226888

2025-11-26T20:03:35.538+00:00 — LukeW (@luke_w)

Content

yeah, behavioural. Ok thanks, that's useful information, I need to look at my sims a bit more 🙂 definitely some weird stuff going on in that model

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message-1443331528779370526

2025-11-26T20:04:12.264+00:00 — BreakingTaps (@polyfractal)

Content

i'm praying it's not toooooo terribly off, otherwise my chip is totally not gonna work 😅
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message-1443331552951140572

2025-11-26T20:04:18.027+00:00 — LukeW (@luke_w)

Content

gate sim would be a simulation of the synthesised (or post-place etc) netlist instead of your (transpiled) source code
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message-1443331577210736831

2025-11-26T20:04:23.811+00:00 — BreakingTaps (@polyfractal)

Content

aha
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message-1443331627538448649

2025-11-26T20:04:35.81+00:00 — BreakingTaps (@polyfractal)

Content

i should probably figure out how to add some basic tests for that...
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message-1443331921525608508

2025-11-26T20:05:45.902+00:00 — LukeW (@luke_w)

Content

There is already some setup for it in the template's cocotb harness, if you look through where this variable is used in `chip_top_tb.py`:
```
gl = os.getenv("GL", False)
```
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message-1443332027171733717

2025-11-26T20:06:11.09+00:00 — LukeW (@luke_w)

Content

in theory just set that flag. in practice, dragons abound

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message-1443332326305042563

2025-11-26T20:07:22.409+00:00 — BreakingTaps (@polyfractal)

Content

ooh interesting. so theoretically the same cocotb tests would run and should match the behavioural testing pre-synth? will try it out when i get home
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message-1443332522636480717

2025-11-26T20:08:09.218+00:00 — LukeW (@luke_w)

Content

that is the theory. you can have new issues in gate sim like Xs propagating in places they didn't before, but the netlist should be equivalent to your RTL
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message-1443332745089781844

2025-11-26T20:09:02.255+00:00 — BreakingTaps (@polyfractal)

Content

rad! that would make me a lot more confident, especially if I can get it run before the payment deadline 😅
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message-1443332830506516611

2025-11-26T20:09:22.62+00:00 — BreakingTaps (@polyfractal)

Content

cheers for the info!
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message-1443348705880178719

2025-11-26T21:12:27.604+00:00 — BreakingTaps (@polyfractal)

Content

unrelated: i rented a beefy'ish droplet to run the process flow. turns out despite being memory-short on my laptop, fewer/faster cores still win over more slower cores and lots of memory 🙁
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message-1443348884666449972

2025-11-26T21:13:10.23+00:00 — BreakingTaps (@polyfractal)

Content

looks like quite a few steps are single-core operations. alas
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message-1443354310938198206

2025-11-26T21:34:43.954+00:00 — LukeW (@luke_w)

Content

Yep, the fastest machine in my house for running this ASIC flow is my macbook air, annoyingly
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message-1443354679713988729

2025-11-26T21:36:11.877+00:00 — LukeW (@luke_w)

Content

it's worse for some commercial ASIC tools because vendors will apply per-core licensing so the optimal play is to buy the fastest single-core machine you can find

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message-1443371040368754782

2025-11-26T22:41:12.561+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Gaming machine trend to do well

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2025-11-26T23:42:29.867+00:00 — Tim 'mithro' Ansell (@mithro_)

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Good way to justify a new machine 😉
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2025-11-27T01:22:37.119+00:00 — Tim 'mithro' Ansell (@mithro_)

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https://claude.ai/public/artifacts/77fed888-f1c3-431e-a4d1-7ec42a556241

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message-1443425043341246495

2025-11-27T02:15:47.873+00:00 — Trevor Peyton (@trev5514)

Content

"To be compatible with the default breakout PCB, do not change any of the power or ground pads."

Just to make sure I understand correctly, I **can** do the wirebond option if I drop a few pwr/gnd pins, I just have to bring my own PCB?
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message-1443426111756435558

2025-11-27T02:20:02.603+00:00 — Trevor Peyton (@trev5514)

Content

Also, it's been a minute since I used the template, I pulled it in October and have not been following updates. Whoever added the automatic pads is amazing. I remember seeing the pad instances individually laid out on the config.yaml. This is night and day, bravo!
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message-1443525588500353085

2025-11-27T08:55:19.707+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Hi Trevor, if you want to use the CoB bonding option:

1. Do not change the number of pads on any side. This ensures that the bondpad placement stays exactly the same.
2. The VSS pads are shorted on the default breakout PCB. This is why you should not change any of the ground pins.
3. As for whether you can provide your own PCB, @Andrew Wingate should be able to answer that.
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message-1443525653956792434

2025-11-27T08:55:35.313+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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I'm glad you appreciate the updated template. Having all pad instances individually was really too much 😄
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message-1443534341920784414

2025-11-27T09:30:06.685+00:00 — Noritsuna Imamura (@noritsunaimamura)

Content

Our GDS had errors in the zero polygon and wide metal. (The new check item is functioning properly.)
We fixed our GDS, and the new precheck was successful.
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/raw/main/images/precheck_5th_OK.png

- precheck log
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/tree/main/precheck_log/RUN_2025-11-27_10-26-31
- GDS
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/blob/main/gds/ISHI-KAI_WS_RUN1.zip

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message-1443608525418004500

2025-11-27T14:24:53.409+00:00 — LukeW (@luke_w)

Content

I'm getting a couple of hundred klayout DRCs in the standard cell region. They're all `CO.6a (i) Metal1 (< 0.34um) end-of-line overlap contact`. Only other mention I found on this discord was https://discord.com/channels/1361349522684510449/1424739011846471740/1424745841952030860. Any ideas what could be causing that? I'm using 9-track cells if that helps
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message-1443608708444586035

2025-11-27T14:25:37.046+00:00 — LukeW (@luke_w)

Content

I have to confess I've not merged the project template for about a week and a half, so I could be missing some updates
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message-1443609583930183841

2025-11-27T14:29:05.778+00:00 — LukeW (@luke_w)

Content

here is one point it flagged between 33/0 and 34/0 (presumably m1 and contact). 1 box = 20 nm

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message-1443610204095774883

2025-11-27T14:31:33.637+00:00 — tnt (@246tnt)

Content

https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html
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message-1443610258487382088

2025-11-27T14:31:46.605+00:00 — tnt (@246tnt)

Content

I'm trying to understand the rule but ... it's not super clear TBH 😅
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message-1443610319946780704

2025-11-27T14:32:01.258+00:00 — tnt (@246tnt)

Content

Can you zoom out a bit ? Does the line "end" there ?
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message-1443610380311068682

2025-11-27T14:32:15.65+00:00 — Tholin (@tholin)

Content

I know this rule!
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message-1443610396639367211

2025-11-27T14:32:19.543+00:00 — Tholin (@tholin)

Content

It needs some metal right here

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message-1443610674591961199

2025-11-27T14:33:25.812+00:00 — Tholin (@tholin)

Content

There is a separate contact overlap minimum for traces that are exactly the minimum-width and at the end of their line.
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message-1443610680396877997

2025-11-27T14:33:27.196+00:00 — tnt (@246tnt)

Content

Well KLayout seems convinced it does, but I'm not sure it's not an error in the KLayout deck.
For me I see that as falling in the CO.6b case.
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message-1443611309047550012

2025-11-27T14:35:57.078+00:00 — Tholin (@tholin)

Content

When a trace terminates at a contact, then the edge opposite to where the trace extends is the "end of line"

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message-1443611377355718757

2025-11-27T14:36:13.364+00:00 — Tholin (@tholin)

Content

In these cases, additional overlap is needed
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message-1443611429637980260

2025-11-27T14:36:25.829+00:00 — Tholin (@tholin)

Reply/reference

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Content

Which is only partially true for the example shown here, but it seems its still covered by the rule.
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message-1443611589050892439

2025-11-27T14:37:03.836+00:00 — Tholin (@tholin)

Content

For now, I suggest adding the affected standard cells to the exclude lists.
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message-1443611887983136980

2025-11-27T14:38:15.107+00:00 — tnt (@246tnt)

Content

OTOH that cell library was made by GF so when there is doubt, I tend to suspect the KLayout deck more.
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message-1443611902289641522

2025-11-27T14:38:18.518+00:00 — Tholin (@tholin)

Reply/reference

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Actually, the overlap shown here is *tiny.* I doubt this would pass even magic DRC.
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message-1443612131344777339

2025-11-27T14:39:13.129+00:00 — tnt (@246tnt)

Content

CO.6b rule is specially for that case that says if the overlap is less than 40 nm you can "compensate" by having a bigger overlap on the adjacent sides.
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message-1443612311322628267

2025-11-27T14:39:56.039+00:00 — tnt (@246tnt)

Content

But I agree that excluding the affected cell is the easiest thing to do given the time constraints.
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message-1443615538793414868

2025-11-27T14:52:45.528+00:00 — LukeW (@luke_w)

Content

This is a zoom-out of the same region. It doesn't end, just necks down

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message-1443615621832118408

2025-11-27T14:53:05.326+00:00 — LukeW (@luke_w)

Content

actually this looks like it is inside of one of the std cells 🤔
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message-1443615935868043274

2025-11-27T14:54:20.198+00:00 — LukeW (@luke_w)

Content

yeah, it's an icgtp_1
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message-1443616540632158381

2025-11-27T14:56:44.385+00:00 — LukeW (@luke_w)

Content

circled it here. from: https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu9t5v0/cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.html

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message-1443616761533698090

2025-11-27T14:57:37.052+00:00 — LukeW (@luke_w)

Reply/reference

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it's clean with magic DRC (apart from all the overlapping filler cells)
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message-1443618155246391377

2025-11-27T15:03:09.339+00:00 — LukeW (@luke_w)

Content

Yeah I clicked through all 200 CO.6a warnings and they're all the same spot in the `icgtp_1`. I also have four `PL.3a : Space on COMP/Field: 0.24µm` which are just for the four orientations of the same cell. Inclined to waive given it's a foundry cell...
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message-1443618204164427888

2025-11-27T15:03:21.002+00:00 — tnt (@246tnt)

Content

Yes, so for me that's valid and the KLayout DRC is an error.

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message-1443618416631218286

2025-11-27T15:04:11.658+00:00 — LukeW (@luke_w)

Content

The points flagged by PL.3a are across this neck on 30/0 in the `icgtp_1` cell:

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message-1443619017645359347

2025-11-27T15:06:34.951+00:00 — LukeW (@luke_w)

Content

My pattern recognition monkey brain is telling me this is just the two-gate poly on the left-hand side of the cell in my picture
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message-1443619395086585856

2025-11-27T15:08:04.94+00:00 — LukeW (@luke_w)

Content

Oh that's definitely a bug right? It's treating it as multiple polygons and saying they violate spacing

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message-1443619993462767657

2025-11-27T15:10:27.604+00:00 — tnt (@246tnt)

Content

Yeah, that seems weird to me too. How wide is the neck down ?
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message-1443620320601964695

2025-11-27T15:11:45.6+00:00 — LukeW (@luke_w)

Content

in x it's about 0.22 um
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message-1443620468203458581

2025-11-27T15:12:20.791+00:00 — LukeW (@luke_w)

Content

I wonder if it's actually flagging the y distance between the two horizontals, since it's a spacing rule
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message-1443620511086018640

2025-11-27T15:12:31.015+00:00 — LukeW (@luke_w)

Content

(the y distance is around 0.10 um)
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message-1443621055057891530

2025-11-27T15:14:40.708+00:00 — tnt (@246tnt)

Content

I looked at the cell, it all seems good to me.
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message-1443621586870472715

2025-11-27T15:16:47.502+00:00 — LukeW (@luke_w)

Content

nice, thank you
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message-1443621613806289148

2025-11-27T15:16:53.924+00:00 — LukeW (@luke_w)

Content

I think I'm DRC clean then (for now)
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message-1443621664259833998

2025-11-27T15:17:05.953+00:00 — LukeW (@luke_w)

Content

is it possible to waive a specific cell for the klayout checks? (in librelane)
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message-1443622109720088698

2025-11-27T15:18:52.159+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks for the investigation, that makes things easy for me 😁

The easiest path forward is to exclude this cell from synthesis and PnR. Does `_icgtp_2` (if it exists) have the same issues?
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message-1443622421780369548

2025-11-27T15:20:06.56+00:00 — LukeW (@luke_w)

Content

1 and 2 both have the metal neck around the via. 4 does not
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message-1443622527401332817

2025-11-27T15:20:31.742+00:00 — LukeW (@luke_w)

Content

they all seem to have the same kink in the poly
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message-1443622641234870396

2025-11-27T15:20:58.882+00:00 — LukeW (@luke_w)

Content

I'd rather not remove clock gating as it would hurt QoR quite a bit given this cell library lacks DFFEs
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message-1443622857438527691

2025-11-27T15:21:50.429+00:00 — LukeW (@luke_w)

Content

also I think the map file for lighter is buried deep inside librelane or openroad somewhere
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message-1443622997905641606

2025-11-27T15:22:23.919+00:00 — Trevor Peyton (@trev5514)

Content

Has anyone used Slang and gotten the power ports to work? It looks like yosys-slang doesn't support inout ports?
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message-1443623510667821167

2025-11-27T15:24:26.171+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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It does support them, but I think you need to keep the hierarchy, if I recall correctly. See here: https://github.com/mole99/greyhound-ihp/blob/2a2cf3e284a2f2486b71e48212d01458f55e8a0e/config.yaml#L103

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message-1443624167256883221

2025-11-27T15:27:02.714+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Content

Looks like that worked, thanks!

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message-1443624533125894174

2025-11-27T15:28:29.944+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Alright, I absolutely get your point. The problem with waiving is, there is currently no way to ignore a cell in KLayout with the current setup afaik.
In the worst case I can take a manual look at the submission and waive those errors.
Ideally, I would find the time to fix them before the tapeout, unfortunately time is currently rare.
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message-1443624727473160233

2025-11-27T15:29:16.28+00:00 — Leo Moser (mole99) (@mole99)

Content

Could you open an issue detailing both issues (collecting the info from above)?
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message-1443627206575132813

2025-11-27T15:39:07.344+00:00 — LukeW (@luke_w)

Reply/reference

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ok, in that case is there a way to add a `grep -v` or so to the log lint in librelane?
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message-1443627470841712813

2025-11-27T15:40:10.35+00:00 — LukeW (@luke_w)

Content

Separately I get magic DRC errors for overlapping identical filler cells (I think other people have seen this) and this is harmless afaict but prevents me from running `make copy-final`
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message-1443628030055420026

2025-11-27T15:42:23.677+00:00 — asic destroyer (@logic_destroyer)

Content

What causes  icgtp?
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message-1443628085336342741

2025-11-27T15:42:36.857+00:00 — LukeW (@luke_w)

Content

either clock gating inference or manual instantiation (I have both)
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message-1443628227338833921

2025-11-27T15:43:10.713+00:00 — asic destroyer (@logic_destroyer)

Content

hmm
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message-1443628348592095343

2025-11-27T15:43:39.622+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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LibreLane counts the DRC errors in the `.lydrb` that was produced by KLayout. So I don't think that would help. You would need a filter inside of that function.
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message-1443628467257217185

2025-11-27T15:44:07.914+00:00 — LukeW (@luke_w)

Content

how have people waived DRCs on past tapeouts?
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message-1443628615987105873

2025-11-27T15:44:43.374+00:00 — LukeW (@luke_w)

Content

(I'm filing an issue with all of the pictures)

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message-1443628697310724147

2025-11-27T15:45:02.763+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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I don't think that's the issue. The default template should also have these overlap issues, but they should be ignored by LibreLane afaik.
If you get any DRC violations, LibreLane won't create the `final` folder.
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message-1443629149498638377

2025-11-27T15:46:50.573+00:00 — asic destroyer (@logic_destroyer)

Content

These are my primitives for GF180.

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message-1443629555171725392

2025-11-27T15:48:27.293+00:00 — LukeW (@luke_w)

Reply/reference

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ohhh you're right, I actually have some new magic DRCs:

```
Poly overlap of contact < 0.065um (CO.3)
MV N-Diffusion overlap of contact < 0.065um (CO.4)
```
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message-1443631404486496267

2025-11-27T15:55:48.204+00:00 — LukeW (@luke_w)

Content

Here's one of the CO.3 violations: contact poly overlap here in `dffrnq_4`. For scale the thick part of that poly is 500 nm across.

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message-1443633262051328111

2025-11-27T16:03:11.082+00:00 — LukeW (@luke_w)

Reply/reference

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You won't have any clock gating cells  if you don't explicitly enable it. Also you got lucky and your `dffrnq` (flop with async reset) are all drive=1.

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message-1443640375548842055

2025-11-27T16:31:27.072+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Oh, I was using some negedge resetn signals. I’ve removed them now.
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message-1443641048747212921

2025-11-27T16:34:07.575+00:00 — asic destroyer (@logic_destroyer)

Content

stage 06

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message-1443642037915226183

2025-11-27T16:38:03.411+00:00 — LukeW (@luke_w)

Content

I wrote up those DRC issues with some pictures: https://github.com/wafer-space/gf180mcu-project-template/issues/34

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message-1443642401393479902

2025-11-27T16:39:30.071+00:00 — Tholin (@tholin)

Content

Last time, I brought you the neverending LVS run, today, I bring you the Synthesis run from hell:

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message-1443642465016877238

2025-11-27T16:39:45.24+00:00 — LukeW (@luke_w)

Reply/reference

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if you have no async reset in your design then how do you know that resetting your chip puts all the pads into tristate?
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message-1443642603831558205

2025-11-27T16:40:18.336+00:00 — LukeW (@luke_w)

Reply/reference

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is this still a gate ROM? I found ABC was thinking incredibly hard about my 256-byte ROM and it helped to have a pipestage after it
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message-1443642710698229909

2025-11-27T16:40:43.815+00:00 — Tholin (@tholin)

Content

No, this is something different.
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message-1443642774632009870

2025-11-27T16:40:59.058+00:00 — Tholin (@tholin)

Content

What does ABC even stand for?
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message-1443643060436205588

2025-11-27T16:42:07.199+00:00 — tnt (@246tnt)

Content

https://people.eecs.berkeley.edu/~alanmi/abc/
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message-1443643143600996525

2025-11-27T16:42:27.027+00:00 — tnt (@246tnt)

Content

That's a logic mapper used by yosyis.
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message-1443645122389606441

2025-11-27T16:50:18.807+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/IO/gf180mcu_fd_io/tri_state_2.html
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message-1443645864752189521

2025-11-27T16:53:15.8+00:00 — LukeW (@luke_w)

Content

yes that's a tristate buffer?
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message-1443646164988723302

2025-11-27T16:54:27.382+00:00 — LukeW (@luke_w)

Content

is there an async path from your reset input to OE or do you have to clock the chip to stop it from driving its outputs in reset?
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message-1443647166651306116

2025-11-27T16:58:26.197+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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I wrote a DM
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message-1443656126519447594

2025-11-27T17:34:02.396+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Do we need a power-on reset chip?
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message-1443656309869121777

2025-11-27T17:34:46.11+00:00 — LukeW (@luke_w)

Content

A PoR would be nice for future tapeouts. I'm just treating my reset input pad as a PoR.
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message-1443656586173218957

2025-11-27T17:35:51.986+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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sonst macht das alles kein Sinn im Chip
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message-1443657200366129272

2025-11-27T17:38:18.421+00:00 — LukeW (@luke_w)

Content

tristating all of your outputs when held in reset is pretty common and not just a PoR thing. For example it lets you drive other signals into those PCB traces on your board when you're debugging. If you have two chips on a bidirectional bus and they **both** enable their outputs at reset then that creates drive contention. Etc
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message-1443657517786726591

2025-11-27T17:39:34.1+00:00 — LukeW (@luke_w)

Content

on a real board your chip may be held in reset for some time with its clock stopped while power rails are sequenced
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message-1443661713244160184

2025-11-27T17:56:14.375+00:00 — Leo Moser (mole99) (@mole99)

Content

Quick question: instead of a synchronizer, Hirosh could use an async apply and sync remove circuit for the reset. The ouput of this circuit gates the bidir OE and also goes into his circuit. So when you apply the reset, the bidir pads are immediately in a safe state. If you remove the reset, his circuit still works as before. Did I understand this correctly?
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message-1443662116589666507

2025-11-27T17:57:50.54+00:00 — LukeW (@luke_w)

Content

Yep that seems like it would work

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message-1443662187036934217

2025-11-27T17:58:07.336+00:00 — LukeW (@luke_w)

Content

so you have an async reset, which is derived from the reset pad input with an async reset synchroniser

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message-1443662336366874886

2025-11-27T17:58:42.939+00:00 — LukeW (@luke_w)

Content

that resets the pads and also goes into another synchroniser which generates the sync reset used for your digital logic
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message-1443662454369550526

2025-11-27T17:59:11.073+00:00 — LukeW (@luke_w)

Content

something like that would work. I don't think he necessarily needs to make any changes but for a "production" chip it's certainly unusual to drive outputs at start of day
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message-1443662686784196671

2025-11-27T18:00:06.485+00:00 — Leo Moser (mole99) (@mole99)

Content

Why do you need another synchronizer afterwards? The reset signal is then already asynchronously removed.
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message-1443662961943253165

2025-11-27T18:01:12.088+00:00 — LukeW (@luke_w)

Content

depends how your resets are constrained but if you allow async transitions to propagate to a sync reset net then that usually needs a timing exception
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message-1443663017915978019

2025-11-27T18:01:25.433+00:00 — LukeW (@luke_w)

Content

even if it is async apply, sync remove
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message-1443663058517098720

2025-11-27T18:01:35.113+00:00 — Leo Moser (mole99) (@mole99)

Content

I see, thanks!
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message-1443663080428015781

2025-11-27T18:01:40.337+00:00 — Leo Moser (mole99) (@mole99)

Content

And another one: Without a PoR the outputs can still be in an unknown state during power up, right? Holding the reset low doesn't help in that case, as the input pads could be doing anything?
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message-1443663493881401354

2025-11-27T18:03:18.912+00:00 — LukeW (@luke_w)

Content

I don't have a simple answer to that and don't fully understand it myself. There's a question there about how the pads behave during ramp-up, and how the logic cells behave at much less than nominal voltage
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message-1443663649364381866

2025-11-27T18:03:55.982+00:00 — LukeW (@luke_w)

Content

If you have an async path from the reset that disables the pads then any spurious enable during power supply ramp will at least be a short-lived transient
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message-1443663789131173940

2025-11-27T18:04:29.305+00:00 — Leo Moser (mole99) (@mole99)

Content

"It's complicated" is what I thought as well 😄
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message-1443663895418896465

2025-11-27T18:04:54.646+00:00 — LukeW (@luke_w)

Content

my answer as a digital designer is values other than 1 and 0 don't exist and can't hurt me

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message-1443664365671940147

2025-11-27T18:06:46.763+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks for all the tips. It's great to have so many people with different experiences around. There's something for everyone to learn 👏
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message-1443664956473081918

2025-11-27T18:09:07.621+00:00 — LukeW (@luke_w)

Content

yeah this project has been a huge learning curve for me. Thanks for all the help, hope I'm not too annoying with flagging issues
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message-1443665373978169405

2025-11-27T18:10:47.162+00:00 — Leo Moser (mole99) (@mole99)

Content

On the contrary, it is greatly appreciated!
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message-1443665392466792540

2025-11-27T18:10:51.57+00:00 — asic destroyer (@logic_destroyer)

Content

@LukeW thank you
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2025-11-27T18:10:56.242+00:00 — asic destroyer (@logic_destroyer)

Content

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2025-11-27T18:11:07.735+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1443665514076438722

2025-11-27T18:11:20.564+00:00 — asic destroyer (@logic_destroyer)

Content

@Leo Moser (mole99) thank you 🙂
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message-1443665674466496608

2025-11-27T18:11:58.804+00:00 — Leo Moser (mole99) (@mole99)

Content

Now only the synchronizer to the core is missing 👍
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message-1443665742502297712

2025-11-27T18:12:15.025+00:00 — LukeW (@luke_w)

Reply/reference

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Functionally looks good, might look funny in STA though. I would add a false path between the synchroniser output and the pad OE signals
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message-1443666027031433347

2025-11-27T18:13:22.862+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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is inside the soc

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message-1443666998482567289

2025-11-27T18:17:14.474+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

Could I use (* async_reg="true" *) reg [1:0] ff;
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message-1443668604947267625

2025-11-27T18:23:37.485+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Maybe @LukeW Do you have an example to set false path. I think I need it for 2 signals 😉
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message-1443668759922348144

2025-11-27T18:24:14.434+00:00 — asic destroyer (@logic_destroyer)

Content

https://github.com/Wren6991/RISCBoy-180/blob/bb4540d8b1ee8493448395a5b010c80b37377010/librelane/chip_top.sdc
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message-1443669485776146483

2025-11-27T18:27:07.491+00:00 — LukeW (@luke_w)

Content

Most of them come from this wildcard:

```tcl
# Apply RTL-inserted false path constraints (setup/hold only, still constrain slew)
set_false_path -setup -hold -through [get_pins *.magic_falsepath_anchor_u/Z]
```

And then there is an RTL module that inserts magic buffers for the constraints:

https://github.com/Wren6991/RISCBoy-180/blob/bb4540d8b1ee8493448395a5b010c80b37377010/hdl/cells/falsepath_anchor.v
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message-1443670493587701870

2025-11-27T18:31:07.772+00:00 — LukeW (@luke_w)

Content

You can also do it directly in the sdc, something like `set_false_path -setup -hold -from sync_reg_name_here/Q -to *_PAD/OE` but it's a bit cumbersome in this flow because flops don't have predictable names unless you instantiate them yourself

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message-1443675548856619008

2025-11-27T18:51:13.042+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Hi-z

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message-1443676405916369038

2025-11-27T18:54:37.381+00:00 — Leo Moser (mole99) (@mole99)

Content

⚙️ Update to the precheck, version [1.2.1](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.2.1).

- Zero area polygons are checked.
- The layout origin and size are checked depending on the selected slot size, the default is `1x1`.
- Ensure that `PDK_ROOT` and `PDK` are set.

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message-1443676465026826342

2025-11-27T18:54:51.474+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1443677963672486121

2025-11-27T19:00:48.779+00:00 — urish

Content

will try in on ttgf0p2
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message-1443678067854676168

2025-11-27T19:01:13.618+00:00 — urish

Content

https://github.com/TinyTapeout/tinytapeout-gf-0p2/actions/runs/19745733739
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message-1443686305811791924

2025-11-27T19:33:57.7+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

Should I apply the same approach to the FPGA as well?
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message-1443699546122223656

2025-11-27T20:26:34.436+00:00 — LukeW (@luke_w)

Content

You can? FPGAs normally already handle this with their own PoR, before your bitstream ever loads

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message-1443700448853758102

2025-11-27T20:30:09.664+00:00 — asic destroyer (@logic_destroyer)

Content

Yes, that's what I thought, which is why I wanted to ask you again.
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message-1443721711903178772

2025-11-27T21:54:39.17+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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message-1443738894305595545

2025-11-27T23:02:55.774+00:00 — Noritsuna Imamura (@noritsunaimamura)

Content

Update to the precheck, version 1.2.1.
All Green!
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/raw/main/images/precheck_6th_OK.png

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message-1443754111227924531

2025-11-28T00:03:23.771+00:00 — Tholin (@tholin)

Content

Is there a "routing keep-out" layer I can define in KLayout?
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message-1443756483367141486

2025-11-28T00:12:49.333+00:00 — htamas (@h.tamas)

Reply/reference

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You can add a macro with an empty .gds and a .lef file with an `OBS` block containing a rectangle on the right metal layer. I don't think klayout can write .lef files but they are easy to write by hand.
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message-1443757590482784367

2025-11-28T00:17:13.29+00:00 — htamas (@h.tamas)

Content

```
VERSION 5.7 ;
  NOWIREEXTENSIONATPIN ON ;
  DIVIDERCHAR "/" ;
  BUSBITCHARS "[]" ;
MACRO whatever
  CLASS COVER ;
  FOREIGN whatever ;
  ORIGIN 0.000 0.000 ;
  SIZE 100.000 BY 100.000 ;
  OBS
    LAYER Metal2 ;
    RECT 25.000 25.000 75.000 75.000 ;
  END
END whatever
END LIBRARY
```
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message-1443759516805234800

2025-11-28T00:24:52.561+00:00 — bailey (@bailey8889)

Reply/reference

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Content

@Tholin you may already be aware, but I believe you can also specify obstruction areas in the openlane config file.

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message-1443765391191969842

2025-11-28T00:48:13.124+00:00 — Tholin (@tholin)

Content

Sorry, let me rephrase: how can I block *just* routing while leaving the PDN free to do what it wants?

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message-1443768563499274251

2025-11-28T01:00:49.461+00:00 — BreakingTaps (@polyfractal)

Content

is there somewhere in the flow that lists overall stats like total transistors, etc?
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message-1443770456359436389

2025-11-28T01:08:20.754+00:00 — LukeW (@luke_w)

Content

Every step in a run should have a `state_out.json`. Have a look at the `metrics` key in the JSON file, maybe that has what you're looking for?
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message-1443770680272486532

2025-11-28T01:09:14.139+00:00 — LukeW (@luke_w)

Content

```
        "design__instance__count__stdcell": 116005,
        "design__instance__area__stdcell": 2878000,
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        "design__instance__area__class:multi_input_combinational_cell": 912403,
```

Maybe more detail than you wanted 🙂
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message-1443771305504669837

2025-11-28T01:11:43.206+00:00 — LukeW (@luke_w)

Content

Doesn't go down to transistor count unfortunately because the design flow is working with bigger units than transistors. If you wanted a transistor count you could write some script to scrape the transistors from the std cell spice netlist `gf180mcu/gf180mcuD/libs.ref/gf180mcu_fd_sc_mcu7t5v0/spice/gf180mcu_fd_sc_mcu7t5v0.spice` and then multiply by instance counts scraped from your netlist

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message-1443813123088847009

2025-11-28T03:57:53.295+00:00 — Greg (@greg.hashtag.9468)

Content

When using the slang frontend, I'm seeing errors, this line in config.yaml suggested this was a tested option. Maybe I'm the first to try it 😅
```
# Enable plugin for better SystemVerilog support
USE_SLANG: True
```

The error seems to be slang's handling of the VDD/VSS connecting in the netlist it passes through to yosys. Not liking the `inout` type.
```
use_slang
6. Executing SLANG frontend.
src/chip_core.sv:12:17: error: direction 'InOut' on inlined port connection unsupported
inout  wire VDD,
^
src/chip_core.sv:13:17: error: direction 'InOut' on inlined port connection unsupported
inout  wire VSS,
^
src/chip_core.sv:32:39: error: direction 'InOut' on inlined port connection unsupported
inout  wire [NUM_ANALOG_PADS-1:0] analog  // Analog
^
ERROR: Compilation failed
```
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message-1443813616573878335

2025-11-28T03:59:50.951+00:00 — Greg (@greg.hashtag.9468)

Content

I was seeing this with a custom design that's using some systemverilog feature to carry arrays of signals into a module. Which plain yosys does not understand.
But I have confirmed the issue with the vanilla template.
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message-1443815629139218554

2025-11-28T04:07:50.784+00:00 — LukeW (@luke_w)

Reply/reference

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apparently there is a workaround: https://discord.com/channels/1361349522684510449/1423348662318272592/1443623510667821167

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message-1443815951022817393

2025-11-28T04:09:07.527+00:00 — Greg (@greg.hashtag.9468)

Content

Ahh, I should have searched this channel before asking :doh:
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message-1443833390322290851

2025-11-28T05:18:25.38+00:00 — Greg (@greg.hashtag.9468)

Content

New error, but this time I'm pretty sure it's related to my RTL
```
6. Executing SLANG frontend.
ERROR: Assert `count_id(cell->name) == 0' failed in kernel/rtlil.cc:2624.
```
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message-1443843361487192109

2025-11-28T05:58:02.691+00:00 — Trevor Peyton (@trev5514)

Content

Has anyone used Fault with this template? I've never used it before and hoping for an easy integration, any tips would be welcome!
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message-1443860622193328128

2025-11-28T07:06:37.964+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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It is probably more advisable to create a macro with DFT support and integrate this macro into the chip.

The successor to Fault is Difetto: https://github.com/donn/difetto/tree/main
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message-1443867514336444487

2025-11-28T07:34:01.179+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Thanks I'll look into that!
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message-1443867797980581969

2025-11-28T07:35:08.805+00:00 — Trevor Peyton (@trev5514)

Content

Has anyone seen this?

`XOR: missing required input 'mag_gds'`

I get it at the end of a run during the KLayout vs. Magic XOR step.
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message-1443868133369839707

2025-11-28T07:36:28.768+00:00 — tnt (@246tnt)

Content

Did you disable the magic streamout step by any chance ?
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message-1443868826176327690

2025-11-28T07:39:13.946+00:00 — Trevor Peyton (@trev5514)

Content

I pulled a fresh template earlier today and haven't changed the config except for macros and to use SLANG.
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message-1443869816216748122

2025-11-28T07:43:09.99+00:00 — Trevor Peyton (@trev5514)

Content

```tcl
meta:
  version: 3
  flow: Chip
  substituting_steps:
    # Disable KLayout DRC
    #KLayout.DRC: null
    #Checker.KLayoutDRC: null

    # Disable KLayout antenna check
    KLayout.Antenna: null
    Checker.KLayoutAntenna: null

    # Disable KLayout density check
    #KLayout.Density: null
    #Checker.KLayoutDensity: null

    # Save time during development
    # Enable for sign-off
    #OpenROAD.IRDropReport: null
    #Magic.DRC: null
    #Checker.MagicDRC: null
    #KLayout.XOR: null
    #Netgen.LVS: null
    #Checker.LVS: null

PRIMARY_GDSII_STREAMOUT_TOOL: klayout
```

This is some relevant lines from the config.yaml.
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message-1443871184851701832

2025-11-28T07:48:36.298+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Are you using macOS by any chance?
@LukeW Didn't you encounter this error as well?
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message-1443871856770809909

2025-11-28T07:51:16.496+00:00 — tnt (@246tnt)

Content

In the `runs` directory, do you see it running magic stream out ?
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message-1443873516880531597

2025-11-28T07:57:52.297+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Yes, I am on a mac.
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message-1443874236061061174

2025-11-28T08:00:43.763+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Yes... Interestingly the log shows:

Up at the top (not sure if this is important just caught my eye):
`Using NULL graphics device.`

Then at the bottom:
`Cannot open .../librelane/runs/RUN_2025-11-28_00-08-28/73-magic-streamout/chip_top.magic.gds to write GDS-II stream output`

I only have a `chip_top.mag` , no .magic.gds.
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message-1443875723340152863

2025-11-28T08:06:38.358+00:00 — tnt (@246tnt)

Content

NULL is normal, just means it's running in console, no GUI output.
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message-1443875749345103915

2025-11-28T08:06:44.558+00:00 — tnt (@246tnt)

Content

The bottom one is not normal 🙂
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message-1443879406962610287

2025-11-28T08:21:16.602+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Now I remember, you likely reached the limit of max open file handlers!
You can try to increase it with `ulimit`. A proper fix would be for LibreLane to tell magic it doesn't have to lock the files. It's on my list...

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message-1443890411054825483

2025-11-28T09:05:00.182+00:00 — urish

Reply/reference

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Content

Passed!

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message-1443892012133781618

2025-11-28T09:11:21.909+00:00 — Tim 'mithro' Ansell (@mithro_)

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You could probably use the prebuilt docker containers @ https://github.com/wafer-space/gf180mcu-precheck/pkgs/container/gf180mcu-precheck

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message-1443893081392025743

2025-11-28T09:15:36.84+00:00 — bailey (@bailey8889)

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Thanks, I'll check it out.
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message-1443898425018941511

2025-11-28T09:36:50.86+00:00 — Trevor Peyton (@trev5514)

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I maxed my limit, and unfortunately, the error still persists.
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message-1443975049190183024

2025-11-28T14:41:19.486+00:00 — Leo Moser (mole99) (@mole99)

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For now, it might be the best path forward to use a Linux machine to build the complete ASIC.
Unfortunately, there seem to be a number of differences between the Linux and macOS versions of the tools.

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message-1443976415384043725

2025-11-28T14:46:45.212+00:00 — LukeW (@luke_w)

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The issue I had was on Ubuntu 24 LTS. I was getting a zero bytes magic GDS because magic failed to open some of the IP mag files. I found my soft open file limit was 1024 and increasing it with `ulimit -Sn 4096` solved that particular issue.

On MacOS I have a different issue which is that I get actual XORs between KLayout and Magic GDS. I didn't diagnose that, I just stopped using MacOS for now (it also tends to crash in the detailed router).
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message-1443976831928893470

2025-11-28T14:48:24.524+00:00 — tnt (@246tnt)

Content

Possibly related is someone on sky130 had klayout on MacOS hallucinate DRC violations that weren't there ( and don't show up when running klayout on linux ).
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message-1443979042251608196

2025-11-28T14:57:11.506+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, he created an issue: https://github.com/KLayout/klayout/issues/2231
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message-1443981439829020672

2025-11-28T15:06:43.133+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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this'll do, thanks! I assume the cells used in a macro are counted in the instance stdcell count? was trying to get a sense for how many transistors/cells were in my logic but not the sram macros. Not really important, just curious 🙂
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message-1443981680489664653

2025-11-28T15:07:40.511+00:00 — LukeW (@luke_w)

Content

I think the SRAM macros are just counted as whole macros, so they don't appear in the cell instance counts there. They're usually custom layout, not standard cells

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message-1443981799893111049

2025-11-28T15:08:08.979+00:00 — LukeW (@luke_w)

Content

for a rough transistor count estimate just multiply the number of SRAM bits by 6
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message-1443982300978352219

2025-11-28T15:10:08.447+00:00 — BreakingTaps (@polyfractal)

Content

oh awesome, that's perfect. cheers
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message-1444072238776057897

2025-11-28T21:07:31.289+00:00 — asic destroyer (@logic_destroyer)

Content

I’d like to share how GF180mcu KianV ASIC SoC will behave.
It currently runs on an FPGA at 30 MHz, using the same setup we have on wafer.space GF180mcu.
We’ll show a short demo over the serial console; the rest will be  over Telnet, we support spi/ethernet on the chip.
The design will become a tiny Linux network SoC. It already runs XV6 (the MIT teaching Unix) , and μLinux.

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message-1444084312537305159

2025-11-28T21:55:29.898+00:00 — asic destroyer (@logic_destroyer)

Content

Kernel 6.18.0-rc5 riscv32

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message-1444104465777950805

2025-11-28T23:15:34.805+00:00 — Tim 'mithro' Ansell (@mithro_)

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Started a thread.
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message-1444104751691333682

2025-11-28T23:16:42.972+00:00 — Tim 'mithro' Ansell (@mithro_)

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How are you running the precheck on GitHub Actions? Are you using custom runners? I thought that the precheck was too resource heavy for the actions?
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message-1444105413493784667

2025-11-28T23:19:20.758+00:00 — Tim 'mithro' Ansell (@mithro_)

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@carlfk / @asic destroyer - Do you think we could get this running on fpgas.online? I'm guessing the issue is SDRAM controller and https://fpgas.online only having Arty boards with DDR3?

@carlfk - Did I ever end up giving you ulx3s boards or did they all end up in my shipping container? I think I had them as the 3rd priority FPGAs to get onto https://fpgas.online behind the NeTV2 boards?
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message-1444106019964850207

2025-11-28T23:21:45.352+00:00 — carlfk

Reply/reference

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I don't think you gave me or I have any ulx3s

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message-1444106164114817074

2025-11-28T23:22:19.72+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@asic destroyer - I assume you are using ulx3s boards?
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message-1444106262043295885

2025-11-28T23:22:43.068+00:00 — asic destroyer (@logic_destroyer)

Content

Yes, best board on earth 🙂
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message-1444107085305348186

2025-11-28T23:25:59.349+00:00 — asic destroyer (@logic_destroyer)

Content

The FPGA design targets multiple boards.

ASIC  and ULX3s  differs  only in the top-level  module.
The underlying hierarchy remains identical in behavior.
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message-1444107318512844972

2025-11-28T23:26:54.95+00:00 — asic destroyer (@logic_destroyer)

Content

I need only 32MiB SDRAM, I could built top for ARTIX7, ecp5, cyclone, gatemate, ...
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message-1444107591134220413

2025-11-28T23:27:59.948+00:00 — asic destroyer (@logic_destroyer)

Content

@Tim 'mithro' Ansell @GoranMahovlic sells ulx3s on https://www.ebay.de/itm/385678851894?_skw=ulx3s&itmmeta=01KB6CNS3DATNKFMD1BADXY67H&hash=item59cc403f36:g:EbYAAOSwdBpjvJtw&itmprp=enc%3AAQAKAAAA4FkggFvd1GGDu0w3yXCmi1fwK1STpgN5pylpk0DDHI4qgOMwtWMnwHddsMaZ--aq3DW7e3EB8j26DYmkpKx441kiUMlJEmXbwEMNnBW7WPlmo61%2FPLyYGXGuiYPxwJymjdgnkgawKFn0aUZLj6ciIwu7V5bQdM2l3YaVkC3ZJ5Ai6WuIb0GcpLzbmOTZbEXIHHz3VEGlr8alajydtJqUfaQeXUS74VKBttzRMap%2FJEPuQYDY5W%2BG2KqT6kCAC5MM1Z9NmjHYoWPaGpRD9kQiXn3N3r%2B83W3rk92piNCIaEjn%7Ctkp%3ABk9SR-KS18zZZg

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message-1444107892491030721

2025-11-28T23:29:11.797+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I had a video chat with @GoranMahovlic a while back and he offered to help with supplying the ulx3s for https://fpgas.online and wafer.space related stuff

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message-1444108630587871373

2025-11-28T23:32:07.773+00:00 — asic destroyer (@logic_destroyer)

Content

The designs fits into 12f
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message-1444109183686279298

2025-11-28T23:34:19.642+00:00 — asic destroyer (@logic_destroyer)

Content

Do you want ASIC-like behavior, or can I optimize it further? I can add more cache (more ways), more TLBs, and still clock it at 70 MHz on the ECP5.
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message-1444109511450427512

2025-11-28T23:35:37.787+00:00 — asic destroyer (@logic_destroyer)

Content

I support these models

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message-1444109813062697111

2025-11-28T23:36:49.697+00:00 — asic destroyer (@logic_destroyer)

Content

But after the deadline, I’m going to heavily rework this repo so it’s based on the ASIC design. After that, I’ll probably only support ULX3S, iCEPi, and the QMTech Wukong.
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message-1444154016639750337

2025-11-29T02:32:28.651+00:00 — BreakingTaps (@polyfractal)

Content

some dumb pad questions 🙃  :

- we can reconfigure input vs bidirectional pads to suit our design, right? should we leave VDD/VSS alone?
- what's the actual difference between input and bidir? bidir just has extra stuff for sourcing output current or something? (i.e. why would you prefer input over bidir set to input)
- what should I do with unused pins? Set to bidir and bidir_ie = 0 "ignore pad" ?
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message-1444155421823733961

2025-11-29T02:38:03.673+00:00 — LukeW (@luke_w)

Content

* yes, all pads are the same size (the two bidi types, the input-only, and the power pads) so changing pad types does not change the pad coordinates
* VDD/VSS need to be left alone to stay bond-compatible with the COBs; you can move them around if you don't rely on the default COB setup
* One case you'd prefer input is for a global reset input, because you don't want that to spuriously enable its output driver during power-up. Pretty much everything else can be bidi
* Tying off A = IE = OE = 0 is one option, you could also put a small hardcoded UART that prints a rude message
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message-1444156615744946207

2025-11-29T02:42:48.326+00:00 — BreakingTaps (@polyfractal)

Content

awesome, thanks!

And lol at the rude message 😄
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message-1444157296195276870

2025-11-29T02:45:30.558+00:00 — Greg (@greg.hashtag.9468)

Content

Or any message. Spare chips could then be used to advertise "BreakingTaps!\r\n" at 9600bps. 😎

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message-1444212516312973367

2025-11-29T06:24:56.06+00:00 — urish

Reply/reference

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Content

Started a thread.
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message-1444306062080737311

2025-11-29T12:36:39.109+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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We need more silicon artwork!
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message-1444319338088890450

2025-11-29T13:29:24.356+00:00 — Tholin (@tholin)

Content

On my GFMPW-1 multi-project die, giving an invalid project selection code causes the chip pins to become all outputs and go "RTFM!" in binary ASCII

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message-1444339239826227260

2025-11-29T14:48:29.3+00:00 — BreakingTaps (@polyfractal)

Content

Hm, so I added a few 256x8 SRAM macros and it seems unhappy about that now. At step 57 (klayout xor magic) I'm getting a slew of errors which seems to stem from:

```
File /home/ubuntu/gf180mcu-project-template/gf180mcu/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/mag/M3_M24310590878114_256x8m81.mag couldn't be read
Failure to read entire subtree of the cell.

Failed on cell M3_M24310590878114_256x8m81.
I/O error in writing file /home/ubuntu/gf180mcu-project-template/librelane/runs/RUN_2025-11-29_06-44-00/56-magic-streamout/chip_top.magic.gds.
File may be incompletely written.
```
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message-1444340022198272131

2025-11-29T14:51:35.832+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Not positive, but it could possibly be related to:

https://discord.com/channels/1361349522684510449/1423348662318272592/1443879406962610287
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message-1444340277669138593

2025-11-29T14:52:36.741+00:00 — BreakingTaps (@polyfractal)

Content

was just scrolling up to that. will give it a shot!
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message-1444344602906591315

2025-11-29T15:09:47.958+00:00 — BreakingTaps (@polyfractal)

Content

while that's chugging along, what's the general road to fixing PVT violations? I guess the easiest fix is just dropping the clock right? any other config changes/tweaks, or is it mostly down to clock speed + layout + what the code is doing?

Edit: related, how much should I care about the non-nominal PVT corners? if nominal looks good are you generally good to go, or is it pretty important to make sure the other corners are passing too?
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message-1444347436192501920

2025-11-29T15:21:03.466+00:00 — Tholin (@tholin)

Content

Another DRC clean build

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2025-11-29T17:03:47.643+00:00 — Trevor Peyton (@trev5514)

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Content

My understanding is that a hold violation will make the chip non functional, setup timing means it just can't operate at the set clock speed at those corners. I'd say it depends on your chips use case. If you expect the chip to never deviate from normal operation (no power supply issues) or in hot/cold temps then yes you can ignore them if you choose. However those corners cover cases when you say get a power supply surge/drop or the chip get's really hot/cold so they are very important if you don't assume ideal.

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message-1444374757268000839

2025-11-29T17:09:37.318+00:00 — BreakingTaps (@polyfractal)

Content

makes sense! I'll focus on Holds. Probably easiest to just drop the clock rate, doesn't particularly matter anyway for a demo chip.

i just found some docs on OpenLane which look helpful for improving my background knowledge too, and some config values to tweak: https://openlane2.readthedocs.io/en/latest/usage/timing_closure/index.html
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message-1444374956283658352

2025-11-29T17:10:24.767+00:00 — asic destroyer (@logic_destroyer)

Content

Leo taught me that you should eliminate all hold violations in the different voltage domains, and that this is very important. Setup violations are a different matter — you can always deal with those later by adjusting the clock frequency.
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message-1444375663988703355

2025-11-29T17:13:13.497+00:00 — BreakingTaps (@polyfractal)

Content

noted! is there a shortlist of "ways to fix" that I should be aware of (other than what's at that openlane page)? I'm so new to this I don't really know what knobs are available 🫠
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2025-11-29T17:14:25.037+00:00 — asic destroyer (@logic_destroyer)

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You won’t believe it, I’m a newbie too.

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message-1444376199647461376

2025-11-29T17:15:21.208+00:00 — asic destroyer (@logic_destroyer)

Content

but Leo has helped me a lot.
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2025-11-29T17:15:53.2+00:00 — asic destroyer (@logic_destroyer)

Content

And luke
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message-1444387340993822750

2025-11-29T17:59:37.512+00:00 — Tholin (@tholin)

Content

It turns out the C64 SID has two built-in ADCs, which I am trying to replicate in my recreation of it as well. Interestingly, they are implemented using just digital logic cells because they’re not true ADCs and are more like....resistance to digital converters. Each ADC pin requires a capacitor and resistor (usually a potentiometer) connected to it. The chip runs a loop of pulling those pins low for a bit, before tri-state-inputing them and running a timer until they register a logic one.

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2025-11-29T18:00:03.58+00:00 — Tholin (@tholin)

Content

Obviously, this depends on the RC circuit’s time constant.
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message-1444387597253083248

2025-11-29T18:00:38.609+00:00 — Tholin (@tholin)

Content

Fixing the resistor to measure the capacitance also works.
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message-1444387717625675897

2025-11-29T18:01:07.308+00:00 — Tholin (@tholin)

Content

Maybe someone here will find this trick useful.

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message-1444411549853683732

2025-11-29T19:35:49.354+00:00 — ReJ aka Renaldas Zioma (@rzioma)

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That mechanism is also similar readout mechanism for potentiometers in paddle controllers - in Atari Pokey chip and Atari 2600 TIA chip!
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message-1444412997740265572

2025-11-29T19:41:34.557+00:00 — Leo Moser (mole99) (@mole99)

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Please check out the LibreLane docs: https://librelane.readthedocs.io/en/latest/
LibreLane is the successor to OpenLane 2, so the docs should be more up to date :)

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message-1444413233094987876

2025-11-29T19:42:30.67+00:00 — Leo Moser (mole99) (@mole99)

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First thing would be to look at the clock tree in OpenROAD GUI to see if it's reasonably balanced.
If that's the case, then increasing the hold slack margin should mostly resolve the hold violations.
If there are still some remaining, taking a closer look at the timing paths can be helpful.

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message-1444427568815280350

2025-11-29T20:39:28.572+00:00 — BreakingTaps (@polyfractal)

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Content

these docs are great, giving them a thorough read-through now. Project template request as complete newbie: I see the docs are linked for nix install, but I _totally_ missed that it also included more general documentation about the build process. 😅  maybe a subsection heading that's basically "If you have questions about build output read these docs" ?

followup questions: how do i judge if the clock tree is balanced? Just visually, seeing if it branches somewhat-nicely?

ditto to how should I check timing paths?
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message-1444428050035900417

2025-11-29T20:41:23.304+00:00 — BreakingTaps (@polyfractal)

Content

here's where I'm at currently. Pretty substantially bad on the ss cases but I think trending towards ok everywhere else?

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message-1444432848244183101

2025-11-29T21:00:27.286+00:00 — BreakingTaps (@polyfractal)

Content

(hmm I do see that the clock line initially has to wind all the way from bottom left up through a bunch of sram blocks. Can probably re-configure everything so the logic is down in the clock corner)

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message-1444436170066100396

2025-11-29T21:13:39.27+00:00 — Trevor Peyton (@trev5514)

Content

I meant to ask this a while ago but forgot is anyone using cocotb tb with SRAM and passing? I'm using verilator and I get quite a few complaints.

```
gf180mcu_fd_ip_sram__sram512x8m8wm1.v:132:28: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay
  132 |   specparam Tcyc = 55600 : 55600 : 55600;
      |
```

This is a typical error. I got this weeks ago and replaced the entire sram section with those with a:

```verilog
`ifndef VERILATOR
  specparam Tcyc = 55600 : 55600 : 55600;
...
`endif
```

Then outside the specify block I did:

```verilog
`ifdef VERILATOR
  parameter Tcyc = 8183;
  parameter Tckh = 4000;
  parameter Tckl = 4000;
...
`endif
```

Is there a better way? Since now it's failing all github deployments automatically since it's using the repo direct and not my local changes.
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message-1444439967647400008

2025-11-29T21:28:44.684+00:00 — asc (@asc9742)

Content

Is LVS of the foundry io pads able to pass using the netgen LVS script from the project template?
The netgen script we have is causing issues with the pads (see questions channel "Running LVS for padframe")
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message-1444442881359216772

2025-11-29T21:40:19.367+00:00 — Tholin (@tholin)

Content

I know you can pass parameters to verilog modules during instantiation, but is it possible to then use those parameters inside the module to do conditional compilation?
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message-1444442940104773642

2025-11-29T21:40:33.373+00:00 — Tholin (@tholin)

Content

I need to `ifdef exclude some stuff in a module, but only during one specific instantiation of it.
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message-1444448709109616660

2025-11-29T22:03:28.811+00:00 — bailey (@bailey8889)

Reply/reference

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Content

Try `gds flatglob`ing these cells before reading the gds in magic
```
*Bondpad*
*CLAMP_COR*
*FILL*
*METAL_RAIL*
*NMOS_*
*POWER_RAIL_COR*
*_BASE*
*comp018green*
*diode_nd2ps_06v0_*[A-Z]*
*diode_pd2nw_06v0_*[A-Z]*
*mim_*_*[A-Z]*
*moscap_*
*nmos_*_*[A-Z]*
*nmos_4T_metal_stack*
*nmos_clamp_*
*pmos_6p0_esd_*
*power_via*
*ppolyf_u_*[A-Z]*
*top_route*
```
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message-1444464792676073514

2025-11-29T23:07:23.432+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Content

Do you mean like this?

https://stackoverflow.com/questions/52061466/verilog-conditional-hardware-based-on-parameter-value

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    "description": "Is it possible to create conditional hardware in Verilog depending on the value of a parameter? Something like this\n\nmodule test #(\n parameter param = 1\n)(\n  input wire clk\n);\n\nreg[3:0] counter = 0;",
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message-1444485291762122782

2025-11-30T00:28:50.795+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

Dear @LukeW , @Leo Moser (mole99)

The previous code corrupted the entire netlist for the control signals. I checked your riscvboy-180 implementation and saw that your anchor tricky style approach works for synthesis.  Can I  simply declare rst_pad as a false path in sdc?

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message-1444485891614703657

2025-11-30T00:31:13.811+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1444491609482989579

2025-11-30T00:53:57.057+00:00 — RebelMike (@rebelmike)

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Content

Would an `if` inside a `generate` block do what you need?
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message-1444491798742565007

2025-11-30T00:54:42.18+00:00 — Tholin (@tholin)

Content

Yes
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message-1444505785517477938

2025-11-30T01:50:16.887+00:00 — asic destroyer (@logic_destroyer)

Content

During gate-level simulation I found that **CEN has to remain high for one clock cycle**. I had previously hardwired it to 0, but I’ve now combined it with `reset_n`, so the SRAM is operational.

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message-1444505853620256809

2025-11-30T01:50:33.124+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1444505995224158380

2025-11-30T01:51:06.885+00:00 — LukeW (@luke_w)

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I am fairly certain the `cen_fell` thing is a bug in the RAM model where they don't initialise all of their variables
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message-1444506147498496050

2025-11-30T01:51:43.19+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1444506416873214054

2025-11-30T01:52:47.414+00:00 — LukeW (@luke_w)

Reply/reference

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Content

ah maybe I had a separate issue which is the model doesn't accept the first access if you start up with CSn high
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message-1444506515883954306

2025-11-30T01:53:11.02+00:00 — LukeW (@luke_w)

Content

I haven't looked at the schematic for the SRAM but that would be a super weird requirement 🤔

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message-1444506618460110878

2025-11-30T01:53:35.476+00:00 — asic destroyer (@logic_destroyer)

Content

My caches are working!

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message-1444506632007585792

2025-11-30T01:53:38.706+00:00 — LukeW (@luke_w)

Reply/reference

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Content

yes IMO it's ok to falsepath the reset pad input since it's synchronised before use

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message-1444506885465047124

2025-11-30T01:54:39.135+00:00 — asic destroyer (@logic_destroyer)

Content

I was able to boot from flash, copy the code into SDRAM, and execute it via micron sdram model.
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message-1444506933393490032

2025-11-30T01:54:50.562+00:00 — LukeW (@luke_w)

Content

nice

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message-1444507126469886022

2025-11-30T01:55:36.595+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1444507193654382824

2025-11-30T01:55:52.613+00:00 — LukeW (@luke_w)

Content

@Leo Moser (mole99) those 0.5 x 0.5 slots are so cute 🥺  think they would be a great gate-golf target

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message-1444507193822150696

2025-11-30T01:55:52.653+00:00 — asic destroyer (@logic_destroyer)

Content

I got the model from you Luke 2022 🙂

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message-1444507407165161624

2025-11-30T01:56:43.518+00:00 — LukeW (@luke_w)

Content

how did we choose the number of VDD/VSS pins? seems to  have like 75% the IOs of the 1x1 but < 50% the power and ground pins

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message-1444508779319132332

2025-11-30T02:02:10.665+00:00 — Trevor Peyton (@trev5514)

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FYI for my application, SRAM should remain on once started, I added a small prime latch where on reset, it toggles the CEN for a cycle to ensure it's always started.
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message-1444509157792153814

2025-11-30T02:03:40.9+00:00 — asic destroyer (@logic_destroyer)

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that was my fix!

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message-1444516403263836284

2025-11-30T02:32:28.355+00:00 — asic destroyer (@logic_destroyer)

Content

Does anyone have a simple SD card Verilog model for iverilog? I only need SPI support, then I could try booting xv6 Unix.

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message-1444592512705761281

2025-11-30T07:34:54.26+00:00 — Greg (@greg.hashtag.9468)

Content

Looks like it's coming together. This is an updated serv soc design.
28 cores, with each processor making use of the SRAM block for registerfile/program text and ram.
A small FSM pre-loads each cores memory from SPI flash. (similar to an FPGAs bitstream)
The cores are connected via a cross-bar to peripherals. One of which enables core to core communication, via queues or flags.

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message-1444593348244541545

2025-11-30T07:38:13.468+00:00 — Greg (@greg.hashtag.9468)

Content

Given the logic density, I think I could fit 32 cores in there... But didn't want to hit a wall with routing.
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message-1444593977549651989

2025-11-30T07:40:43.506+00:00 — Greg (@greg.hashtag.9468)

Content

A cross-bar between every core isn't a very scalable solution. But gives a lot of flexibility to the application
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message-1444610132909752462

2025-11-30T08:44:55.244+00:00 — asic destroyer (@logic_destroyer)

Content

CoreScore style @Greg ?
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message-1444610376342966359

2025-11-30T08:45:53.283+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1444610577375694871

2025-11-30T08:46:41.213+00:00 — Greg (@greg.hashtag.9468)

Content

I did take a look at corescore. We can probably make this the highest ranking serv ASIC on that list 😉

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message-1444613444996173884

2025-11-30T08:58:04.907+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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@Leo Moser (mole99)
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message-1444645005519098027

2025-11-30T11:03:29.522+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Thanks Hirosh, I did see the question, I just haven't had time to reply yet :)

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message-1444645136071131269

2025-11-30T11:04:00.648+00:00 — Leo Moser (mole99) (@mole99)

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Content

The default pinout of the 1x1 slot is based on the TT chip: https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?gid=0#gid=0
A number of the VDD/VSS pads will be used for the analog power domain in the future.

In addition, the core are of the 0p5x0p5 chip is less than a quarter of that of the 1x1 chip. That's why I reduced the number of power/ground pads considerably.
It may turn out that this is not enough to support the number of I/Os at high speeds, so we might change that again for run 2.

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message-1444676303725920267

2025-11-30T13:07:51.596+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Z80 in a **quarter** slot. I think it is cute!

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message-1444677015532863601

2025-11-30T13:10:41.304+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Leo Moser (mole99) quarter slot works! 🙂
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message-1444682168289726667

2025-11-30T13:31:09.817+00:00 — RebelMike (@rebelmike)

Content

I noticed the project template SDC file has `set_input_delay -min 0 -clock $clocks $clk_core_input_ports` which sets the hold time on the inputs to zero.  I think that's may be why you've had to turn up the hold slack margin, because it means a bunch of buffering is required on the inputs which is a bit difficult for the flow to get right.

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message-1444690601001095249

2025-11-30T14:04:40.332+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Make sure to also check that the actual timing of the clock tree in the "Clock Tree Viewer".

This shows the example template where the design is quite sparse so there's a lot of routing between the clock buffers and after SPEF extraction the tree isn't as balanced as it should be (that's why I had to increase the hold margin).

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message-1444691372127948871

2025-11-30T14:07:44.183+00:00 — Leo Moser (mole99) (@mole99)

Content

For a detailed report on the timing paths, take a look at `librelane/runs/<timestamp>/54-openroad-stapostpnr/<corner>/` and open `min.rpt`/`max.rpt` for hold/setup checks.
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message-1444692219859701922

2025-11-30T14:11:06.298+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Have you implemented PIO and SIO?
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message-1444693940602404925

2025-11-30T14:17:56.555+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Well, I looked at a bunch of Z80 computers from back in the day… and I couldn’t find almost a single one that would use Zilog’s PIO/SIO.

So I am actually thinking to focus on ZX Spectrum like machine repairs and put ULA (graphics) and AY (audio) instead.

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message-1444694125717884948

2025-11-30T14:18:40.69+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

If I am missing some, let me know plz!
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message-1444694178218119261

2025-11-30T14:18:53.207+00:00 — asic destroyer (@logic_destroyer)

Content

I have no idea 🙂
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message-1444694445470781530

2025-11-30T14:19:56.925+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Plus 16KB of RAM if I go full slot.

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message-1444701239190487153

2025-11-30T14:46:56.674+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

aha, didn't know that little widget existed in the gui, cheers! Didn't see the timing report tab either. looking through the violators now, looks like my ALU is popping up in the list which is interesting. didn't think I had anything particularly expensive in there but will give examine it closer.

thanks for all th ehelp!

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message-1444714101807775874

2025-11-30T15:38:03.361+00:00 — Tholin (@tholin)

Content

Just one more design. I can still fit more. I can do just one more design!

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message-1444739232311546016

2025-11-30T17:17:54.94+00:00 — Tholin (@tholin)

Content

I think I’m a little behind. I still have not submitted any GDSIIs and let precheck run.
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message-1444739246379241624

2025-11-30T17:17:58.294+00:00 — Tholin (@tholin)

Content

How do I even do this?
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message-1444743372584652900

2025-11-30T17:34:22.058+00:00 — Trevor Peyton (@trev5514)

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Content

You can do it locally:
https://github.com/wafer-space/gf180mcu-precheck

But I believe the test project is where we will end up submitting which just runs that on a server:
https://doc.test-platform.wafer.space

I'd do it locally, mine timed out on the website.

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message-1444815823750562053

2025-11-30T22:22:15.762+00:00 — asic destroyer (@logic_destroyer)

Content

It would be nice to run the SPICE model. I could run it on a remote server and check what it does after a year. How can I run something like that in SPICE?
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message-1444828491215278272

2025-11-30T23:12:35.921+00:00 — Tholin (@tholin)

Content

I tried to use the online platform, but it just keeps cycling between "Queued" and "Starting"
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message-1444847805414903958

2025-12-01T00:29:20.785+00:00 — LukeW (@luke_w)

Content

The `.sdc` in the template has this at the end:

```
if { [info exists ::env(OPENLANE_SDC_IDEAL_CLOCKS)] && $::env(OPENLANE_SDC_IDEAL_CLOCKS) } {
    unset_propagated_clock [all_clocks]
} else {
    set_propagated_clock [all_clocks]
}
```

However I've instrumented this and that variable is never set in any stages, which is probably why I have multi-hundred-ns clock slew times in pre-CTS STA. @Leo Moser (mole99) do you know what's up with that? librelane sets it here: https://github.com/librelane/librelane/blob/774d6e6f221ccf21bd499e9b8ccba4afeffff4fd/librelane/steps/openroad.py#L725-L728

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message-1444849547678322730

2025-12-01T00:36:16.173+00:00 — LukeW (@luke_w)

Content

(context for suddenly caring about pre-CTS STA is I wanted to try enabling the resizer earlier in the flow to help with some stubborn setup paths)
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message-1444859528121417748

2025-12-01T01:15:55.696+00:00 — LukeW (@luke_w)

Content

I have a dumb workaround:

```tcl
set clk_pins [get_pins  -of_objects [get_net -of_objects [get_pins i_chip_core.clkroot_sys_u.magic_clkroot_anchor_u/Z]]]
set clk_loads [llength $clk_pins]
puts "clk_sys has $clk_loads directly connected pins"

if { [expr $clk_loads > 10] } {
    puts "Setting all clocks to ideal!"
    unset_propagated_clock [all_clocks]
} else {
    puts "Setting all clocks to non-ideal"
    set_propagated_clock [all_clocks]
}
```

This prints the right messages in the right phases (ideal until after CTS), but even with `unset_propagated_clock [all_clocks]` my early STAs still have enormous clock rise/fall times. Is this just a me problem or do other people's pre-CTS STAs also have huge setup violations due to clock slew?
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message-1444864017532453016

2025-12-01T01:33:46.055+00:00 — RebelMike (@rebelmike)

Content

I thought that was just how it was pre-CTS. I guess there should be some option to tell STA to ignore the load on the clock pin?
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message-1444864478826074132

2025-12-01T01:35:36.036+00:00 — LukeW (@luke_w)

Content

yeah, that is what the `unset_propagated_clock` is supposed to do:

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message-1444864554528931840

2025-12-01T01:35:54.085+00:00 — LukeW (@luke_w)

Content

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message-1444864832372346992

2025-12-01T01:37:00.328+00:00 — LukeW (@luke_w)

Content

(from OpenSTA docs). Ok so it's not just me, it's other people too 😅 right now there isn't really any usable timing information in the early STA which I imagine is part of the reason the early resizer step has been turned off
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message-1444868068408033364

2025-12-01T01:49:51.859+00:00 — RebelMike (@rebelmike)

Content

Ah no, hold on - I think it is working.  I have massive slew but it's on my rst_n net, not my clock net:
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message-1444868139585372352

2025-12-01T01:50:08.829+00:00 — RebelMike (@rebelmike)

Content

```                      0.150000    0.000000    0.000000   clock clk_PAD (rise edge)
                                  0.000000    0.000000   clock network delay (ideal)
                      0.150000    0.000000    0.000000 ^ i_chip_core.tt.i_peripherals.i_simple_peri16.i_spi_ctrl.rstn_gf180mcu_fd_sc_mcu7t5v0__dffq_1_Q/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
   832    4.638381  110.209221   63.362564   63.362564 ^ i_chip_core.tt.i_peripherals.i_simple_peri16.i_spi_ctrl.rstn_gf180mcu_fd_sc_mcu7t5v0__dffq_1_Q/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                                         i_chip_core.tt.i_peripherals.i_simple_peri16.i_spi_ctrl.rstn (net)
                    110.209221    0.000000   63.362564 ^ i_chip_core.tt.i_peripherals.i_simple_peri19.ay8913.noise_generator.reset_gf180mcu_fd_sc_mcu7t5v0__clkinv_1_ZN/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
   164    0.691456    3.280350   53.123268  116.485832 v i_chip_core.tt.i_peripherals.i_simple_peri19.ay8913.noise_generator.reset_gf180mcu_fd_sc_mcu7t5v0__clkinv_1_ZN/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
                                                         i_chip_core.tt.i_peripherals.i_simple_peri19.ay8913.noise_generator.reset (net)
```

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message-1444868261891280969

2025-12-01T01:50:37.989+00:00 — LukeW (@luke_w)

Content

huhhhh ok, thanks for the datapoint
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message-1444868294543937861

2025-12-01T01:50:45.774+00:00 — RebelMike (@rebelmike)

Content

That's from 12-openroad-staprepnr
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message-1444871960717824060

2025-12-01T02:05:19.858+00:00 — LukeW (@luke_w)

Content

...it's possible this was just me being dumb. There is a whole bunch of other tcl that librelane runs during STA and it might handle ideal clocks there. But yeah I also see the slow unbuffered reset
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message-1444872074471538721

2025-12-01T02:05:46.979+00:00 — LukeW (@luke_w)

Content

normally there is a command like `set_ideal_network` which you can use to do the same thing for resets but I don't think OpenSTA supports it
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message-1444874184940589066

2025-12-01T02:14:10.154+00:00 — RebelMike (@rebelmike)

Content

I'm so used to being extremely area constrained on TT that I completely forgot until now that you can set the synth strategy to trade area for speed!
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message-1444878164995215392

2025-12-01T02:29:59.073+00:00 — LukeW (@luke_w)

Content

Here is an ugly trick to get it to ignore reset timing pre-CTS (relies on the name of a manual flop instances in my reset synchronisers):

```tcl
set main_clk_pin [get_pins i_chip_core.clkroot_sys_u.magic_clkroot_anchor_u/Z]
set rst_pins [get_pins i_chip_core.*sync*flop2/Q]

set clk_pins [get_pins  -of_objects [get_net -of_objects ${main_clk_pin}]]
set clk_loads [llength ${clk_pins}]
puts "clk_sys has ${clk_loads} directly connected pins"

if { [expr $clk_loads > 10] } {
    puts "Setting all clocks to ideal!"
    unset_propagated_clock [all_clocks]
    puts "Case analysing reset nets:"
    foreach pin ${rst_pins} {puts [sta::get_full_name ${pin}]}
    set_case_analysis 1 ${rst_pins}
} else {
    puts "Setting all clocks to non-ideal"
    set_propagated_clock [all_clocks]
    unset_case_analysis ${rst_pins}
}
```

Seems to work for me. Might give better placement as the datapath delays are actually realistic.

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message-1444891060211023965

2025-12-01T03:21:13.532+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

I've been working through the synth strategies and haven't seen any real correlation unfortunately. 🙁  `AREA 3` seems to be working best/fastest for my design so far
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message-1444891789147508808

2025-12-01T03:24:07.324+00:00 — RebelMike (@rebelmike)

Content

Yeah I was hoping it would fix it as I only needed a couple of ns, but it didn’t seem to
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message-1444891956739047485

2025-12-01T03:24:47.281+00:00 — LukeW (@luke_w)

Content

If you add this to your Makefile:

```
librelane-explore: ## Run synthesis exploration
    librelane librelane/config.yaml --pdk ${PDK} --pdk-root ${PDK_ROOT} --manual-pdk --last-run --flow SynthesisExploration
.PHONY: librelane-explore
```

And then run `make librelane-explore` it will try all 9 strategies and tell you which is best (though it's just synthesis timing)

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message-1444891971842867342

2025-12-01T03:24:50.882+00:00 — BreakingTaps (@polyfractal)

Content

likewise 😭  got it down to about 3ns but just can't seem to improve from there. might need to just drop the clock at this point
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message-1444893835363881072

2025-12-01T03:32:15.18+00:00 — BreakingTaps (@polyfractal)

Content

been pretty surprised by timing in general. For a while I assumed reducing density would help the optimizer spread out, insert buffers more easily, etc. but cranking up the density (in addition to more margins) helped a lot
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message-1444894186456486100

2025-12-01T03:33:38.887+00:00 — LukeW (@luke_w)

Content

What's your density set to at the moment?
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message-1444895162051592213

2025-12-01T03:37:31.487+00:00 — BreakingTaps (@polyfractal)

Content

between 45 and 55 is yielding best results so far (still -3ns in some corners though)

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message-1444907814958141521

2025-12-01T04:27:48.175+00:00 — LukeW (@luke_w)

Content

There's a step disabled by default which I found helped a little:

```
RUN_POST_GRT_RESIZER_TIMING: True
```
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message-1444908200024473744

2025-12-01T04:29:19.982+00:00 — LukeW (@luke_w)

Content

from: https://github.com/librelane/librelane/blob/774d6e6f221ccf21bd499e9b8ccba4afeffff4fd/librelane/flows/classic.py#L156-L161

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2025-12-01T04:31:17.862+00:00 — BreakingTaps (@polyfractal)

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ooh, will try that on my next run!
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2025-12-01T04:34:05.44+00:00 — BreakingTaps (@polyfractal)

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if/when I do another shuttle, I think I'll just write a quick optimizer to churn through config options for like a week. beats doing it by hand 😅
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message-1444909930220879943

2025-12-01T04:36:12.493+00:00 — LukeW (@luke_w)

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yeah, I mean it should be possible to do this stuff methodically, but this flow does things in weird places
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message-1444909974814720093

2025-12-01T04:36:23.125+00:00 — LukeW (@luke_w)

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like it doesn't do any gate sizing until after detailed placement
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message-1444910090229518346

2025-12-01T04:36:50.642+00:00 — LukeW (@luke_w)

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but I am also just trying random shit to make my design meet timing at this point

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message-1444910174899933366

2025-12-01T04:37:10.829+00:00 — LukeW (@luke_w)

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I have had one run that I think I could make pass with some manual netlist changes but I don't really want to do that
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message-1444910509181767740

2025-12-01T04:38:30.528+00:00 — BreakingTaps (@polyfractal)

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i'm very nearly read to call it with my best -3ns case, and just slap a big heatsink on it 😄 looked fine in the normal corners, just the hot ones were bad
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message-1444910714404995142

2025-12-01T04:39:19.457+00:00 — BreakingTaps (@polyfractal)

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how would you go about doing this btw? not sure I'd know what to tweak even if I wanted to
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message-1444911061672132700

2025-12-01T04:40:42.252+00:00 — LukeW (@luke_w)

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You can run `librelane` with a `--last-run --from (some pass)` argument to make it restart a run from part way. Since I'm pressed for time I'd probably just edit the netlist with a text editor and re-run from there
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message-1444911155960221697

2025-12-01T04:41:04.732+00:00 — LukeW (@luke_w)

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I just need some gate upsizing on some gates that are consistently on the critical path on my processor
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message-1444911230123905197

2025-12-01T04:41:22.414+00:00 — LukeW (@luke_w)

Content

I think there is a "more proper" way of doing this in LibreLane, by adding an ECO pass
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message-1444911881578872852

2025-12-01T04:43:57.733+00:00 — LukeW (@luke_w)

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At work our synth and pnr flows are just TCL and my understanding is they'll do pretty much the same thing: write a list of ECO scripts applied at a given point in the flow to apply a manual (but repeatable) fix. That's normally for slightly more esoteric stuff though, not just making the gates the right size on the critical path 😅

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message-1444912048357244989

2025-12-01T04:44:37.496+00:00 — BreakingTaps (@polyfractal)

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interesting, thanks! is there a way for librelane to tell you the critical path? Or is that just based on your knowledge of how the processor works?
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message-1444912138987769896

2025-12-01T04:44:59.104+00:00 — LukeW (@luke_w)

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Yeah, just from reading the `max.rpt` from the final STA
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2025-12-01T04:45:07.248+00:00 — BreakingTaps (@polyfractal)

Content

oh gotcha, roger
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message-1444912287742955552

2025-12-01T04:45:34.57+00:00 — LukeW (@luke_w)

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the reports are a bit inscrutable partly because this flow doesn't correctly attribute flops to their original names in the source code
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message-1444912327060099142

2025-12-01T04:45:43.944+00:00 — LukeW (@luke_w)

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but you can usually make educated guesses
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message-1444912538121670677

2025-12-01T04:46:34.265+00:00 — BreakingTaps (@polyfractal)

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yeah it feels like reading tea leaves 🙁  I'm using a transpiled HDL which makes everything even more inscrutable too
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message-1444913133054591107

2025-12-01T04:48:56.108+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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message-1444940704483901593

2025-12-01T06:38:29.649+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

this helped me a bunch btw, thanks! gained me +5ns on setup and now using that to help beat down cap/slew violations 🙂
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message-1444981998782255168

2025-12-01T09:22:34.977+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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The same here... since yesterday.
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message-1444992838365347881

2025-12-01T10:05:39.335+00:00 — urish

Content

Same for me
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message-1445014108750745621

2025-12-01T11:30:10.59+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Leo Moser (mole99) I think including another `yaml` before `config.yaml` **broke** 9t cell support!

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message-1445014670330171574

2025-12-01T11:32:24.481+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

`resloved.json` in the runs folder gets confused

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message-1445014917261557871

2025-12-01T11:33:23.354+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

My quick-and-dirty workaround is to place `STD_CELL_LIBRARY: gf180mcu_fd_sc_mcu9t5v0` in `slot_*.yaml` file instead of `config.yaml`
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message-1445015237064396924

2025-12-01T11:34:39.601+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

But begs a question which other parameters are ignored by the flow, if they are not in the first `yaml` file passed into the librelane 🤷‍♂️
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message-1445017856063574056

2025-12-01T11:45:04.019+00:00 — Leo Moser (mole99) (@mole99)

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Very sorry about that! I think this is either a LibreLane bug, or at least strange behaviour (user config resolved too early). I'll open an issue in the LibreLane repro.
Yes, adding `STD_CELL_LIBRARY` to `slot_*.yaml` instead is a workaround.

I'm suspect that only `STD_CELL_LIBRARY` is affected because it is a special variable that can be set by passing `--scl` to LibreLane. If you see other variables being overwritten, please let me know. However, I think that's unlikely.
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message-1445019037326381129

2025-12-01T11:49:45.654+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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I agree that it is very unlikely!
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message-1445019223171797145

2025-12-01T11:50:29.963+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Here is the issue: https://github.com/librelane/librelane/issues/827

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message-1445026511240298556

2025-12-01T12:19:27.574+00:00 — RebelMike (@rebelmike)

Reply/reference

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Content

You can improve this with `SYNTH_AUTONAME: True`, however that results in very long names so you'll likely have to go up to Magic 8.3.578 or later to avoid LVS errors
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message-1445036134374834176

2025-12-01T12:57:41.908+00:00 — RebelMike (@rebelmike)

Reply/reference

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Thanks, this along with sorting the resets helped a fair bit!
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message-1445072081153822854

2025-12-01T15:20:32.288+00:00 — Tholin (@tholin)

Content

Alright. Finished with the RISC-V core on my multi-project die. Feature set is rv32ima_zicsr_smrnmi
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message-1445072439556964372

2025-12-01T15:21:57.738+00:00 — Tholin (@tholin)

Content

That’s the second-to-last thing on my to-do list
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message-1445072653974241371

2025-12-01T15:22:48.859+00:00 — Tholin (@tholin)

Content

Tomorrow I will do a final code review. Should be pretty relaxed.
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message-1445073818912821359

2025-12-01T15:27:26.602+00:00 — BreakingTaps (@polyfractal)

Content

https://tenor.com/view/community-chaos-chaotic-fire-gif-17636558

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message-1445073824793235701

2025-12-01T15:27:28.004+00:00 — BreakingTaps (@polyfractal)

Content

meanwhile over here
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message-1445075037311995965

2025-12-01T15:32:17.091+00:00 — Tholin (@tholin)

Content

What I have here is actually almost the bare minimum you need to boot mainline Linux
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message-1445075086683144192

2025-12-01T15:32:28.862+00:00 — Tholin (@tholin)

Content

But its missing the interrupt controller.
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message-1445085451378626812

2025-12-01T16:13:39.998+00:00 — BreakingTaps (@polyfractal)

Content

hm, trying to add a logo similar to the WS logo in the corner. I used the same layers (0/0 background, 81/0 art, 152/5 foreground) but I'm getting an error:

> Failed to extract PR boundary from GDSII view of macro 'gf180mcu_bt_ip__logo'. Ensure that the GDSII view has a PR boundary layer.

any ideas? from checking the docs 0/0 should be the PR_bndry
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message-1445099663400243251

2025-12-01T17:10:08.408+00:00 — LukeW (@luke_w)

Reply/reference

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Looking into why my CTS is weird, I saw there is no max wire length defined. This is my `config.json` from the CTS pass:

```
    "CTS_CLK_MAX_WIRE_LENGTH": 0,
```

Would limiting the max wire length help with the pre/post extraction differences?
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message-1445100435948961944

2025-12-01T17:13:12.598+00:00 — LukeW (@luke_w)

Content

(trying a run now with 500 um just as an experiment)
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message-1445100911939682435

2025-12-01T17:15:06.083+00:00 — BreakingTaps (@polyfractal)

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need to check my notes but if that's the same max_wire_length that I set, it made things much worse. I tried 50 (lol), 500 and 1000 and in all cases the design was notably worse and sometimes failed routing/congestion
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message-1445101032823590922

2025-12-01T17:15:34.904+00:00 — LukeW (@luke_w)

Content

ha
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message-1445101767611383828

2025-12-01T17:18:30.091+00:00 — BreakingTaps (@polyfractal)

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ah ok, so I set `DESIGN_REPAIR_MAX_WIRE_LENGTH` in the config, not sure if that ends up being the same as the CTS setting
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message-1445101852000518289

2025-12-01T17:18:50.211+00:00 — BreakingTaps (@polyfractal)

Content

i assume not
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message-1445101950260613383

2025-12-01T17:19:13.638+00:00 — LukeW (@luke_w)

Content

ah yeah that is something different I believe -- that is a limit on all of the datapath wires that is applied after global placement

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message-1445102021119312056

2025-12-01T17:19:30.532+00:00 — LukeW (@luke_w)

Content

500 um is barely enough to get across an SRAM (440 um wide I believe)
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message-1445102190925709312

2025-12-01T17:20:11.017+00:00 — LukeW (@luke_w)

Content

I looked at my clock tree and the first net has a routed length of over 3.5 mm which is long enough to see from space

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2025-12-01T17:21:02.984+00:00 — BreakingTaps (@polyfractal)

Content

🤞 it works!
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message-1445102705772331069

2025-12-01T17:22:13.766+00:00 — BreakingTaps (@polyfractal)

Content

this last month has been the steepest learning curve of my life haha 😂

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message-1445103082794127563

2025-12-01T17:23:43.655+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

same 🙂
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message-1445103203577499698

2025-12-01T17:24:12.452+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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ASIC design is like waging war. It is exhausting and brutal.

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message-1445103265292226590

2025-12-01T17:24:27.166+00:00 — LukeW (@luke_w)

Reply/reference

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Content

seemed to increase my clock skew by about 1.5 ns so I don't necessarily recommend this 😅

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message-1445104264375701544

2025-12-01T17:28:25.366+00:00 — asic destroyer (@logic_destroyer)

Content

I had  M3.2b violations yesterday, but @Leo Moser (mole99) told me to change DENSITY from 30 to 30.1 and it is gone - lol
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message-1445105163525165286

2025-12-01T17:31:59.74+00:00 — asic destroyer (@logic_destroyer)

Content

My Intel i9 PC has been crunching LibreLAN for weeks – this is going to be expensive. Electricity in Germany is among the most expensive in the world.
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message-1445107272513486879

2025-12-01T17:40:22.562+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Attachments

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message-1445107873167310928

2025-12-01T17:42:45.769+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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just do it! 🙂

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message-1445125343491915827

2025-12-01T18:52:11.019+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

If you're still getting the same error, you can send me a repo/branch so I can take a look.
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message-1445126102703149260

2025-12-01T18:55:12.029+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

`CTS_CLK_MAX_WIRE_LENGTH` only constraints the wire from the clock input pin to the clock root buffer. So it would only shift the whole clock tree, as I understand it.

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message-1445126454634483803

2025-12-01T18:56:35.936+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Yes, there was a strange violation where a trace would be too close to one of the SRAMs.
Just reroll the RNG dice! 😁

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message-1445126626840154283

2025-12-01T18:57:16.993+00:00 — LukeW (@luke_w)

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yeah I looked at the TCL and it seems to be a post-CTS repair step, doesn't do anything during CTS

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message-1445126711342530672

2025-12-01T18:57:37.14+00:00 — LukeW (@luke_w)

Content

Also the related `CTS_DISTANCE_BETWEEN_BUFFERS` seems to do nothing at all

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message-1445127140109713429

2025-12-01T18:59:19.366+00:00 — Leo Moser (mole99) (@mole99)

Content

> -distance_between_buffers: Distance (in microns) between buffers that cts should use when creating the tree. When using this parameter, the clock tree algorithm is simplified and only uses a fraction of the segments from the LUT.

Doesn't sound too useful? But I would have at least expected a change.
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message-1445127190856339547

2025-12-01T18:59:31.465+00:00 — LukeW (@luke_w)

Content

oh and `CTS_TOLERANCE` from OpenLANE was removed 😅
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message-1445127397241520169

2025-12-01T19:00:20.671+00:00 — LukeW (@luke_w)

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I have a weird long clock branch that contains my SRAM, processor register files (which have clock gates due to latches) and nothing else. I was hoping to segment the clock nets a bit more and bring the SRAMs onto the same branch as the logic
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message-1445127437301190830

2025-12-01T19:00:30.222+00:00 — LukeW (@luke_w)

Content

but I might stop messing with CTS for now
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message-1445127733368852480

2025-12-01T19:01:40.81+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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When we complete the tapeout, I’ll be so happy to have my old life back.

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message-1445128319627694312

2025-12-01T19:04:00.585+00:00 — Leo Moser (mole99) (@mole99)

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Content

Fighting with CTS is no fun. This place is not a place of honour.
By the way, what does your clock tree look like before and after SPEF extraction? Is there a significant mismatch?

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message-1445137092022763530

2025-12-01T19:38:52.087+00:00 — BreakingTaps (@polyfractal)

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Content

Will do, thanks! I was looking through logs and noticed that I forgot to add it to the ignore_disconnected, flatten, etc parts of the config for logo/ID.  hoping that resolves things 🤞

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message-1445149247019155566

2025-12-01T20:27:10.064+00:00 — Lofty (@ravenslofty)

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`Chip' - Stage 68 - Design Rule Check (KLayout) ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╸━━━━━ 67/77 7:51:20`
I am having a time of it

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message-1445155535480684544

2025-12-01T20:52:09.35+00:00 — asic destroyer (@logic_destroyer)

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I’d like to learn how to produce nice like @Tholin  GDS renderings, and how to use the TinyTapeout GDS viewer with GF180MCU designs. I noticed that you’ve already integrated support for GF180, and it appears to be working. @urish @Matt Venn
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message-1445158088691810354

2025-12-01T21:02:18.083+00:00 — asic destroyer (@logic_destroyer)

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hmm -
https://www.zerotoasiccourse.com/post/3drendering/

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message-1445159893429391390

2025-12-01T21:09:28.366+00:00 — kris (@kris____)

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i made a fork of gdsiistl that automatically puts the layers at the right height for sky130, if that's of any interest to you: <https://github.com/diy-ic/gdsiistl>
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message-1445159953441751203

2025-12-01T21:09:42.674+00:00 — kris (@kris____)

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not sure how it'd work with gf180, probably won't without some fiddling

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message-1445165807620587694

2025-12-01T21:32:58.419+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

I have changed the layerstack...let see
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message-1445166110562455695

2025-12-01T21:34:10.646+00:00 — kris (@kris____)

Content

good luck 🫡

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message-1445171348967133184

2025-12-01T21:54:59.579+00:00 — Tholin (@tholin)

Content

Final GDSII for me. I was going to keep adding to it and look for any remaining bugs, but I sustained injury to my hand, so that's it for me. Typing with one hand right now, but managed to struggle my way into running make librelane one final time.

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message-1445171476717375710

2025-12-01T21:55:30.037+00:00 — tnt (@246tnt)

Content

@Tholin I'd be curious to explore it. Got it online somewhere ?
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message-1445171613459812452

2025-12-01T21:56:02.639+00:00 — Tholin (@tholin)

Content

Will commit whenever I'm able to
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message-1445171675493568643

2025-12-01T21:56:17.429+00:00 — Tholin (@tholin)

Content

And write docs. Also once recovered.
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message-1445179733020250256

2025-12-01T22:28:18.493+00:00 — asic destroyer (@logic_destroyer)

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I have forgotten to use this from tholin
https://github.com/AvalonSemiconductors/gfmpw1-multi/blob/main/gds2gltf.py
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message-1445207977861709865

2025-12-02T00:20:32.588+00:00 — Lofty (@ravenslofty)

Reply/reference

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`Chip' - Stage 68 - Design Rule Check (KLayout) ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╸━━━━━ 67/77 11:45:25`
um. what do I do when klayout gets stuck on my design.
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message-1445208895374233693

2025-12-02T00:24:11.34+00:00 — Lofty (@ravenslofty)

Content

I am increasingly concerned I will have nothing to tape out because I cannot get it to pass KLayout DRC in any sensible amount of time.
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message-1445210692327178443

2025-12-02T00:31:19.767+00:00 — bailey (@bailey8889)

Reply/reference

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@Lofty that is concerning. Is your design pure digital or do you have hard macros? Are you using any type of SRAM?
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message-1445210755434549288

2025-12-02T00:31:34.813+00:00 — Lofty (@ravenslofty)

Reply/reference

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pure digital, no hard macros, no SRAM.
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message-1445253603135721482

2025-12-02T03:21:50.501+00:00 — LukeW (@luke_w)

Reply/reference

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There are some super cool projects on this die and I'm looking forward to studying it and learning from your schematics once the dust clears post-tapeout 🙂
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message-1445279934082977907

2025-12-02T05:06:28.288+00:00 — BreakingTaps (@polyfractal)

Content

ffffff DRC failures 💀

time to learn how to debug...hopefully it's just the logo art I added 🤞
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message-1445281215119888509

2025-12-02T05:11:33.711+00:00 — LukeW (@luke_w)

Content

Nothing but zeroes 🥳

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message-1445281239874666607

2025-12-02T05:11:39.613+00:00 — LukeW (@luke_w)

Content

except for this one

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message-1445282073463095358

2025-12-02T05:14:58.356+00:00 — LukeW (@luke_w)

Content

They are all `Poly overlap of contact < 0.065um (CO.3)` in 9-track std cells
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message-1445289357144621259

2025-12-02T05:43:54.921+00:00 — bailey (@bailey8889)

Reply/reference

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Looking at the rules in the ciel managed `gf180mcuD` pdk,
```
co3_l.output('CO.3', 'CO.3 : Poly2 overlap of contact. : 0.07µm')
```
Does wafer.space have it's own version of the pdk?
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message-1445289810016206970

2025-12-02T05:45:42.894+00:00 — LukeW (@luke_w)

Content

I think Leo might have some patches that aren't yet merged (then again that might just be LibreLane)
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message-1445290011019972769

2025-12-02T05:46:30.817+00:00 — LukeW (@luke_w)

Content

ah yeah
```
clone-pdk: ## Clone the GF180MCU PDK repository
    rm -rf $(MAKEFILE_DIR)/gf180mcu
    git clone https://github.com/wafer-space/gf180mcu.git $(MAKEFILE_DIR)/gf180mcu --depth 1
.PHONY: clone-pdk
```
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message-1445290300598780026

2025-12-02T05:47:39.858+00:00 — LukeW (@luke_w)

Content

He mentioned there is something odd about how Magic handles contact on this issue: https://github.com/wafer-space/gf180mcu-project-template/issues/34

KLayout doesn't flag those cells (for that rule)

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message-1445292006225084472

2025-12-02T05:54:26.511+00:00 — bailey (@bailey8889)

Reply/reference

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Started a thread.
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message-1445293112540008570

2025-12-02T05:58:50.277+00:00 — BreakingTaps (@polyfractal)

Content

ok so I think my DRC issues are just the logo, looking at the final GDS it's misplaced (apparently the origin being set to lower right corner wasn't honored). A few questions:

- I know KLayout can show DRC violations, but where/what file is that stored in? I'm just seeing json files in the klayout DRC directories
- if I edit the GDS and move it over by hand, think I could restart the flow towards the end? Or will I need to go through the whole build again, fixing it in the config?

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message-1445293265518592161

2025-12-02T05:59:26.75+00:00 — BreakingTaps (@polyfractal)

Content

weirdly it passed all the non-DRC steps which is why I didn't catch it. even renders out to images fine 🙁
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message-1445293393252188302

2025-12-02T05:59:57.204+00:00 — LukeW (@luke_w)

Content

iirc the file you want ends with `.lyrdb`
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message-1445293571920892016

2025-12-02T06:00:39.802+00:00 — LukeW (@luke_w)

Content

you can open that in klayout after opening your GDS and it will flag coordinates of the violations and which rules they violate

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message-1445293606171574344

2025-12-02T06:00:47.968+00:00 — BreakingTaps (@polyfractal)

Content

_begins grepping_
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message-1445293974033006722

2025-12-02T06:02:15.673+00:00 — BreakingTaps (@polyfractal)

Content

aha

> ./63-klayout-density/reports/density.klayout.lyrdb
> ./66-klayout-drc/reports/drc.klayout.lyrdb
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message-1445294007457419314

2025-12-02T06:02:23.642+00:00 — BreakingTaps (@polyfractal)

Content

hiding in reports 🙂
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message-1445294021478977596

2025-12-02T06:02:26.985+00:00 — LukeW (@luke_w)

Content

yeah you want the second one
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message-1445294182443909300

2025-12-02T06:03:05.362+00:00 — LukeW (@luke_w)

Content

it's a bit confusing because the directory with the report is not from the step whose job it is to raise errors when you have DRCs (`checker-klayoutdrc`)
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message-1445294298454036580

2025-12-02T06:03:33.021+00:00 — BreakingTaps (@polyfractal)

Content

yeah that is confusing for sure
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message-1445294335783338099

2025-12-02T06:03:41.921+00:00 — BreakingTaps (@polyfractal)

Content

oh happy days, it's all just this stupid logo art 😅

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message-1445294569670447248

2025-12-02T06:04:37.684+00:00 — BreakingTaps (@polyfractal)

Content

reckon I can fix by hand and then start the run from somewhere towards the end? maybe like 57-magic-streamout?
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message-1445294976622919791

2025-12-02T06:06:14.709+00:00 — Leo Moser (mole99) (@mole99)

Content

If you use my script and Makefile to generate the layout for the logo, there's also a make target to run DRC on the logo itself. Once that is clean you can continue with the integration.
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message-1445295114820784220

2025-12-02T06:06:47.658+00:00 — LukeW (@luke_w)

Content

it's possible in theory, if you copy your `librelane` Makefile target and add `--last-run --from KLayout.DRC` or some  such. I never got the re-runs to work though
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message-1445295146215280711

2025-12-02T06:06:55.143+00:00 — LukeW (@luke_w)

Content

ah, ignore me and  listen to the expert
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message-1445295240012365854

2025-12-02T06:07:17.506+00:00 — Leo Moser (mole99) (@mole99)

Content

No, that's right 😄
But you also need to pass the initial state.
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message-1445295522524041247

2025-12-02T06:08:24.862+00:00 — Leo Moser (mole99) (@mole99)

Content

`--with-initial-state` should point to the input state of e.g. Klayout DRC.
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message-1445295646151020616

2025-12-02T06:08:54.337+00:00 — BreakingTaps (@polyfractal)

Content

ah, well I made the logo using my own jank script and then just copied the layout/structure of the WS logo. 🙁  probably easiest to just redo the whole thing, the DRC is the timesuck anyway and that cant be avoided
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message-1445295665394618489

2025-12-02T06:08:58.925+00:00 — Leo Moser (mole99) (@mole99)

Content

However, to see the changes of your macro, you would need to start the flow from the StreamOut step.
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message-1445295819707125842

2025-12-02T06:09:35.716+00:00 — Leo Moser (mole99) (@mole99)

Content

If you need more logo examples, I added two more in my design here: https://github.com/mole99/gf180mcu-fabulous-fpga

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message-1445295826707419298

2025-12-02T06:09:37.385+00:00 — bailey (@bailey8889)

Content

@BreakingTaps I seen strange placements due to cells not having a bounding box when the lef is created from magic.

If you created the logo in magic, then I recommend loading the logo, setting the bounding box with
```
select top cell
property FIXED_BBOX [box values]
lef write <lef_file> -hide
```

Before that, you could load the lef in klayout to see if the coordinates match the gds. If they don't, then you might try the above solution.
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message-1445295979895980096

2025-12-02T06:10:13.908+00:00 — BreakingTaps (@polyfractal)

Content

will check, thanks for the tip!

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message-1445296441021956221

2025-12-02T06:12:03.849+00:00 — BreakingTaps (@polyfractal)

Content

coordinates do appear to be correct (lower right) in klayout
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message-1445297774286471281

2025-12-02T06:17:21.724+00:00 — BreakingTaps (@polyfractal)

Content

ah, ok I think I see. since I just manually created all the extra stuff (lef, vh, etc) I neglected to see that the lef file specifies an origin too
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message-1445300591965245450

2025-12-02T06:28:33.511+00:00 — BreakingTaps (@polyfractal)

Content

aaand restarted...hopefully I did that right otherwise it would have been best to start all the way over 😅
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message-1445300879862403164

2025-12-02T06:29:42.151+00:00 — BreakingTaps (@polyfractal)

Content

shame DRC is single-threaded, seems like it'd be low hanging fruit to run in parallel? I assume each rule is independent of the others?
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message-1445302161993891931

2025-12-02T06:34:47.835+00:00 — BreakingTaps (@polyfractal)

Content

(i'm also assuming the DRC engine is ruby inside of KLayout but maybe a bad assumption 🙂 )
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message-1445304279584739434

2025-12-02T06:43:12.708+00:00 — urish

Reply/reference

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Content

Started a thread.
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message-1445359606774763603

2025-12-02T10:23:03.738+00:00 — Greg (@greg.hashtag.9468)

Content

The 0p5x0p5 slots are very pad-frame heavy 😅

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message-1445367646731239467

2025-12-02T10:55:00.613+00:00 — Leo Moser (mole99) (@mole99)

Content

Any smaller and you would need to remove the padring on some of the sides 😉

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message-1445372872590753822

2025-12-02T11:15:46.555+00:00 — LukeW (@luke_w)

Content

Huh, that's a DRC I've not seen before: `DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm`.

COMP on top belongs to a `sdffrnq_4` and poly below belongs to a `nand3_4`

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message-1445373733022732309

2025-12-02T11:19:11.698+00:00 — LukeW (@luke_w)

Content

I... think it's just checking in the wrong direction? Also sorry for using cursed cells nobody else uses, in my defence they are faster

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message-1445377946826182786

2025-12-02T11:35:56.347+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Someone has to be first 🙂
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message-1445382346852532316

2025-12-02T11:53:25.395+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Issue report please 👏
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message-1445382462518591558

2025-12-02T11:53:52.972+00:00 — LukeW (@luke_w)

Content

Sure, can I just add it to my existing 9-track DRC issue?
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message-1445382638746730638

2025-12-02T11:54:34.988+00:00 — LukeW (@luke_w)

Content

(being  https://github.com/wafer-space/gf180mcu-project-template/issues/34)

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message-1445382690231681034

2025-12-02T11:54:47.263+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, that's fine 👌
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message-1445395757044727888

2025-12-02T12:46:42.634+00:00 — LukeW (@luke_w)

Reply/reference

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Content

actually I do have a tech map file to map DFFEs and sync set/clear flops as scan flops, which other people could use to improve QoR on their designs, so there might be a lot more `sdffrnq_4` in the future 🙂 https://github.com/Wren6991/RISCBoy-180/blob/main/librelane/gf180_scanflop_map.v

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message-1445395944689635409

2025-12-02T12:47:27.372+00:00 — LukeW (@luke_w)

Content

the only reason I don't recommend using that right now is to get good results you have to disable hold checks on the Q->D path, which I am 99% sure is fine since Q is stable when D is selected, but I'd like to be the guinea pig for one tapeout
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message-1445430961646075966

2025-12-02T15:06:36.065+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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What topology does your chain have?
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message-1445438246476578968

2025-12-02T15:35:32.904+00:00 — Lofty (@ravenslofty)

Reply/reference

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it's not a chain
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message-1445445098795040769

2025-12-02T16:02:46.624+00:00 — asic destroyer (@logic_destroyer)

Content

I assumed to avoid  a big shift register split into multiple chains. Is that correct?
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message-1445445640334217446

2025-12-02T16:04:55.737+00:00 — Lofty (@ravenslofty)

Reply/reference

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Luke's design has no scan chains. use of scan flops does not imply a scan chain
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message-1445446785412759574

2025-12-02T16:09:28.745+00:00 — asic destroyer (@logic_destroyer)

Content

Is it just to reduce logic like muxes and so on?
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message-1445446851300954182

2025-12-02T16:09:44.454+00:00 — Lofty (@ravenslofty)

Reply/reference

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yes, by using scan flops which have that mux merged into the cell.

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message-1445447118683902155

2025-12-02T16:10:48.203+00:00 — asic destroyer (@logic_destroyer)

Content

I appreciate the clarification.
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message-1445453224885751829

2025-12-02T16:35:04.035+00:00 — LukeW (@luke_w)

Content

Following up on the RAM issues I mentioned a few days back: https://github.com/wafer-space/gf180mcu-project-template/issues/38

Am I correct that other RAM enjoyers have their chip selects permanently asserted post startup? That might explain why only I am seeing these issues.

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message-1445462386512367636

2025-12-02T17:11:28.337+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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message-1445462440803434626

2025-12-02T17:11:41.281+00:00 — asic destroyer (@logic_destroyer)

Content

Is that okay?
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message-1445462590128914553

2025-12-02T17:12:16.883+00:00 — BreakingTaps (@polyfractal)

Content

I have mine tied to reset. So it's high for the first cycle/holding down reset, and then permanently low after that.

I did play with enabling/disabling to save power when banks aren't being used, but that introduced at least one extra clock cycle for it to turn back on and was too much hassle to deal with so late in my project
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message-1445462662505828412

2025-12-02T17:12:34.139+00:00 — BreakingTaps (@polyfractal)

Content

(well not specifically the reset pin, but the reset logic)
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message-1445463811716026410

2025-12-02T17:17:08.132+00:00 — asic destroyer (@logic_destroyer)

Content

I’m going to be so happy when the tape-out is done, because every time I look up here now, I flinch. It’s really like being on a carousel.
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message-1445465931173073089

2025-12-02T17:25:33.45+00:00 — BreakingTaps (@polyfractal)

Content

yah seriously. I just know someone is going to post a "Hey make sure XYZ" and I'll realize mine is opposite but it's too late to change 💀

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message-1445466162510172331

2025-12-02T17:26:28.605+00:00 — BreakingTaps (@polyfractal)

Content

oh well, if it arrives totally broken at least I'll have some neat trinkets and a good learning experience 😊
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message-1445466769136549929

2025-12-02T17:28:53.236+00:00 — Tholin (@tholin)

Content

Update: one of my artists got back to me with two PNG files and "sorry I'm late"
I am turning my PC on again and making this happen, no matter what.
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message-1445466881728450673

2025-12-02T17:29:20.08+00:00 — Tholin (@tholin)

Content

I have just a little bit of free space on the right of my layout
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message-1445466953891188786

2025-12-02T17:29:37.285+00:00 — Tholin (@tholin)

Content

About to play high-stakes tetris
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message-1445467533472956551

2025-12-02T17:31:55.468+00:00 — LukeW (@luke_w)

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Content

yeah this is functionally fine, you just waste power by reading the RAM every cycle
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message-1445467792580022362

2025-12-02T17:32:57.244+00:00 — LukeW (@luke_w)

Content

ok so that explains the inconsistency, thanks
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message-1445468393145634928

2025-12-02T17:35:20.43+00:00 — asic destroyer (@logic_destroyer)

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which inconsistency?
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message-1445468757043449918

2025-12-02T17:36:47.19+00:00 — asic destroyer (@logic_destroyer)

Content

Wasting how much power?
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message-1445469290101735568

2025-12-02T17:38:54.281+00:00 — LukeW (@luke_w)

Reply/reference

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Content

like a milliwatt per RAM instance iirc
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message-1445469345777062111

2025-12-02T17:39:07.555+00:00 — LukeW (@luke_w)

Content

there are some power figures in the docs though they're not particularly illuminating
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message-1445469481840410716

2025-12-02T17:39:39.995+00:00 — LukeW (@luke_w)

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Content

The fact the RAM model worked for other people and fell on its ass for me. It sounds like I'm the only person deasserting chip select when I don't intend to read the RAM.
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message-1445470951545376799

2025-12-02T17:45:30.4+00:00 — LukeW (@luke_w)

Reply/reference

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> but that introduced at least one extra clock cycle for it to turn back on
I don't understand this part. CEN is aligned with the address
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message-1445471538756456449

2025-12-02T17:47:50.402+00:00 — BreakingTaps (@polyfractal)

Content

honestly no idea. I added a second bank of memory at some point, and noticed that I was throwing away a read each cycle. Checked the docs and saw that I could probably use CEN de-activate unused memory but then tests started failing because the second bank wasn't active when it was needed.

had bigger issues to deal with so went back to just perma-enabled 🙂
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message-1445471652992385116

2025-12-02T17:48:17.638+00:00 — BreakingTaps (@polyfractal)

Content

from a quick skim of the waveforms it looked like it was just one cycle behind but didn't investigate much
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message-1445471696810414183

2025-12-02T17:48:28.085+00:00 — LukeW (@luke_w)

Content

you might have hit the bug in the RAM model
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message-1445471843451535442

2025-12-02T17:49:03.047+00:00 — BreakingTaps (@polyfractal)

Content

aha! would make sense given the issues you've run into as well. I just assumed it took the memory an extra cycle to power back up or something 😅
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message-1445471848149291199

2025-12-02T17:49:04.167+00:00 — LukeW (@luke_w)

Content

This is the behavioural RAM model I've been using for most of my sims:

```verilog
reg [WIDTH-1:0] mem [0:DEPTH-1];

reg [WIDTH-1:0] rdata_q;
assign rdata = rdata_q;
always @ (posedge clk) begin: update
    integer i;
    if (!cs_n && we_n) begin
        rdata_q <= mem[addr];
    end
    if (!cs_n && !we_n) begin
        for (i = 0; i < WIDTH / 8; i = i + 1) begin
            if (!be_n[i]) begin
                mem[addr][i * 8 +: 8] <= wdata[i * 8 +: 8];
            end
        end
    end
end
```
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message-1445472089363447911

2025-12-02T17:50:01.677+00:00 — LukeW (@luke_w)

Content

basically all inputs are sampled together on the posedge and rdata is valid some time in the next cycle. Pretty much all synchronous SRAMs look like this
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message-1445472353860587661

2025-12-02T17:51:04.738+00:00 — LukeW (@luke_w)

Content

it matches up with the transition table in the RAM docs as well, and matches up with their model if you ignore all the weird behavioural delay stuff they've hacked in
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message-1445472533527658598

2025-12-02T17:51:47.574+00:00 — LukeW (@luke_w)

Content

also the fact that read data stays valid if you don't do another read is handy and I exploit it in one place
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message-1445472558538555542

2025-12-02T17:51:53.537+00:00 — BreakingTaps (@polyfractal)

Content

you'd think a model provided by the foundry would be correct 😭   as a complete outsider to the industry, i'm kinda horrified what passes as normal (from the little bit I've peeked behind the curtain)
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message-1445472617967386767

2025-12-02T17:52:07.706+00:00 — LukeW (@luke_w)

Content

it's not normal

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message-1445472628931559494

2025-12-02T17:52:10.32+00:00 — BreakingTaps (@polyfractal)

Content

especially for such an old node!
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message-1445472923698597918

2025-12-02T17:53:20.598+00:00 — LukeW (@luke_w)

Content

we simulate RTL against vendor RAM models all the time and it's fine because the functional behaviour is described synchronously (maybe with a delay on the read data), and then they add timing checks which you can disable for behavioural sims where there are no delays
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message-1445472979193430108

2025-12-02T17:53:33.829+00:00 — LukeW (@luke_w)

Content

these models are just kinda hacky
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message-1445473018208846004

2025-12-02T17:53:43.131+00:00 — BreakingTaps (@polyfractal)

Content

welp
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message-1445473109032566845

2025-12-02T17:54:04.785+00:00 — LukeW (@luke_w)

Content

but yes it is true the ASIC industry is much messier than people think
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message-1445473158176968939

2025-12-02T17:54:16.502+00:00 — LukeW (@luke_w)

Content

lots of people who are actually software engineers and just don't want to admit it
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message-1445473191584731357

2025-12-02T17:54:24.467+00:00 — BreakingTaps (@polyfractal)

Content

maybe they just threw it together as a low priority intern project, since they knew it was part of the original open sourcing efforts?
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message-1445473303018868776

2025-12-02T17:54:51.035+00:00 — asic destroyer (@logic_destroyer)

Content

Can I leave it as it is? @LukeW
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message-1445473364511817730

2025-12-02T17:55:05.696+00:00 — LukeW (@luke_w)

Reply/reference

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yes

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message-1445473519268790354

2025-12-02T17:55:42.593+00:00 — LukeW (@luke_w)

Reply/reference

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Content

I did wonder but the model is from 2014:

```
 * Project:             018 5VGREEN SRAM
 * Author:              GlobalFoundries PDK Authors
 * Data Created:        05-06-2014
 * Revision:        0.0
```

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message-1445473597845016648

2025-12-02T17:56:01.327+00:00 — asic destroyer (@logic_destroyer)

Content

When you enable CEN, do you have to wait another clock cycle?
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message-1445473694502748171

2025-12-02T17:56:24.372+00:00 — LukeW (@luke_w)

Reply/reference

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I wouldn't change your design now given there are issues with the RAM models. What you have should work
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message-1445473841269706914

2025-12-02T17:56:59.364+00:00 — LukeW (@luke_w)

Content

but no, `!CEN && GWEN` is a read enable which is aligned with the address. If that function is true on cycle _n_ then new read data is valid on Q on cycle _n_ + 1
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message-1445473941702312118

2025-12-02T17:57:23.309+00:00 — LukeW (@luke_w)

Content

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message-1445474105825427577

2025-12-02T17:58:02.439+00:00 — asic destroyer (@logic_destroyer)

Content

When you have caches and a pipelined CPU, should the CEN signal always be low, since the CPU is doing work every cycle anyway?
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message-1445474187677401140

2025-12-02T17:58:21.954+00:00 — LukeW (@luke_w)

Content

are you issuing a load/store to your D cache every cycle?
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message-1445474241125290185

2025-12-02T17:58:34.697+00:00 — asic destroyer (@logic_destroyer)

Content

I$ and D$
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message-1445474293059162333

2025-12-02T17:58:47.079+00:00 — LukeW (@luke_w)

Content

are you fetching instructions from your I cache when you're stalled on a `div` or `rem`?
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message-1445474451943588032

2025-12-02T17:59:24.96+00:00 — asic destroyer (@logic_destroyer)

Content

Out of order, superscalar 🙂
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message-1445474779598684231

2025-12-02T18:00:43.079+00:00 — LukeW (@luke_w)

Content

Your icache will still stall -- you normally overprovision icache bandwidth so you can catch up after a flush. Anyway no, it is not normal for production designs to enable RAMs when they don't intend to read or write them.
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message-1445475244889604348

2025-12-02T18:02:34.013+00:00 — asic destroyer (@logic_destroyer)

Content

Got it
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message-1445475336992325843

2025-12-02T18:02:55.972+00:00 — asic destroyer (@logic_destroyer)

Content

Every stall counts
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message-1445476660743766178

2025-12-02T18:08:11.579+00:00 — asic destroyer (@logic_destroyer)

Content

Then you have saved 28 mW?
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message-1445480920349020333

2025-12-02T18:25:07.148+00:00 — LukeW (@luke_w)

Content

That's worst case at 1 MHz

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message-1445483581114683563

2025-12-02T18:35:41.524+00:00 — asic destroyer (@logic_destroyer)

Content

k
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message-1445490428815347863

2025-12-02T19:02:54.143+00:00 — LukeW (@luke_w)

Content

For anyone else who needs it

```makefile
librelane-yolo: ## Run full flow, including DRC, but don't quit after DRC errors
    librelane librelane/config.yaml --pdk ${PDK} --pdk-root ${PDK_ROOT} --manual-pdk --skip Checker.MagicDRC --skip Checker.KLayoutDRC
.PHONY: librelane-yolo
```

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message-1445490968177541141

2025-12-02T19:05:02.737+00:00 — Leo Moser (mole99) (@mole99)

Content

And if you want to add it to your config:

```yaml
QUIT_ON_MAGIC_DRC: False
QUIT_ON_KLAYOUT_DRC: False
```
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message-1445491647415849022

2025-12-02T19:07:44.68+00:00 — LukeW (@luke_w)

Content

ooh nice
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message-1445499614651224188

2025-12-02T19:39:24.217+00:00 — Tholin (@tholin)

Content

No square micrometer unused

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message-1445499825511469137

2025-12-02T19:40:14.49+00:00 — Tholin (@tholin)

Content

I turned off KLayout DRC and saving that for the precheck.
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message-1445499859410092246

2025-12-02T19:40:22.572+00:00 — Tholin (@tholin)

Content

All the macros individually pass KLayout DRC
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message-1445499888577155245

2025-12-02T19:40:29.526+00:00 — Tholin (@tholin)

Content

So hopefully nothing bad hapens.
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message-1445536455626592379

2025-12-02T22:05:47.79+00:00 — Greg (@greg.hashtag.9468)

Content

@LukeW I had seen the same thing. I'd initially hooked CEN upto the processor read strobe. But the last byte in a bust would read back incorrect. Seems like the vendor model adjusts Q on that last cycle when CEN=H, which doesn't really match with the "Hold previous data" statement.
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message-1445544431750221845

2025-12-02T22:37:29.446+00:00 — LukeW (@luke_w)

Reply/reference

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Content

Which one do you trust?
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message-1445544473797984327

2025-12-02T22:37:39.471+00:00 — LukeW (@luke_w)

Content

Normally I would say the vendor model but...
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message-1445558681449267310

2025-12-02T23:34:06.839+00:00 — Tholin (@tholin)

Content

Alright. This kicks ass!

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message-1445558879646650522

2025-12-02T23:34:54.093+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Passes DRC?
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message-1445558915860267110

2025-12-02T23:35:02.727+00:00 — Tholin (@tholin)

Content

Passes magic DRC
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message-1445559062954770515

2025-12-02T23:35:37.797+00:00 — Tholin (@tholin)

Content

LVS failed because I forgot to add some entries to LVS_FLATTEN_CELLS
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message-1445559147000103104

2025-12-02T23:35:57.835+00:00 — Tholin (@tholin)

Content

Re-running now, then will throw the output straight at precheck.
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message-1445562869247770674

2025-12-02T23:50:45.288+00:00 — bailey (@bailey8889)

Reply/reference

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@Tholin What command are you using to run LVS?

Most of the behind the scenes commands have a `--noextract` option which will use the existing extracted data in the `WORK_ROOT` directory.
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message-1445579568340668456

2025-12-03T00:57:06.662+00:00 — Greg (@greg.hashtag.9468)

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I've followed the vendor model. Probably would be nice if a design in this shuttle had signals to RAM so it could be confimed..
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message-1445594216523763733

2025-12-03T01:55:19.061+00:00 — Tholin (@tholin)

Content

Lots of projects on my die

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message-1445605302803103926

2025-12-03T02:39:22.236+00:00 — LukeW (@luke_w)

Reply/reference

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Aight, well I'm 99% it's actually a synchronous RAM in spite of the model's protests but since I don't have time to run spice on it I'll add a chicken bit to my debugger that forces all the RAM chip selects low 😅
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message-1445606039587127457

2025-12-03T02:42:17.899+00:00 — LukeW (@luke_w)

Content

No room for more 😎

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message-1445626759562399825

2025-12-03T04:04:37.926+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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How much memory is that?
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message-1445634476100292670

2025-12-03T04:35:17.692+00:00 — LukeW (@luke_w)

Content

* CPU RAM: 8 kB (16 x 512 x 8)
* APU RAM: 4 kB (8 x 512 x 8)
* PPU scan buffers: 2 x 512-pixel (4 x 512 x 8)
* PPU palette RAM: 1 x 256-pixel (2 x 256 x 8)

So I guess 14.5 kB 🙂
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message-1445634628756177040

2025-12-03T04:35:54.088+00:00 — LukeW (@luke_w)

Content

then the external RAM is 256 kB 16-bit wide
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message-1445649062626857023

2025-12-03T05:33:15.391+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

14.5kB isn't too bad...
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message-1445649717861154940

2025-12-03T05:35:51.611+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@LukeW - Well, if you have some spare time then, want to do some 1x0.5 and/or 0.5x1 projects which might work with your external RAM interface?
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message-1445655984688205944

2025-12-03T06:00:45.739+00:00 — urish

Reply/reference

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Awesome graphics! Well done 🙂
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message-1445664732915826738

2025-12-03T06:35:31.479+00:00 — LukeW (@luke_w)

Content

```c
/*******************************************************************************
*                                 SRAM_CHICKEN                                 *
*******************************************************************************/

// The foundry SRAM models return incorrect data if chip select transitions on a
// clock edge. 99% sure this is just an issue with the model, but just in case,
// this register forces all SRAMs to be permanently enabled. You should clear
// this bit to avoid wasting power.

// Field: SRAM_CHICKEN  Access: RW
// Reset: 0x1
#define SYSCFG_SRAM_CHICKEN_LSB  0
#define SYSCFG_SRAM_CHICKEN_BITS 1
#define SYSCFG_SRAM_CHICKEN_MASK 0x1
```

I can simulate with the unmodified foundry models now. When I get chips back I'll find out whether that was necessary.

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message-1445664963334115329

2025-12-03T06:36:26.415+00:00 — LukeW (@luke_w)

Reply/reference

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Sorry, not this tapeout 😅  I'm going to keep testing up until the last minute
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message-1445820599824945242

2025-12-03T16:54:53.046+00:00 — Tholin (@tholin)

Content

Started on docs:
https://avalonsemiconductors.github.io/WS2025/multiplexer.html
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message-1445839027755548805

2025-12-03T18:08:06.607+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Tim 'mithro' Ansell @Leo Moser (mole99) I have my design in 2 formats - a) slot 1x1 and b) quarter slot 0.5x0.5. What do you think is a better for submission for *this* shuttle?
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message-1445839382941667572

2025-12-03T18:09:31.29+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Would 0.5 x 0.5 give better or worse "yield". Would it be harder to put on board, etc.
Any benefits of going 0.5 x 0.5 at all?
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message-1445839608192434177

2025-12-03T18:10:24.994+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

I understand it is a lot on your plate, so I might just submit both for now and we finalise that decision next week?
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message-1445840323216670822

2025-12-03T18:13:15.469+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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There is only one 0.5x0.5 slot for this shuttle, but this may change for run 2 if there is more demand. Unfortunately, this slot has already been assigned to someone else.

You could use the 0.5x1 or 1x0.5 slots instead of the 1x1 slot.
However, the CoB is currently only prepared for the 1x1 slot. There is no PCB for the others yet, so it may be better to stay with the 1x1?
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message-1445840743850705080

2025-12-03T18:14:55.756+00:00 — Leo Moser (mole99) (@mole99)

Content

Given that most of the 1x1 area is unused, I don't think there's much difference in yield.
Also, I'm not sure if yield is really an issue for this process.

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message-1445842971261014057

2025-12-03T18:23:46.812+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Using 1x1 slot is no problem for me!
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message-1445843858507432028

2025-12-03T18:27:18.348+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Sorry! I just checked the spreadsheet and the other 1x1 slot that is assigned to you is for a different project (RZML), correct? If so, could you rather use a 1x0.5 slot?
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message-1445844510989881475

2025-12-03T18:29:53.912+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

I think it should be the other way around - Z80 is the primary project and another one is "good to have". Anyway, I will do 1x0.5 just in case.
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message-1445854734119469228

2025-12-03T19:10:31.296+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Well, you have at least one 1x1 slot reserved. Hopefully Tim can clarify in the morning.
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message-1445887574383005767

2025-12-03T21:21:01.025+00:00 — Greg (@greg.hashtag.9468)

Content

After improving my in-efficient RTL I did manage to fit 23 servs on a design. 🏁

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message-1445887773948117185

2025-12-03T21:21:48.605+00:00 — Greg (@greg.hashtag.9468)

Content

Scales into a half-width slot too with just 9 cores

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message-1445893486632239144

2025-12-03T21:44:30.615+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Can you create a project on the platform for that one too? Maybe there's some space left :)
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message-1445893756548288624

2025-12-03T21:45:34.968+00:00 — BreakingTaps (@polyfractal)

Content

hm a last minute GDS art addition is now triggering MT.1  ("min. metaltop width : 0.44µm") and MT.2a ("min. metaltop spacing : 0.46µm")  DRC errors. Any ideas or try regenerating with a slightly different size?
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message-1445895083906961548

2025-12-03T21:50:51.435+00:00 — LukeW (@luke_w)

Reply/reference

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Yeah I just had the same thing because a hole in the metal generated by the image script left two corners touching

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message-1445895154119475271

2025-12-03T21:51:08.175+00:00 — LukeW (@luke_w)

Content

I just opened it up in klayout and squished the hole, hopefully that fixes it
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message-1445895272046526564

2025-12-03T21:51:36.291+00:00 — LukeW (@luke_w)

Content

(apparently `klayout -e` is the magic flag required to actually let you edit anything)

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message-1445895290698600539

2025-12-03T21:51:40.738+00:00 — Greg (@greg.hashtag.9468)

Reply/reference

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Content

It's in and passed the current pre-check 👍

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message-1445895433934209034

2025-12-03T21:52:14.888+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

yeah that looks like my issues. i'm not great with klayout, how did you close the hole? Just draw a new polygon to fill it, or did you edit the existing polygon?
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message-1445895984302260296

2025-12-03T21:54:26.106+00:00 — Greg (@greg.hashtag.9468)

Content

The script used for the waferspace logo does a DRC check. But doesn't grep/show errors the DRC found. You have to dig into the .xml report, and look under the <items> tree
So I had a similar issue on my logo art
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message-1445896990293753970

2025-12-03T21:58:25.953+00:00 — BreakingTaps (@polyfractal)

Content

aha, that's good to know for a faster check. cheers!
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message-1445897099676876951

2025-12-03T21:58:52.032+00:00 — LukeW (@luke_w)

Content

ah. I saw it ran a DRC in the Makefile, didn't see that it didn't propagate an exit code 😅  thanks Greg

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message-1445897562870648832

2025-12-03T22:00:42.466+00:00 — Leo Moser (mole99) (@mole99)

Content

Btw. you can load the DRC results using the Marker Browser in KLayout.
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message-1445897623729868890

2025-12-03T22:00:56.976+00:00 — LukeW (@luke_w)

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I used the "partial" tool to drag over the edge on the left hand side of the hole until it met the right hand side

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message-1445897711839744000

2025-12-03T22:01:17.983+00:00 — LukeW (@luke_w)

Content

it should snap and the redundant vertices should disappear
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message-1445898221498007663

2025-12-03T22:03:19.495+00:00 — BreakingTaps (@polyfractal)

Content

rad, thanks!
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message-1445900764915695757

2025-12-03T22:13:25.893+00:00 — BreakingTaps (@polyfractal)

Content

aaand fixed, re-drc time

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message-1445902555610878002

2025-12-03T22:20:32.828+00:00 — Tim 'mithro' Ansell (@mithro_)

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@ReJ aka Renaldas Zioma - I would suggest making sure ***all*** are on https://platform.wafer.space - that way we have choice. I think we'll find a way to have both.

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message-1445902833411948715

2025-12-03T22:21:39.061+00:00 — Tim 'mithro' Ansell (@mithro_)

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I ***think*** I have two 1x1 slots allocated for @ReJ aka Renaldas Zioma
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message-1445903109954998385

2025-12-03T22:22:44.994+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Think you could do a version of that half-width slot with *just* the SRAM connected to the I/O pins?
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message-1445903974061576408

2025-12-03T22:26:11.013+00:00 — Greg (@greg.hashtag.9468)

Content

Yeah. Easy could do that. So target the 0.5x1 slot? Just a 512x8 instance?
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message-1445904292547395624

2025-12-03T22:27:26.946+00:00 — Greg (@greg.hashtag.9468)

Content

We can add the other sizes too, but would require sharing the A/D bus? Along with muxing on the Q
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message-1445905486816870503

2025-12-03T22:32:11.682+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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All the sizes! 😛
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message-1445905545444720794

2025-12-03T22:32:25.66+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

According to @LukeW, something like https://www.renesas.com/en/document/dst/r1rp0416di-series-datasheet?srsltid=AfmBOor09cVZb0I6oElST_hOGtjGlgGKCuuOzj2dmwoCr6L8-vb7cOhK would be the competition 🙂
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message-1445906029190709469

2025-12-03T22:34:20.994+00:00 — Greg (@greg.hashtag.9468)

Content

Right I misunderstood. So not a test structure for just a single instance. But fill the area with the 512x8 instances and add address decoding. 👍
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message-1445906704175992983

2025-12-03T22:37:01.923+00:00 — LukeW (@luke_w)

Content

so we can finally get to the bottom of the CEN controversy
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message-1445907086390067348

2025-12-03T22:38:33.05+00:00 — Trevor Peyton (@trev5514)

Content

I tried doing `STD_CELL_LIBRARY: gf180mcu_fd_sc_mcu9t5v0` in the project template and it's not applied (still the 7 track cell). Is this overriden somewhere I'm missing?
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message-1445907292644966502

2025-12-03T22:39:22.225+00:00 — Greg (@greg.hashtag.9468)

Content

Quick test: try doing an `export STD_CELL_LIBRARY=gf180mcu_fd_sc_mcu9t5v0` in your shell
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message-1445907293517647952

2025-12-03T22:39:22.433+00:00 — LukeW (@luke_w)

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That was the only flag I had to pass, and I am definitely getting 9-track cells in my layout
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message-1445907495460802571

2025-12-03T22:40:10.58+00:00 — Greg (@greg.hashtag.9468)

Content

I think this was raised before, in the latest template, the extra yaml for the slot sizes may be applying some defaults
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message-1445907720069709914

2025-12-03T22:41:04.131+00:00 — Greg (@greg.hashtag.9468)

Content

Your project @LukeW has everything in the one config.yaml
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message-1445907732480790693

2025-12-03T22:41:07.09+00:00 — LukeW (@luke_w)

Content

ahh ok, that would make sense. I squashed those commits out when I merged because I didn't want to deal with the huge merge conflict with my padring changes and my other changes in that file 😅
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message-1445909535670931499

2025-12-03T22:48:17.004+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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https://docs.google.com/document/d/1hk0WXCmQ8LYNhn8gIVs8vHymR2MleQx2ro_hQlyOYKU/edit?tab=t.0

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    "description": "GF180MCU SRAM Maximizer Goal Work out the maximum amount of SRAM that is able to fit into the GF180MCU configuration.  Specification Layout as many SRAMs as possible that fit in a given die space.  Current die size - 3.88mm x 5.07mm     Die Size         Instances    Total  Wi...",
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message-1445909989561602179

2025-12-03T22:50:05.22+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

If someone wants to do something else random, you could also try filling the die just with capacitors - https://docs.google.com/document/d/1ahoCTmPvKExYtk3qqxvjMpnq5XOcIQvVWMF84zgi82k/edit?tab=t.0#heading=h.psr38aq67ats - I was sure I had more info in that doc but it appears I miss remembered.

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    "description": "GF180MCU Silicon Capacitor Goal Create software which is able to generate a \"maximal silicon capacitor\" for a given configuration.  Specifications  GDSFactory Uses AI to tune the capacitor capacity Initial targets are the different GF180MCU stack ups.   Why? Empty slots can be filled with silicon...",
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    "title": "wafer.space - GF180MCU Silicon Capacitor",
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message-1445913058420723888

2025-12-03T23:02:16.893+00:00 — BreakingTaps (@polyfractal)

Content

7T vs 9T: is it just that 9T are bigger so they can drive harder and suffer from timing issues less?
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message-1445913761712967803

2025-12-03T23:05:04.571+00:00 — Trevor Peyton (@trev5514)

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Content

My understanding is that 9T is larger and has more room for routing so it can typically run faster. I believe there is also a power tradeoff with them.

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message-1445913883003850822

2025-12-03T23:05:33.489+00:00 — Trevor Peyton (@trev5514)

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Content

I didn't see any 7t overrides, do you happen to know where it was brought up?
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message-1445914626792624139

2025-12-03T23:08:30.822+00:00 — BreakingTaps (@polyfractal)

Content

think it was mentioned here: https://discord.com/channels/1361349522684510449/1423348662318272592/1445014108750745621

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message-1445915080947667096

2025-12-03T23:10:19.101+00:00 — Trevor Peyton (@trev5514)

Content

That would be it! Easy fix, thank you!
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message-1445963573825110077

2025-12-04T02:23:00.704+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I'm not sure but I think @LukeW found a bunch of potential DRC violations inside the 9t cells? Or was I confused about that?

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message-1445969250505199757

2025-12-04T02:45:34.13+00:00 — ReJ aka Renaldas Zioma (@rzioma)

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Content

I hope not, I am using 9T.
I think I haven't see any DRCs on them.
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message-1445969461818691747

2025-12-04T02:46:24.511+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://github.com/wafer-space/gf180mcu-project-template/issues/34

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message-1445969772062838854

2025-12-04T02:47:38.479+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Looks like it might just be the clock gate cell
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message-1446018887001968681

2025-12-04T06:02:48.393+00:00 — Leo Moser (mole99) (@mole99)

Content

These all seem to be false positives. At least the CO rules in magic are, due to the way the rules are implemented.
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message-1446079864653352984

2025-12-04T10:05:06.598+00:00 — LukeW (@luke_w)

Content

I haven't been updating that issue with all the flagged DRCs because I think we need to just DRC the whole library post-tapeout. I no longer have any ICGTPs in my design (just two ICGTNs) but I do have a lot of `sdffq_4` which are also flagged by Magic.
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message-1446128540109246585

2025-12-04T13:18:31.731+00:00 — BreakingTaps (@polyfractal)

Content

hot damn these 9T cells are giving much better results for my design

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message-1446138800022749274

2025-12-04T13:59:17.885+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Content

Is your design 3.3 or 5V?
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message-1446139130785431733

2025-12-04T14:00:36.745+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

5V
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message-1446139631073624144

2025-12-04T14:02:36.023+00:00 — BreakingTaps (@polyfractal)

Content

went from barely scraping by the ss/hot corners with tonnnns of slack/margin/buffer tweaking, to gobs of margin and I'm starting to dial back the settings (and increase the speed). like 0.2ns slack up to 30ns slack in some corners

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message-1446165809683763211

2025-12-04T15:46:37.49+00:00 — asic destroyer (@logic_destroyer)

Content

What is the current flow? Do I just run libralane-nodrc to generate the GDS, and then verify the GDS using fg180mcu-precheck?
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message-1446221836433100860

2025-12-04T19:29:15.308+00:00 — Trevor Peyton (@trev5514)

Content

I think a separate GF180 macro template would be a great addition to complement this template. The further along this template has come, the more focused it is on top level, but it has lots of great features that are specific to GF180 that would be useful for making macros.
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message-1446232840831242386

2025-12-04T20:12:58.961+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1446233012118487272

2025-12-04T20:13:39.799+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 The PDK and project template have been updated with the following changes:

- PDK [1.3.1](https://github.com/wafer-space/gf180mcu/releases/tag/1.3.1)
  - Implement CUP.2 and CUP.3 rules.
  - Modify the pad library to conform to CUP.2 and CUP.3.
  - Flatten the guard ring and merge the marker polygons.
  - Correct `ANTENNAGATEPLUSDIFF` in the techlef for thick oxide devices. (thanks @egor!)

- Project template [1.2.2](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.2.2)
  - Update the PDK to 1.3.1.
  - Enable KLayout antenna checks by default.
  - Add a script to generate standalone padrings for analog designs.

Please ensure you update your project and clone the latest PDK version.

Note: This is not the final update to the project template and PDK before the tapeout. At least one more update to the filler generation is planned.
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message-1446233054736683008

2025-12-04T20:13:49.96+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.

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message-1446247605754396853

2025-12-04T21:11:39.193+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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PDK_TAG in Makefile is 1.3.0 is that ok?
I built a chip via  PDK_TAG=1.3.1 make librelane-nodrc
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message-1446254295656693762

2025-12-04T21:38:14.19+00:00 — Leo Moser (mole99) (@mole99)

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The PDK_TAG in the Makefile should be 1.3.1: https://github.com/wafer-space/gf180mcu-project-template/blob/6ca8397bb7542385b5537af4e4b6d5ed80882b57/Makefile#L8

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message-1446291237354078391

2025-12-05T00:05:01.777+00:00 — BreakingTaps (@polyfractal)

Content

after updating and rebuilding, should we re-submit to platform.wafer.space ? or just hold off until the final update with filler changes?
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message-1446313837140644011

2025-12-05T01:34:49.986+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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There is a bit of a queue on the precheck at the moment. I'm working on an upgrade for the queueing that should make things go faster.

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message-1446446102734962835

2025-12-05T10:20:24.561+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Major performance update!

A long-standing issue in the KLayout DRC deck has been discovered and fixed 🎉
Many thanks to Matthias for [investigating the issue and providing a solution](https://github.com/KLayout/klayout/issues/2241#issuecomment-3612915372).
This reduces the time taken by KLayout DRC for one tested design from several hours to just 1.5h ⏱️

- PDK [1.4.1](https://github.com/wafer-space/gf180mcu/releases/tag/1.4.1)
  - Fix the connectivity setup in KLayout DRC.
  - Check for both P/N-type diodes in the KLayout antenna script. (thanks @tnt!)

Make sure to update your project and your local precheck with the latest PDK:

- Project template [1.2.3](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.2.3)
- Precheck [1.4.2](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.4.2)

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message-1446446172695822517

2025-12-05T10:20:41.241+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1446450880768638986

2025-12-05T10:39:23.733+00:00 — Thorben (@thorben_61995)

Content

Awesome, my current precheck is still not finished after > 27 hours and was stuck for most of the time in the connectivity setup 😆
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message-1446452145103704076

2025-12-05T10:44:25.174+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Well, let me know how it goes 😉

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message-1446456490511695924

2025-12-05T11:01:41.2+00:00 — tnt (@246tnt)

Content

BTW, running antenna check pre-fill GDS also seemed to speed it up a bit FWIW.
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message-1446463139339309118

2025-12-05T11:28:06.404+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes, this is because both the antenna script and the DRC deck consider the dummy shapes for their checks. Since we have dedicated DRC rules for dummy, which ensures they are spaced from active metal, there's no need to include them here. It's on my list :)
In fact, I have already removed the dummy shapes from the connectivity setup.

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message-1446522068647678024

2025-12-05T15:22:16.246+00:00 — Thorben (@thorben_61995)

Reply/reference

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So the old precheck took a whopping "1 day, 12:33:53" to complete on my design (luckily successfully) on a big server. I'm currently running the updated one to see how much faster it goes. If the current pipeline on platform.wafer.space is still running with the old precheck version, you might want to remove my submission from the queue (seems like a waste of time).
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message-1446534939418820661

2025-12-05T16:13:24.877+00:00 — asic destroyer (@logic_destroyer)

Content

@Lofty What is the likelihood that the gate-level implementation might no longer match the behavioral specification? I’m asking because we constantly build chips, and although we could preserve stage 6, I wanted to understand whether this mismatch is actually possible.
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message-1446535310560464997

2025-12-05T16:14:53.364+00:00 — Lofty (@ravenslofty)

Reply/reference

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Um. I think I'm lacking context here. I assume you mean stage 6 of LibreLane, which is Yosys synthesis
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message-1446535349122760747

2025-12-05T16:15:02.558+00:00 — asic destroyer (@logic_destroyer)

Content

yes
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message-1446535433604436080

2025-12-05T16:15:22.7+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

Then the likelihood being above zero is a bug :p

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message-1446535697275293798

2025-12-05T16:16:25.564+00:00 — asic destroyer (@logic_destroyer)

Content

Otherwise, we would always have to completely rebuild everything starting from stage 6, even though that stage has already been thoroughly tested.
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message-1446535879865663698

2025-12-05T16:17:09.097+00:00 — Lofty (@ravenslofty)

Content

I assume you're rebuilding the chips because you need to change some librelane `config.yaml` setting?
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message-1446536123169116222

2025-12-05T16:18:07.105+00:00 — asic destroyer (@logic_destroyer)

Content

And many other things as well, but they’re mostly only relevant for everything after stage 6.
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message-1446536222808871115

2025-12-05T16:18:30.861+00:00 — Lofty (@ravenslofty)

Content

you should be more specific about what you're changing
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message-1446536287040311398

2025-12-05T16:18:46.175+00:00 — asic destroyer (@logic_destroyer)

Content

https://github.com/wafer-space/gf180mcu-project-template/tree/main
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message-1446536334259785912

2025-12-05T16:18:57.433+00:00 — Lofty (@ravenslofty)

Content

I mean the librelane settings
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message-1446536346444496937

2025-12-05T16:19:00.338+00:00 — asic destroyer (@logic_destroyer)

Content

https://github.com/wafer-space/gf180mcu
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message-1446536450714894507

2025-12-05T16:19:25.198+00:00 — Lofty (@ravenslofty)

Content

e.g. if you're changing `STD_CELL_LIBRARY` from 7-track to 9-track, you need to go through Yosys again
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message-1446536490430501014

2025-12-05T16:19:34.667+00:00 — Lofty (@ravenslofty)

Reply/reference

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this is a PDK, not the librelane settings.
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message-1446536564451705036

2025-12-05T16:19:52.315+00:00 — Lofty (@ravenslofty)

Reply/reference

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and this is a project template, not the librelane settings.
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message-1446536581900140606

2025-12-05T16:19:56.475+00:00 — Lofty (@ravenslofty)

Content

:p
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message-1446536780357570743

2025-12-05T16:20:43.791+00:00 — asic destroyer (@logic_destroyer)

Content

The config.yaml is embedded in the template, and everything else is derived from it.
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message-1446536808023326803

2025-12-05T16:20:50.387+00:00 — Lofty (@ravenslofty)

Content

yes.
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message-1446536849882484747

2025-12-05T16:21:00.367+00:00 — Lofty (@ravenslofty)

Content

but you said you are changing some settings
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message-1446536874960359495

2025-12-05T16:21:06.346+00:00 — Lofty (@ravenslofty)

Content

what are the settings you are changing
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message-1446537313978159254

2025-12-05T16:22:51.016+00:00 — asic destroyer (@logic_destroyer)

Content

I just wanted to ask whether rebuilding from stage 0 could change the Yosys synthesis semantics, but you said it wouldn’t.
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message-1446537424162525234

2025-12-05T16:23:17.286+00:00 — Lofty (@ravenslofty)

Content

assuming the input is the same, it won't
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message-1446537463232200766

2025-12-05T16:23:26.601+00:00 — asic destroyer (@logic_destroyer)

Content

thank you
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message-1446537909200228392

2025-12-05T16:25:12.928+00:00 — asic destroyer (@logic_destroyer)

Content

It could be that nothing in the behavioral code changed, yet the synthesis still comes out differently (when buggy)  after many runs.
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message-1446773958568575108

2025-12-06T08:03:11.483+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I believe Yosys **should** be deterministic / reproducible, same input produces the same output. I don't know if anyone is validating / checking that aspect and it is really easily to make output of tools like Yosys non-deterministic/reproducible. https://reproducible-builds.org/ goes through a lot of what it takes to make things reproducible.

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message-1446774344079507466

2025-12-06T08:04:43.396+00:00 — tnt (@246tnt)

Content

It's been a while since I checked, but it was deterministic on the same platform / same binary. ( i.e. if you run it twice ). But if you run on different platforms, it might not be. ( And then of course different version could produce different results obviously ).

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message-1446776059159904277

2025-12-06T08:11:32.303+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

If someone (or a CI system) isn't paying attention to it, these things sadly seem to drift 🙁

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message-1446794125197447188

2025-12-06T09:23:19.582+00:00 — asic destroyer (@logic_destroyer)

Content

normal @Tim 'mithro' Ansell  @Leo Moser (mole99) ?
How long is it expected to take? I have the latest versions of all three repositories (gf180mcu PDK, template, and checker) from Git.

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message-1446924107475058910

2025-12-06T17:59:49.772+00:00 — BreakingTaps (@polyfractal)

Content

the whole precheck takes about 4hrs on my build server atm (Ryzen 9950x3d, about the fastest I could rent on short notice)

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message-1446924830111961251

2025-12-06T18:02:42.062+00:00 — urish

Content

Takes 4:30 to 5 hours for Tiny Tapeout on GitHub actions, e.g. a fresh one from today: <https://github.com/TinyTapeout/tinytapeout-gf-0p2/actions/runs/19984611269>

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message-1446928927678398475

2025-12-06T18:18:58.998+00:00 — tnt (@246tnt)

Content

If you have the RAM, running magic DRC / KLayout DRC / KLayout antenna in parallel can shorten that.

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message-1446957224999125274

2025-12-06T20:11:25.605+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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how?
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message-1446957372735226097

2025-12-06T20:12:00.828+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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how to rent, where?
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message-1446957757004648498

2025-12-06T20:13:32.445+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

I'm using OVH and their "Gaming" dedicated bare metal servers: https://us.ovhcloud.com/bare-metal/

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message-1446958907749826671

2025-12-06T20:18:06.804+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

by make librelane-magicdrc, make librelane-klayoutdrc? How antenna (inside DRCs)?
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message-1446964963246608628

2025-12-06T20:42:10.547+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Update Time!
The PDK has been updated with changes to the KLayout antenna script.

- PDK [1.4.4](https://github.com/wafer-space/gf180mcu/releases/tag/1.4.4)
  - Skip certain checks in the KLayout antenna script if corresponding layers are empty. Correctly check the top metal layer. (thanks @Egor Lukyanchenko!)
  - Don't consider dummy metal in the KLayout antenna script (already handled by the DRC rules).
  - *Actually* check for both P/N-type diodes in the KLayout antenna script. (thanks again @tnt!)

Please make sure to update:

- Project template [1.2.5](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.2.5)
- Precheck [1.4.3](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.4.3)
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message-1446965026412953771

2025-12-06T20:42:25.607+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.

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message-1447077465296998421

2025-12-07T04:09:13.126+00:00 — Noritsuna Imamura (@noritsunaimamura)

Reply/reference

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Content

There were thousands of antenna errors and CUP errors, but the fixes have been completed successfully.
All Green in "Precheck 1.4.3"!

- Fixed antenna and CUP errors in PDK 1.4.4.
- Replaced the frame with the "template 1.2.5" base generated by the "make librelane-padring".
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/raw/main/images/precheck_7th_OK.png

- GDS
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/blob/main/gds/ISHI-KAI_WS_RUN1.zip

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message-1447118940114260030

2025-12-07T06:54:01.493+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Great!

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message-1447147175594295433

2025-12-07T08:46:13.356+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Started a thread.
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message-1448086720510824458

2025-12-09T22:59:38.32+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 @everyone Important Update!

This update introduces a reworked filler generation that complies with several rules that the foundry did not allow us to waive. This may result in your design not meeting the necessary metal density requirements. Therefore, an option has been added to the filler generation script which enables the dummy fill shapes to be moved to the active metal layer, in order to allow some of these very restrictive rules to be ignored.
This option is enabled by default for the Metal2 layer in the project template, as this layer is most likely to be under the minimum density limit for digital designs.

Additionally, the antenna script has been updated to correctly verify the antenna rules according to the PDK docs. Previously, the check did not take the diode area into account correctly. Thanks to @tnt for identifying the issue and to @Egor Lukyanchenko for providing an updated KLayout implementation.

Furthermore, another issue was discovered in the antenna script.
Similar to the DRC deck, the comp layer needs to be cut by the poly gate to prevent shorts in the extracted netlist. This was less obvious than in the DRC deck, since the antenna check starts with the lower layers and progresses to the upper layers. It is expected for the check to get progressively slower - but not to this extent!
The antenna check should now finish in reasonable time, even for very complex designs.
(Previously, one design with a lot of combinatorial logic timed out on the online platform. Now the antenna check for this design completes in 13.7 minutes on my machine.)

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message-1448086732024184965

2025-12-09T22:59:41.065+00:00 — Leo Moser (mole99) (@mole99)

Content

- PDK [1.6.3](https://github.com/wafer-space/gf180mcu/releases/tag/1.6.1)
  - Correctly implement antenna checks based on `ANTENNADIFFSIDEAREARATIO`.
  - Fix shorts in the antenna connectivity setup.
  - Update the magic tech file from open_pdks.
  - Filler generation:
    - Comply with DPF.12, DPF.13, DM.4_DM.6, DM.5_DM.7 and DPF.1.
    - Add option to the filler generation to move a dummy metal layer to active metal and ignore DM.4_DM.6 and DM.5_DM.7.

- Project template [1.3.0](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.3.0)
  - Update the LibreLane branch.
  - Enable active dummy fill for Metal2 layer.

- Precheck [1.5.0](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.5.0)
  - Update the LibreLane branch.

Please make sure to update the wafer.space logo in the template repo, as its shapes have been copied to all metal layers to make it easier to meet the global density requirements.

Note: If your design passes the latest precheck, it is eligible for tapeout.

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message-1448086780187246864

2025-12-09T22:59:52.548+00:00 — Leo Moser (mole99) (@mole99)

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message-1448086818032455733

2025-12-09T23:00:01.571+00:00 — Leo Moser (mole99) (@mole99)

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message-1448087950351929504

2025-12-09T23:04:31.537+00:00 — BreakingTaps (@polyfractal)

Content

Since this affects dummy fill well after synthesis/routing/etc and the rest is DRC/antenna checks, I assume we can restart the build process later down the line? Do you happen to know at what step we should restart it?
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message-1448089689599901787

2025-12-09T23:11:26.206+00:00 — Leo Moser (mole99) (@mole99)

Content

It's probably best to start from the beginning of the flow. The manual macro placement comes right after synthesis, so there isn't much gained.
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message-1448090728184938639

2025-12-09T23:15:33.824+00:00 — BreakingTaps (@polyfractal)

Content

ah ok. will do, thanks!
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message-1448092044118724732

2025-12-09T23:20:47.567+00:00 — BreakingTaps (@polyfractal)

Content

followup question: if we have art in the corners similar to the ID/WS logo, shoudl we also copy it to all the metal layers? or only needed if the dummy fill generation struggles for some reason?
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message-1448092147265048657

2025-12-09T23:21:12.159+00:00 — Buck (@buck_042)

Content

Previously, when we used the analog-style top integration, we ran the fill step with
klayout -b -zz -r ${PDK_ROOT}/${PDK}/libs.tech/klayout/tech/drc/filler_generation/fill_all.rb -rd input=chip_top.gds -rd output=chip_top_filled.gds.

Now that the filler scripts have been updated, could you please let me know whether this command should also be updated (for example, by adding any additional options)? Thanks!
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message-1448103171321757706

2025-12-10T00:05:00.499+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Leo Moser (mole99) - Any idea?
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message-1448184728413802610

2025-12-10T05:29:05.225+00:00 — BreakingTaps (@polyfractal)

Content

> 973618 KLayout DRC errors found.

oh lawdy
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message-1448184867035811900

2025-12-10T05:29:38.275+00:00 — BreakingTaps (@polyfractal)

Content

i'm hoping I didn't update the repo correctly or something 😅

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message-1448187267905753281

2025-12-10T05:39:10.687+00:00 — BreakingTaps (@polyfractal)

Content

hmm, I was hopeful config.yaml merged without the new `Metal2_active` or accidentally left in `COMP_fill_cell` / `Poly2_fill_cell`... but no, that merged cleanly
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message-1448187706982010890

2025-12-10T05:40:55.371+00:00 — Trevor Peyton (@trev5514)

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Wow, on my beefy CPU, I was at 2 days total, roughly 1 day 16 hours alone on the antenna check. I updated to this and it finished within 12 minutes!

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message-1448189902629113937

2025-12-10T05:49:38.854+00:00 — Leo Moser (mole99) (@mole99)

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Sure, when I'm not asleep 😄
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message-1448190186449272992

2025-12-10T05:50:46.522+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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BTW What is your "beefy CPU"?
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message-1448190234184515634

2025-12-10T05:50:57.903+00:00 — Leo Moser (mole99) (@mole99)

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Yes, that would be to meet the global target density more easily. If you have no issue meeting it, then it's not necessary.
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message-1448190916429873202

2025-12-10T05:53:40.563+00:00 — Leo Moser (mole99) (@mole99)

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If you're making an analog design, you should be able to use the filler generation as is and still meet all density limits.
If you have problems meeting the density limit for one of the layers, you can pass `-rd Metaln_active` to the script, where n is the number of the metal layer. This moves the fill shapes to the active metal layer and thus ignores some of the dummy fill rules.
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message-1448191184294903889

2025-12-10T05:54:44.427+00:00 — Leo Moser (mole99) (@mole99)

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Did you also clone the latest PDK, not just update the tag? 😁
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message-1448191582997319792

2025-12-10T05:56:19.485+00:00 — BreakingTaps (@polyfractal)

Content

pretty sure I did! will redo all the steps just to be safe
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message-1448191835661930638

2025-12-10T05:57:19.725+00:00 — Trevor Peyton (@trev5514)

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"Relatively beefy" - for what I could afford at the time (2 years ago), not sure how it holds up now days!

13th Gen Intel(R) Core(TM) i7-13700K

My main computer (powerhouse) is an M1 max mac which the above CPU keeps up with nicely. With all the issues from librelane on mac, I loaded ubuntu onto the Intel chip and have been running pnr for my design on that. No issues since. I still use the mac for cocotb tb and everything else.
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message-1448208340214747196

2025-12-10T07:02:54.717+00:00 — tnt (@246tnt)

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@Leo Moser (mole99) Moving the filler to active should not be done during fill generation. It should be kept as a filler layer until the very end so you can run DRC with it as a filler metal except for those DF rules.
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message-1448208712668811264

2025-12-10T07:04:23.517+00:00 — tnt (@246tnt)

Content

And you can't just move say Metal2 anyway because if you move it to active, then you'll violate the rules for the Metal3 dummy so it's pretty much an all or nothing.
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message-1448214231185883187

2025-12-10T07:26:19.234+00:00 — Leo Moser (mole99) (@mole99)

Content

@tnt I see your point. However, I was considering the consequences of moving all dummy fill to active metal during the precheck. If we place the fill as dummy metal, but ignore DM.4_DM.6, DM.5_DM.7, we would need to remove these rules from the DRC deck.

This means, even designs where we don't need to use these exceptions (analog designs and the smaller slot sizes for digital designs) will have their dummy fill moved to active metal. I'm also not sure how happy GF will be about us circumventing these rules. Therefore, I thought it would be better to violate this rule on only one layer.

However, you're right. I'm seeing issues with the dummy fill on Metal3 that I didn't notice yesterday: it's getting placed on top of active Metal2.

I'll try to fix this and see if Metal3 can still meet density. If not we may need to resort to the all or nothing method.
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message-1448214396261236756

2025-12-10T07:26:58.591+00:00 — Leo Moser (mole99) (@mole99)

Content

@BreakingTaps This is the issue you're seeing. Sorry about that! I'll look into what went wrong.

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message-1448216671809441864

2025-12-10T07:36:01.124+00:00 — tnt (@246tnt)

Content

Ideally you'd have the option to ignore the distance to next/prev layers but still put them as dummy metal. And then another option in the DRC deck to ignore those rules, then as the last step of the hardening process, move them from `filler` to `drawing` and then run the full precheck on that.

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message-1448217004094783558

2025-12-10T07:37:20.347+00:00 — RebelMike (@rebelmike)

Content

I guess an ideal solution would be, per layer, to add dummy fill as normal first, and then if the min density isn’t met add as little active metal as possible to meet the density requirement. That would then tend not to be so much that the dummy fill on the layer above is too blocked.

Maybe that could be achieved by only converting some of the dummy to active during fill generation for each layer?
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message-1448217504303550535

2025-12-10T07:39:19.606+00:00 — tnt (@246tnt)

Content

Thing is if you add active on one layer, you now need to remove filler above/below it if you want to meet that rule ..
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message-1448218530481836093

2025-12-10T07:43:24.266+00:00 — urish

Content

Let's think like a smart LLM.

Instead of solving the actual problem, we'll simply write a script that will delete the problematic rule  from the calibre deck. Then find a vulnerability in calibre that will allow code execution. Run this script. Problem solved!

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message-1448219899619971143

2025-12-10T07:48:50.694+00:00 — tnt (@246tnt)

Content

I was more thinking like ... add some solid `Metal2.drawing` between the bond pads.
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message-1448219972814770187

2025-12-10T07:49:08.145+00:00 — tnt (@246tnt)

Content

Tons of area far from everything that matters ...
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message-1448223125157449728

2025-12-10T08:01:39.722+00:00 — Leo Moser (mole99) (@mole99)

Content

Alright, I found the issue in the filler script. The top-level filler cells were only added to the layout once they had been generated for all layers. This means that subsequent layers did not consider previous ones (which was fine when it all was dummy metal).

By using `start_changes()` and `end_changes()` I can add the top-level filler cells before generating the actual fill. This allows each fill layer to consider the previous one. However, it does not allow to consider the subsequent layer, i.e. if you generate dummy metal on Metal2, you would need to consider this when placing active Metal3. Therefore, fill would need to be done in two passes: first generate the active metal fill for some layers, then generate the dummy metal fill for the other layers. But yeah, it would prevent fill on the layers above and below the active fill, so not a solution anyways...
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message-1448223411196133428

2025-12-10T08:02:47.919+00:00 — Leo Moser (mole99) (@mole99)

Content

The truly general solution is to ignore DM.4_DM.6 and DM.5_DM.7 when generating the dummy fill, and to move these shapes to active metal during the precheck.

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message-1448258350910537728

2025-12-10T10:21:38.196+00:00 — Leo Moser (mole99) (@mole99)

Content

@everyone Filler Generation Hotfix!

Yesterday's update to the filler generation did not work as expected. Sorry about that!

The new approach is to keep the metal fill as dummy metal until the submission. The precheck will then move the dummy metal shapes to active metal.
This allows us to ignore the previous/subsequent dummy metal rules, which are disabled by default for Metal2 in the project template.

- PDK [1.6.4](https://github.com/wafer-space/gf180mcu/releases/tag/1.6.4)
  - Keep fill on dummy metal layers.
  - Rename option to `Metaln_ignore_active`.

- Project template [1.3.1](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.3.1)
  - Update the PDK and use the new filler option for Metal2.

- Precheck [1.5.1](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.5.1)
  - Move dummy metal shapes to active metal.

Please update your projects and clone the latest PDK.
Should any issues arise during this process, please let us know.
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message-1448258377636511758

2025-12-10T10:21:44.568+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1448290396244545740

2025-12-10T12:28:58.399+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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message-1448298480618438687

2025-12-10T13:01:05.864+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

How much do you want to bet that when GF itself runs fill generation, that they just fill all layers and don't run DRC afterwards?

It would be instructive and maybe helpful in the long term to get photos of one of the original GF open MPW runs, etching the surface away to get a view of each metal layer's fill pattern.  Then we will either come to an understanding of what GF actually does to get correct fill density without violating their own rules, or we'll have evidence to go back to them and insist that they change their rules.
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message-1448299091149979658

2025-12-10T13:03:31.426+00:00 — Tholin (@tholin)

Content

Tim Ansell has a bunch of raw dies from me, ready for destructive testing

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message-1448299301708238971

2025-12-10T13:04:21.627+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Leo Moser (mole99) :  The implication of the "new approach" is that the previous simple fill pattern generation works correctly with the new method.  So if we submitted something with the original fill pattern generation, do we need to do anything other than re-run precheck?  Is there even a way on the server to simply re-run the precheck without doing a new upload?
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message-1448301834182590505

2025-12-10T13:14:25.416+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes, if you have previously generated the fill pattern when these rules were completely ignored, you can submit your design, as all the dummy layers will be moved to active metal.

However, it might be better to only enable the exception for those layers that really need it :)
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message-1448301896237318225

2025-12-10T13:14:40.211+00:00 — Leo Moser (mole99) (@mole99)

Content

When it comes to the server, that's @Tim 'mithro' Ansell's domain.
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message-1448302389370163342

2025-12-10T13:16:37.783+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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There is a bunch of images at https://siliconpr0n.org/archive/doku.php?id=vendor:efabless&s[]=gf180mcu#master_page_list but I don't think we ever got as far as delayering
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message-1448302741930774539

2025-12-10T13:18:01.84+00:00 — Tholin (@tholin)

Content

Also no images from GFMPW-1 dies, which might've been different.
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message-1448304778114502727

2025-12-10T13:26:07.304+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

This looks like about the best image of fill patterns I can get from the GFMPW-0 photos.  It's hard to tell which layers are represented other than top metal.

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message-1448306013123117276

2025-12-10T13:31:01.753+00:00 — Leo Moser (mole99) (@mole99)

Content

There doesn't seem to be much fill at all next to the bondpads, but it should be allowed according to their rule. But then again, the density might already be achieved in that local area:

> 1. Check the metal density in an area of 200um by 200um at a step of 100um.
> 2. Add dummy metal if total die metal density is less than 30%

We don't do that, we fill globally and as much as we can.
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message-1448331655004684459

2025-12-10T15:12:55.254+00:00 — LukeW (@luke_w)

Reply/reference

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Content

Are the foundry 9-track cells DRC-clean with the latest changes to the DRC decks?
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message-1448332634387386510

2025-12-10T15:16:48.757+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

No, we would waive them in the online platform. The long term plan is to either adjust the GDS slightly or to add GDS-based rules to the magic tech file.

However, there were talks about making magic DRC errors not fail the precheck, which seems to be the likely way forward: https://discord.com/channels/1361349522684510449/1448059137593184366/1448295208683962420

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message-1448386150753505320

2025-12-10T18:49:28.053+00:00 — Trevor Peyton (@trev5514)

Content

I'm trying to work through my thousands of capacitance and slew violations all related to the pads. Does anyone know where OUTPUT_CAP_LOAD and MAX_CAPACITANCE_CONSTRAINT is defined? Also, I quickly looked through the IO lib files and noticed a max capacitance of 30 while MAX_CAPACITANCE_CONSTRAINT is set to  0.2. I'm assuming this is good for internal cells but is 0.2 correct for the pads and can it be relaxed? Has anyone gotten around the cap and slew violations?
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message-1448397073715302522

2025-12-10T19:32:52.29+00:00 — Tholin (@tholin)

Content

Submitting this to precheck. Wish me luck.

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message-1448413006445940847

2025-12-10T20:36:10.949+00:00 — digshadow

Content

I'm not really closely watching this, but if there is an image that you want let me know ASAP
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message-1448413039606104145

2025-12-10T20:36:18.855+00:00 — digshadow

Content

As I'm actively tearing down my lab right now for an indeterminate amount of time
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message-1448413953217790083

2025-12-10T20:39:56.677+00:00 — tnt (@246tnt)

Content

The block between the two large drawing has a tenuous link to power 😅   I guess at 5V the IR drop isn't all that big a deal but still, not sure if IR Drop stuff is properly setup in the default template.
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message-1448417440437371042

2025-12-10T20:53:48.095+00:00 — Tholin (@tholin)

Reply/reference

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Content

There isn’t actually a lot of standard cells in there. 10% density. Its the project multiplexer

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message-1448431165831909478

2025-12-10T21:48:20.484+00:00 — Tholin (@tholin)

Content

9 Magic DRC Errors
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message-1448431401966764062

2025-12-10T21:49:16.783+00:00 — Tholin (@tholin)

Content

I guess I can’t access the report right away.
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message-1448437138705223883

2025-12-10T22:12:04.528+00:00 — Tholin (@tholin)

Content

No idea how to run just the magic DRC checks locally.
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message-1448438521999392963

2025-12-10T22:17:34.331+00:00 — Tholin (@tholin)

Content

Actually, I believe I know which specific rule is being violated in KLayout. Can I run just that rule?
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message-1448478607763570872

2025-12-11T00:56:51.522+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - Coming to platform.wafer.space "real soon now"

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message-1448491726128808097

2025-12-11T01:48:59.184+00:00 — Tholin (@tholin)

Content

Passed magic DRC just now
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message-1448491815870140487

2025-12-11T01:49:20.58+00:00 — Tholin (@tholin)

Content

So I’m probably good
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message-1448504722204917800

2025-12-11T02:40:37.69+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - \o/
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message-1448666516110315551

2025-12-11T13:23:32.363+00:00 — Tholin (@tholin)

Content

I ran the full KLayout DRC locally and got hit with a 500 megabyte DRC report file with millions of dummy metal violations, but I didn’t get these on the online precheck?
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message-1448666649971396709

2025-12-11T13:24:04.278+00:00 — Tholin (@tholin)

Content

Actually crashed my text editor
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message-1448667124179402773

2025-12-11T13:25:57.338+00:00 — tnt (@246tnt)

Content

The default template now ignores one of the DRC rule when generating fill because it's basically impossible to meet density and full fill that rule ...
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message-1448667175991771156

2025-12-11T13:26:09.691+00:00 — tnt (@246tnt)

Content

The DRC deck has some option IIRC to now disable that part of the deck.
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message-1448667796337590384

2025-12-11T13:28:37.593+00:00 — Tholin (@tholin)

Content

Yeah, I now. I saw and was like "why is this disabled? curious!"
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message-1448667803551928402

2025-12-11T13:28:39.313+00:00 — Tholin (@tholin)

Content

So I tried it
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message-1448667825186275399

2025-12-11T13:28:44.471+00:00 — Tholin (@tholin)

Content

Mistakes were made
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message-1448667862494347306

2025-12-11T13:28:53.366+00:00 — Tholin (@tholin)

Content

I lost some unsaved changes in that text editor
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message-1448668043872960604

2025-12-11T13:29:36.61+00:00 — Tholin (@tholin)

Content

I assume the fab waived this?
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message-1448669328353529856

2025-12-11T13:34:42.854+00:00 — tnt (@246tnt)

Content

Nope
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message-1448669598135357544

2025-12-11T13:35:47.175+00:00 — tnt (@246tnt)

Content

waferspace will copy the "fill" shape to the "drawing" layer before submission to fab and cross their finger the fab doesn't complain about it.
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message-1448670324915699743

2025-12-11T13:38:40.453+00:00 — Tholin (@tholin)

Content

Is this done during precheck and DRC checked?
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message-1448672497498062918

2025-12-11T13:47:18.437+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes
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message-1448675610242056334

2025-12-11T13:59:40.573+00:00 — Tholin (@tholin)

Content

Very good. Then I have not observed any issues with this yet.
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message-1448675707294187651

2025-12-11T14:00:03.712+00:00 — Tholin (@tholin)

Content

With how large the dummy block areas around my art blocks are, I was worried about not meeting density requirements, but it appears I’m all good.
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message-1448745383189544960

2025-12-11T18:36:55.74+00:00 — Tholin (@tholin)

Content

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message-1448745463749672970

2025-12-11T18:37:14.947+00:00 — Tholin (@tholin)

Content

I had to manually edit out some DRC errors in KLayout, but its all good to go now!
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message-1448745562806423744

2025-12-11T18:37:38.564+00:00 — Tholin (@tholin)

Content

So, does that mean I can finally click this?

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message-1448771278264860692

2025-12-11T20:19:49.607+00:00 — Trevor Peyton (@trev5514)

Content

I'm getting this: `Required PDK variable 'DPL_CELL_PADDING' did not get a specified value. This PDK may be incompatible with your flow` while trying to run the make `librelane-openroad` (launching openroad). I'm not sure if it's something I did, and I'm looking around, but I did just update the PDK. Does anyone else have this issue on the latest pdk update?
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message-1448784181407514842

2025-12-11T21:11:05.956+00:00 — asic destroyer (@logic_destroyer)

Content

@Tim 'mithro' Ansell @Leo Moser (mole99) should I?

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message-1448785199830794311

2025-12-11T21:15:08.767+00:00 — Tholin (@tholin)

Content

I made another thing real quick. I doubt its gonna get fabbed during this run. But after the logo, there was still plenty of space in the margins for logic, so I put the wafer.space screensaver VGA demo that got submitted to TT. Felt appropriate.

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message-1448804302897414226

2025-12-11T22:31:03.293+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

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message-1448840968156614809

2025-12-12T00:56:44.972+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  I'm not allowed to change my own project description?  My project description changed slightly with the last submission, but "Edit" does not allow me to edit that description.  I can see locking it after the chip has been submitted for manufacture, but not before.
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message-1448877673492516985

2025-12-12T03:22:36.206+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - What happens when you try to edit the description?
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message-1448881110871441571

2025-12-12T03:36:15.741+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  I can't.  There's no option to do so.
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message-1448881608420753438

2025-12-12T03:38:14.366+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Can you send me a screenshot of the project page? Do you see a blue edit button in the "Project Details" section?
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message-1448883040607801547

2025-12-12T03:43:55.826+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

There's an Edit button, but when I click on it, the options to edit are limited.  Just a public/private checkbox, URL, and license (if I recall correctly---Not at my desk now).
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message-1448902518108196906

2025-12-12T05:01:19.624+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

The description and project title should be on that edit page.
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message-1448983032177492092

2025-12-12T10:21:15.674+00:00 — Greg (@greg.hashtag.9468)

Content

I noticed that too. descriptions don't appear on the edit page..
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message-1448983076112699474

2025-12-12T10:21:26.149+00:00 — Greg (@greg.hashtag.9468)

Content

Attachments

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message-1448984164610347049

2025-12-12T10:25:45.667+00:00 — Tholin (@tholin)

Content

Can’t create a new project either, which I guess makes sense. I just wanted to see if the wafer.space logo die passes prechecks, since DRC struggles with art that big.
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message-1449020740451041404

2025-12-12T12:51:06.027+00:00 — Tholin (@tholin)

Content

Tip: start writing your documentation ASAP. I am a handful of paragraphs into writing mine and I already discovered and fixed two bugs in my designs.

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message-1449038181843468369

2025-12-12T14:00:24.379+00:00 — Tim Edwards (@rtimothyedwards_19428)

Reply/reference

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I see what Greg showed in the screenshot.  No editable title, no editable description.
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message-1449067891721764936

2025-12-12T15:58:27.766+00:00 — asic destroyer (@logic_destroyer)

Content

I was able to edit all fields
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message-1449136684519133184

2025-12-12T20:31:49.247+00:00 — Tim Edwards (@rtimothyedwards_19428)

Reply/reference

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Really?  What does the edit page for "Project Details" look like for you?
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message-1449138030479802390

2025-12-12T20:37:10.149+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Leo Moser (mole99) :  I'm getting antenna violations on I/O pins.  The I/O pins are on the 3.3V set and I may be seeing violations which others don't see because the 3.3V transistors at the input are smaller and so the ratio is easier to exceed (plus the ratio was only slightly above 400).  The problem is that these pins _are_ connected to antenna diodes.  They have a (to me) weird configuration in which the signal is connected to the nwell of an nwell-to-pdiff diode.  But it is still a valid diode.  But klayout reports zero diode area for the net.
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message-1449139685115957282

2025-12-12T20:43:44.645+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Leo Moser (mole99) :  Also, I am getting nearly no metal2 fill inside the core area of the chip.  This sounds like the issue everyone was having before the latest implementation.  But I'm supposed to be using the latest fill.  How do I know if the fill pattern generator is current?
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message-1449145656727048315

2025-12-12T21:07:28.388+00:00 — Leo Moser (mole99) (@mole99)

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Thanks for the report @Tim Edwards, I can take a look tomorrow.
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message-1449145737827975258

2025-12-12T21:07:47.724+00:00 — Leo Moser (mole99) (@mole99)

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You need to explicitly allow the metal fill to ignore the active metal below/above it. The project template sets this in the LibreLane config, however, if you run fill manually then you need to pass the following: `-rd Metal2_ignore_active`
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message-1449146090359226551

2025-12-12T21:09:11.774+00:00 — Tim Edwards (@rtimothyedwards_19428)

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Thanks.  Somehow my SRAM test chip worked without it, probably because of all the blank space.

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message-1449147447606640720

2025-12-12T21:14:35.367+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  I confirmed the issue of not being able to edit the title or description of the project using Chrome, so it's not browser-specific.  That was the first time I had logged into wafer.space on that computer, so it isn't cookie-specific, either.
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message-1449149036719378566

2025-12-12T21:20:54.241+00:00 — asic destroyer (@logic_destroyer)

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Sorry! My fault!
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message-1449180648500756604

2025-12-12T23:26:31.077+00:00 — Tim 'mithro' Ansell (@mithro_)

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You should still be able to create projects - Issue reported @ https://github.com/wafer-space/platform.wafer.space/issues/218

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message-1449180816939946026

2025-12-12T23:27:11.236+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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(and @Greg) - Bug reported @ https://github.com/wafer-space/platform.wafer.space/issues/217

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message-1449181196717265161

2025-12-12T23:28:41.782+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Greg - I started having Claude Code work on trying to do tiles with just SRAM - https://github.com/mithro/gf180mcu-sram-forge and the output repos -> https://github.com/mithro?tab=repositories&q=gf180mcu-ic&type=&language=&sort=

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message-1449189293217153255

2025-12-13T00:00:52.138+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Seems like the project creation and project title/description problems are somewhat related.
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message-1449193145190580336

2025-12-13T00:16:10.52+00:00 — BreakingTaps (@polyfractal)

Content

oh! I didn't know you could put multiple instances in one macro block in the tcl stuff: https://github.com/mithro/gf180mcu-ic-1x1-sram-u8b24k/blob/main/librelane/pdn_cfg.tcl#L177

i dumbly repeated the _grid,_connect, and _stripe stuff for each macro block 🤦‍♂️
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message-1449193462766243840

2025-12-13T00:17:26.236+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Be careful, the AI might have hallucinated it can do that 😛

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message-1449193520303964210

2025-12-13T00:17:39.954+00:00 — BreakingTaps (@polyfractal)

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oh haha
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message-1449193549299056702

2025-12-13T00:17:46.867+00:00 — BreakingTaps (@polyfractal)

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😄

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message-1449197149291151441

2025-12-13T00:32:05.172+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Although if an AI hallucinates an API, that has been a good indicator that maybe that API ***should*** actually exist.

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message-1449201067274272799

2025-12-13T00:47:39.292+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell : "Users are reporting being unable to edit their project title. . . They do appear for staff users"---Quick solution:  Make everybody part of the staff!  Then you can also promote how quickly your company has grown!

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message-1449201472670797874

2025-12-13T00:49:15.946+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

As the only investor in this company is me, I doubt they will be convinced 😉

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message-1449212275939348490

2025-12-13T01:32:11.646+00:00 — Greg (@greg.hashtag.9468)

Reply/reference

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Content

The instance name does not have to be complete. I used `u_sram` in my pdn.tcl

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message-1449212489719091280

2025-12-13T01:33:02.615+00:00 — Greg (@greg.hashtag.9468)

Content

https://github.com/gregdavill/gf180mcu-racquet/blob/develop/librelane/pdn_cfg.tcl#L200
Which matches all the `u_chip_core.gen_proc_wrapper[<instance_number>].u_proc_wrapper.u_sram` blocks

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message-1449212951335800974

2025-12-13T01:34:52.673+00:00 — Greg (@greg.hashtag.9468)

Content

I was having a hard time working out the voodoo incantation to match both placement in the .yaml, and pdn config. tcl doesn't seem to like `[` `]`, but escaping them stopped them matching anything 🙃
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message-1449233872540799088

2025-12-13T02:58:00.677+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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The issues should be fixed in an hour or two.

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message-1449325945197432947

2025-12-13T09:03:52.509+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin / @Tim Edwards - The fix for the project creation and project edit has been deployed.

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message-1449407636817580225

2025-12-13T14:28:29.309+00:00 — Tholin (@tholin)

Content

Submitted the die with the wafer.space logo to precheck and I’m expecting it to succeed. If you end up fabbing it, feel free to use it for all the marketing purposes. Its all yours.
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message-1449428627992350852

2025-12-13T15:51:53.995+00:00 — Tholin (@tholin)

Content

Clean & submitted

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message-1449585569918095360

2025-12-14T02:15:31.866+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Thank you so much!
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message-1449586724584816831

2025-12-14T02:20:07.16+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - Some kinda related terrible ideas:
 * There was a bunch of discussion around seeing if we could make the silicon be something like really bad/inefficient infrared LEDs due to silicon being mostly transparent to IR. (I think @Ethan Mahintorabi and @BreakingTaps where part of that discussion but might have it confused with being infrared sensors -- might have instead been @digshadow and bunnie?) -- I wonder if you could make a logo that glows? (or maybe the metal just blocks the light?) 😛
 * I wonder if you could make the logo be some type of capacitor or connected to the power rails so the logo does something 😛
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message-1449596602514804766

2025-12-14T02:59:22.242+00:00 — digshadow

Reply/reference

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Content

You can do 1060 nanometer fairly easily. Whether that's power efficient or useful is a different question
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message-1449596883428315332

2025-12-14T03:00:29.217+00:00 — digshadow

Content

I should be clear though, you can't easily do something that's visible to human eye without putting a coating on
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message-1449600634293846180

2025-12-14T03:15:23.493+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Glows in an Infrared camera would be fine....

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message-1449816127919100115

2025-12-14T17:31:41.177+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 One More Update!

No worries - if your design passed precheck before, it will pass precheck now, too.

This update makes magic DRC optional: magic DRC violations won't block the submission process.
This decision was made due to a number of false positive errors that can show up if you read in a layout in magic that was not generated by magic.
However, please note that you should still **closely verify** all magic DRC violations. If you have any doubts, or magic catches a DRC violation that KLayout does not, please let us know.

The other change is that the antenna check will also consider nwell-to-pcomp diodes. Previously, it only considered pcomp-to-nwell and nplus-to-substrate diodes.
These structures are found inside the foundry-provided I/O cells, so this change should help reduce antenna violations in some cases.

- PDK [1.6.5](https://github.com/wafer-space/gf180mcu/releases/tag/1.6.5)
- Project Template [1.3.3](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.3.3)
- Precheck [1.5.3](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.5.3)

PS: Another reminder to submit your designs @ https://platform.wafer.space/ by [17th Dec @ 11:59pm AoE](https://discord.com/channels/1361349522684510449/1361349523724570938/1448290154966945936)❗
And please make sure to update your project description, visibility, license, and URL.
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message-1449816187323289743

2025-12-14T17:31:55.34+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.

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message-1449831550920167646

2025-12-14T18:32:58.307+00:00 — RebelMike (@rebelmike)

Content

Ah, just realised that the template doesn't fail the GitHub action if the GL test fails!
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message-1449833975949299732

2025-12-14T18:42:36.479+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Indeed, I guess there are cons & pros. It is useful in the sense that you get the GDS for inspection even if the test fails,  but easy to miss the failure
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message-1449834905965035620

2025-12-14T18:46:18.212+00:00 — RebelMike (@rebelmike)

Content

A failing action can still upload artifacts - think I would prefer it to fail but still give you GDS.  It would also be nice to upload the final netlist as an artifact so you could then run GL tests locally.  Fortunately my test fail was just a setup issue I'd introduced at some point, looks like all is good (not that my tests actually test much - I've had very limited time to work on this - hoping that the fact it's basically the same as the Tiny Tapeout version of TinyQV will save me!)

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message-1449864649846690053

2025-12-14T20:44:29.706+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks Mike, that's good feedback. I'll look into it tomorrow.

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message-1449870888718696611

2025-12-14T21:09:17.169+00:00 — Noritsuna Imamura (@noritsunaimamura)

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I ran the new PDK and Precheck on the GDS where I had already submitted on platform.wafer.space, and it was successful.
Do I need to precheck this GDS again and submit it on the platform.wafer.space?
https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1/raw/main/images/precheck_9th_OK.png

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message-1450028663033561138

2025-12-15T07:36:13.497+00:00 — Leo Moser (mole99) (@mole99)

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Great! No, you don't need to resubmit your design.
If it passed the precheck previously, then it is fine.

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message-1450097393705156680

2025-12-15T12:09:20.166+00:00 — Simi (@simi150500)

Content

@Jonathan (JMU, Germany) and I (JKU, Austria) have just submitted our multi-project chip. 🎉
This tapeout has 13 different projects on it, coming from our students or from our research departments.
Some of our highlights are the game Tetris and a RISC-V CPU for our TinyWhisper project. And of course, our students are excited to tape their first chip. 🙌

The starting template has also been extended with some more Makefile targets to also build specific macros, copy important reports `copy-reports`, and copy & ZIP the GDS for submission `copy-gds`. There is also a Makefile target `build-all`, which enables everyone to simply clone the repo, install the `nix-shell`, execute `make build-all` in it, and the whole chip will be built submission-ready. Maybe this is useful for someone for future runs. Feel free to use it. 🙂

A big shoutout to @Leo Moser (mole99), who supported us during this journey. Another thanks to @Tholin and his project (https://github.com/AvalonSemiconductors/ws-submission-2025/), which served as a reference for using macros. Thanks @Tim 'mithro' Ansell and everyone else involved, for making this possible. 🙂

GitHub Repo: https://github.com/iic-jku/gf180mcu-jku-projects

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message-1450098645792723105

2025-12-15T12:14:18.687+00:00 — Tholin (@tholin)

Content

Not having reset overrides for non-selected projects is....a choice. Dynamic power consumption on gf180 is particularly high. You’re gonna have some HOT chips!

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message-1450139792510550180

2025-12-15T14:57:48.829+00:00 — Simi (@simi150500)

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Good catch. Thanks for pointing that out. Maybe we find some time to fix this. But probably not until the next run.
Anyway, only the smaller designs are connected to the MUX. The bigger designs are running simultaneously. Therefore, adding reset overrides probably won't significantly affect the chip temperature. It still would be pretty hot. 😅
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message-1450226544965324943

2025-12-15T20:42:32.226+00:00 — RebelMike (@rebelmike)

Content

I've just submitted TinyQV!  https://github.com/MichaelBell/ws01-tinyQV?tab=readme-ov-file#tinyqv-for-wafer-space-run-1

TinyQV is an RV32EC system on chip which I designed to work well within Tiny Tapeout's constraints.  Earlier in the year there was a competition where Tiny Tapeout contributors could submit compatible peripherals to be taped out as part of the ttsky25a shuttle.

This version is a slight tweak to the Tiny Tapeout version, with UART and audio broken out on extra pins to allow a bit more flexibility in how it can be used, and the ability to work standalone (without the aid of another microcontroller to bring up the flash and PSRAM chips).  There's also an SRAM macro providing some scratch memory.  There's much more that could be done with the extra pins, possibility of analog interfaces, and using more area - but I've been very tight on time since the Wafer Space announcement (I initially didn't expect to contribute because of this - thanks @Leo Moser (mole99) for encouraging me to take part!)

All the Tiny Tapeout competition winning peripherals are present, plus basic UART, SPI, PWM blocks.  Additionally there's a peripheral to interface with the Tiny Tapeout gamepad Pmod, a quickly hacked together change to my VGA display peripheral that should allow a 256x120 resolution video mode, and @ReJ aka Renaldas Zioma's AY-3-819x sound generator - so some retro style games should be possible.

Many thanks to @Tim 'mithro' Ansell and @Leo Moser (mole99) for offering to put TinyQV on the shuttle!  I have submitted quarter, half height and half width versions - they are all functionally identical, so use whichever one you have space for.

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message-1450273290701508709

2025-12-15T23:48:17.278+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Great to see all the submissions!
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message-1450460109481185292

2025-12-16T12:10:38.346+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Minor Update!

This update fixes a regression introduced in the previous update (sorry!).
If your precheck was clean with PDK version 1.6.4, it will be clean with the latest version as well.

- PDK [1.6.6](https://github.com/wafer-space/gf180mcu/releases/tag/1.6.6)
- Project Template [1.3.5](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.3.5)
- Precheck [1.5.4](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.5.4)

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message-1450460191014518835

2025-12-16T12:10:57.785+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1450534496658128978

2025-12-16T17:06:13.631+00:00 — Tholin (@tholin)

Content

I re-ran my top-level flow with the new PDK and got this NP.2 and PP.2 violation

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message-1450539736245600316

2025-12-16T17:27:02.846+00:00 — Tholin (@tholin)

Content

Check #111 on the platform
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message-1450557278552981727

2025-12-16T18:36:45.258+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Did you open an issue on GitHub? I haven't seen anything yet.

The update to the precheck only affected the antenna check. These issues are probably due to some bad RNG luck.

Are these violations from magic DRC or from KLayout DRC?
Did you verify that these violations are false positives?

If you want help with that issue on Discord, please create a post under #⁉️-questions.

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message-1450707792510976000

2025-12-17T04:34:50.582+00:00 — BreakingTaps (@polyfractal)

Content

ah ok, @Tim 'mithro' Ansell I think my precheck might actually be stuck this time. running for 10hr, but the resource usage checkpoints stop at 4 minutes. that tracks with the log timestamps too. Gonna restart it but wanted to drop a ping in case it's helpful for debugging or something

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message-1450708821029814302

2025-12-17T04:38:55.8+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Have you done that already?
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message-1450708912117514456

2025-12-17T04:39:17.517+00:00 — BreakingTaps (@polyfractal)

Content

yep just restarted it. seems to be crunching along nicely now 👍
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message-1450709097090384015

2025-12-17T04:40:01.618+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

There is suppose to be code which finds containers and checks which become orphaned
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message-1450709262308474994

2025-12-17T04:40:41.009+00:00 — BreakingTaps (@polyfractal)

Content

maybe got in a weird state since it was started right around the redeploy earlier?
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message-1450721703943471196

2025-12-17T05:30:07.326+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Yeah, the system "should" be self healing but I guess that isn't working
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message-1450850338226704394

2025-12-17T14:01:16.129+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Has anyone submitted since? My design I submitted this morning with this flow returned:

[Error]: Layer 'GUARD_RING_MK' is not used. wafers.space requires a seal ring (guard ring) around the die.
From the wesbite
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message-1451154623753748623

2025-12-18T10:10:23.452+00:00 — Tholin (@tholin)

Content

I can’t run GL anymore, so I guess no verification for me.
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message-1451154906366087289

2025-12-18T10:11:30.832+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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You break your graphics stack?
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message-1451154974468735130

2025-12-18T10:11:47.069+00:00 — Tholin (@tholin)

Content

Not that GL
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message-1451155199895802002

2025-12-18T10:12:40.815+00:00 — Tholin (@tholin)

Content

This one

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message-1451156342663544924

2025-12-18T10:17:13.272+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

``default_nettype wire`?
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message-1451156623618740276

2025-12-18T10:18:20.257+00:00 — Leo Moser (mole99) (@mole99)

Content

The stdcells require that to be set. The last statement even from a previous file is used.
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message-1451157823680413798

2025-12-18T10:23:06.374+00:00 — Tholin (@tholin)

Content

That is very annoying
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message-1451158722482016307

2025-12-18T10:26:40.665+00:00 — Leo Moser (mole99) (@mole99)

Content

That is Verilog. You should set `` `default_nettype none`` at the start of all your files and `` `default_nettype wire`` at the end.
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message-1451223555713925261

2025-12-18T14:44:18.112+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Verilog is the worst hardware description language except for all the others.

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message-1451312998646943975

2025-12-18T20:39:42.969+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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My mental model is -- "Verilog is to C" is as "VHDL is to Ada" is as "SystemVerilog is to C++".

That includes things like:
 * C is full of foot guns, people think it's a low level language and they know the direct mapping to hardware but don't realise all bets are off when a compiler is involved, etc.
 * C++ is a massive language which includes multiple other languages internally, every restricts their usage to some small subsection of the language -- but no one can agree what the right subsection is, etc.

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message-1451326320268021845

2025-12-18T21:32:39.091+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  "The UNIX-Hater's Handbook" (Simson Garfinkel, Danie Weise, and Steven Strassmann, IDG Books, 1994) is a great read, if a bit "over the top".  It has an entire chapter devoted to C++, with sections like "C++ is to C as Lung Cancer is to Lung".

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message-1451326599487160522

2025-12-18T21:33:45.662+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

"Q:  Where did the names "C" and "C++" come from?
 A:  They were grades."  ---Jerry Leichter
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message-1451378291670913044

2025-12-19T00:59:10.039+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - The thing I like about C++ people is they don't pretend they actually understand how it works, people like to /think/ they know what is happening with C code but are very frequently proven wrong.

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message-1451597254635950140

2025-12-19T15:29:14.878+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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I don’t have any issues with Verilog and find it quite pleasant to work with. SystemVerilog is, of course, even better.
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message-1451597431488647472

2025-12-19T15:29:57.043+00:00 — asic destroyer (@logic_destroyer)

Content

I started doing logic design in 2021.
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message-1451599108761718986

2025-12-19T15:36:36.936+00:00 — Lofty (@ravenslofty)

Reply/reference

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VHDL doesn't have an official synthesisable subset either, which doesn't help.

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message-1451686692850372804

2025-12-19T21:24:38.61+00:00 — Egor Lukyanchenko (@egorxe)

Reply/reference

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It had one, but I'm not sure if anyone actually adhered to it https://standards.ieee.org/ieee/1076.6/3466/

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message-1452720740154478738

2025-12-22T17:53:34.699+00:00 — BreakingTaps (@polyfractal)

Content

@Leo Moser (mole99) (not-important-question): I'm trying to familiarize myself with how LibreLane/OpenRoad works. In `gf180mcu/flows/chip.py` I see a list of steps that are executed for the whole flow. Then in `gf180mcu/steps/*` all the actual step processing logic and config/parameters lives, correct?

So when you add a `OpenROAD.Floorplan` step to `chip.py`, the corresponding logic is defined in the `Floorplan(OpenROADStep)` class residing in `steps/openroad.py`  Is that the gist of how it works?

context: was investigating adding an optional `rtl_macro_placer ` step to the flow  (ala https://github.com/librelane/librelane/issues/537).  Placing macros by hand was super tedious for me, and probably terrible layout performance 😅
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message-1452722103496347721

2025-12-22T17:58:59.745+00:00 — Lofty (@ravenslofty)

Reply/reference

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yes, that's roughly correct
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message-1452722159024603158

2025-12-22T17:59:12.984+00:00 — Lofty (@ravenslofty)

Content

but you don't need to dump your plugin into there
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message-1452722321210216569

2025-12-22T17:59:51.652+00:00 — Lofty (@ravenslofty)

Content

for example, I wanted to play around with openroad's `rmp` step
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message-1452722342789775421

2025-12-22T17:59:56.797+00:00 — Lofty (@ravenslofty)

Content

```python
from decimal import Decimal
import os
from typing import Literal, Optional, Tuple

from librelane.steps.openroad import Step, TclStep, OpenROADStep, CompositeStep, State, Variable, ViewsUpdate, MetricsUpdate, dpl_variables
from librelane.common import get_script_dir, process_list_file

@Step.factory.register()
class RMP(OpenROADStep):
    id = "OpenROAD.RMP"
    name = "Restructure RMP"
    version = "0.1.0"

    config_vars = OpenROADStep.config_vars + dpl_variables + [
        Variable(
            "RMP_CORNER",
            Optional[str],
            description="IPVT corner to use during restructure. If unspecified, the value for `DEFAULT_CORNER` from the PDK will be used.",
            default="max_ss_125C_4v50"
        ),
        Variable(
            "RMP_TARGET",
            Literal["timing", "area"],
            description="In area mode, the focus is area reduction, and timing may degrade. In delay mode, delay is likely reduced, but the area may increase",
            default="area",
        ),
        Variable(
            "RMP_SLACK_THRESHOLD",
            Optional[Decimal],
            description="Specifies a (setup) timing slack value below which timing paths need to be analyzed for restructuring",
            default=Decimal()
        ),
        Variable(
            "RMP_DEPTH_THRESHOLD",
            Optional[int],
            description="Specifies the path depth above which a timing path would be considered for restructuring",
        ),
    ]

    def get_script_path(self):
        return "~/gf180mcu-chess/restructure.tcl"

    def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
        self.config = self.config.copy(DEFAULT_CORNER=self.config["RMP_CORNER"])

        kwargs, env = self.extract_env(kwargs)
        lib_list = self.toolbox.filter_views(
            self.config, self.config["LIB"], timing_corner=self.config.get("RMP_CORNER")
        )

        excluded_cells: Set[str] = set(self.config["EXTRA_EXCLUDED_CELLS"] or [])
        excluded_cells.update(
            process_list_file(self.config["SYNTH_EXCLUDED_CELL_FILE"])
        )
        excluded_cells.update(process_list_file(self.config["PNR_EXCLUDED_CELL_FILE"]))
        trimmed_lib = self.toolbox.remove_cells_from_lib(
            frozenset([str(lib) for lib in lib_list]),
            excluded_cells=frozenset(excluded_cells),
        )

        env["_RMP_LIB"] = TclStep.value_to_tcl(trimmed_lib)
        env["_RMP_ABC_LOG"] = TclStep.value_to_tcl(
            os.path.join(self.step_dir, "abc.log")
        )
        env["RMP_CORNER"] = TclStep.value_to_tcl(self.config.get("RMP_CORNER"))
        return super().run(state_in, env=env, **kwargs)

@Step.factory.register()
class RMPPlus(CompositeStep):
    id = "OpenROAD.RMPPlus"
    Steps = [
        RMP,
        Step.factory.get("OpenROAD.GlobalPlacement"),
        Step.factory.get("OpenROAD.DetailedPlacement"),
        Step.factory.get("OpenROAD.GlobalRouting"),
    ]
```
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message-1452722970849185974

2025-12-22T18:02:26.538+00:00 — BreakingTaps (@polyfractal)

Content

ooh interesting. where do "user plugins" live in the project template, and how do you specify where the step is inserted into the standard chip flow? Might be missing it from skimming that code but I don't think I see how it slots into the flow? Or is it run as a standalone step?
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message-1452723173434065116

2025-12-22T18:03:14.838+00:00 — Lofty (@ravenslofty)

Reply/reference

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anything which is in `PYTHONPATH`, and which has a filename which begins with `librelane_plugin_`
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message-1452723210750525440

2025-12-22T18:03:23.735+00:00 — Lofty (@ravenslofty)

Content

(e.g. the above file is called `librelane_plugin_rmp.py`)
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message-1452723433967190087

2025-12-22T18:04:16.954+00:00 — Lofty (@ravenslofty)

Content

> how do you specify where the step is inserted into the standard chip flow?
same as any other step in the flow; you add it in `librelane/config.yaml` under `substituting_steps`.
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message-1452723649772785816

2025-12-22T18:05:08.406+00:00 — BreakingTaps (@polyfractal)

Content

oh! I didn't realize that's what the `substituting_steps` section was for (makes sense in retrospect). awesome, thank you!
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message-1452724105668333710

2025-12-22T18:06:57.1+00:00 — BreakingTaps (@polyfractal)

Content

so just to check my understanding, for your `rmp` you would have nulled out the `GlobalPlacement`, `DetailedPlacement` and `GlobalRouting` , then inserted your `RMP` to run (and which includes the others)?
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message-1452724811708108851

2025-12-22T18:09:45.433+00:00 — Lofty (@ravenslofty)

Reply/reference

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actually, the intent was to run those, and then `OpenROAD.RMPPlus` afterwards to try to use the information
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message-1452724844968935576

2025-12-22T18:09:53.363+00:00 — Lofty (@ravenslofty)

Content

||but RMP sucks, so it didn't help any||
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message-1452724874513485944

2025-12-22T18:10:00.407+00:00 — BreakingTaps (@polyfractal)

Content

hehe
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message-1452724890871271639

2025-12-22T18:10:04.307+00:00 — BreakingTaps (@polyfractal)

Content

gotcha 🙂 👍
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message-1452725400181412072

2025-12-22T18:12:05.736+00:00 — Lofty (@ravenslofty)

Content

I know it's quite insulting to call things like this *toys*, but having passes that have little documentation, only work in very specific situations and have crippling flaws, mixed in alongside the Serious Stuff for Serious People makes it confusing to know what to use
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message-1452725444884431099

2025-12-22T18:12:16.394+00:00 — Lofty (@ravenslofty)

Content

*cough*
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message-1452725449359753467

2025-12-22T18:12:17.461+00:00 — Lofty (@ravenslofty)

Content

anyway
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message-1452726084243292252

2025-12-22T18:14:48.829+00:00 — BreakingTaps (@polyfractal)

Content

state of documentation in general was a real hindrance to me personally (as a complete newbie). Even simple things, like is this parameter unitless? nanoseconds? percentage? who knows! 🙃

And even moreso for how parameters interact. optimizing was a lot of tweaking and seeing how it adjusted things
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message-1452726175091785952

2025-12-22T18:15:10.489+00:00 — BreakingTaps (@polyfractal)

Content

(not project template that is, Openroad/librelane)
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message-1452726459738226789

2025-12-22T18:16:18.354+00:00 — BreakingTaps (@polyfractal)

Content

that said I recognize docs are hard and no fun for OSS contributors 🙂
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message-1452726493125017620

2025-12-22T18:16:26.314+00:00 — Lofty (@ravenslofty)

Content

tbqh I have decided to do something very stupid in the hopes of improving gf180mcu performance :p
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message-1452726599081529395

2025-12-22T18:16:51.576+00:00 — BreakingTaps (@polyfractal)

Content

oh? any details to share or wait until the silicon is back?
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message-1452726790341660672

2025-12-22T18:17:37.176+00:00 — Lofty (@ravenslofty)

Content

you might be aware that tholin's been working on a new standard cell library
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message-1452727005345878098

2025-12-22T18:18:28.437+00:00 — Lofty (@ravenslofty)

Content

well, I've decided to make a new standard cell library too
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message-1452727066129727732

2025-12-22T18:18:42.929+00:00 — Lofty (@ravenslofty)

Content

except I'm going with domino logic
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message-1452727627923066881

2025-12-22T18:20:56.871+00:00 — BreakingTaps (@polyfractal)

Content

oooh neat! will have to do some reading on that, only passingly familiar
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message-1452729579113414698

2025-12-22T18:28:42.071+00:00 — BreakingTaps (@polyfractal)

Content

(had a quick refresher, very cool! can't wait to see how it turns out 🙂 )
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message-1452749380850421760

2025-12-22T19:47:23.173+00:00 — Lofty (@ravenslofty)

Content

so, admittedly, the tooling is not really set up for domino logic
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message-1452749504016289802

2025-12-22T19:47:52.538+00:00 — Lofty (@ravenslofty)

Content

but, I think there's a chicken-and-egg situation of "no open domino logic libraries, so why support domino logic in open tooling"
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message-1452749549742592121

2025-12-22T19:48:03.44+00:00 — Lofty (@ravenslofty)

Content

and so, a shitty domino logic library can pave the way for a good one :p
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message-1453328316105887987

2025-12-24T10:07:52.094+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lofty / @BreakingTaps - The more people we get using the tools, the better things like documentation will hopefully get.

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message-1453336311015674008

2025-12-24T10:39:38.229+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

Unfortunately more people using the tools might not pay Precision to add important things to OpenROAD...

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message-1453338933940326462

2025-12-24T10:50:03.583+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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The great thing is that it only takes a *few* people to pay Precision to add things.
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message-1453339005381906529

2025-12-24T10:50:20.616+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Most people don't pay to improve gcc or llvm

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message-1453425887772151979

2025-12-24T16:35:34.992+00:00 — BreakingTaps (@polyfractal)

Content

Who pays Precision currently? University grants? or maybe startups looking for extra support?
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message-1454664061592797235

2025-12-28T02:35:38.635+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Content

How did you enable ICG cells btw?
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message-1454667534828699784

2025-12-28T02:49:26.719+00:00 — nxmq99

Reply/reference

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Content

USE_LIGHTER will turn DFF Enables to ICGs
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message-1454667908713283807

2025-12-28T02:50:55.86+00:00 — BreakingTaps (@polyfractal)

Content

thanks!
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message-1455388246769930381

2025-12-30T02:33:17.836+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - A whole bunch of people pay them, for example Google pays them.
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message-1455388316890300537

2025-12-30T02:33:34.554+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - They have contracts with other groups that I'm not at liberty to share.
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message-1455388500240236604

2025-12-30T02:34:18.268+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - FWIW - Precision was *originally* paid by DARPA as part of the IDEA project.
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message-1455388612601446412

2025-12-30T02:34:45.057+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I believe there will also be an OpenROAD Foundation created at some point...
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message-1455608312845570192

2025-12-30T17:07:45.677+00:00 — BreakingTaps (@polyfractal)

Content

aha, interesting! didnt know they were part of that chronology
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message-1455608357963563028

2025-12-30T17:07:56.434+00:00 — BreakingTaps (@polyfractal)

Content

well i'm happy they are getting paid! doing good work it seems 🙂
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message-1455709419605197066

2025-12-30T23:49:31.407+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - If you know companies that want to pay them, I'm happy to set up an introduction! 🙂

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message-1456751082641293567

2026-01-02T20:48:43.228+00:00 — Ethan Mahintorabi (@ethanmahintorabi)

Content

Also just fyi Yosys has a clockgate command https://yosyshq.readthedocs.io/projects/yosys/en/0.46/cmd/clockgate.html
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message-1456751306126393591

2026-01-02T20:49:36.511+00:00 — Ethan Mahintorabi (@ethanmahintorabi)

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You need to run opt_dff before it to make sure all the flops are turned into enables and then you can use that command to convert some portion of them to clock gates
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message-1457667378111578278

2026-01-05T09:29:45.092+00:00 — Tholin (@tholin)

Content

What is the metal slot thing about? What are metal slots?
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message-1457668618656550975

2026-01-05T09:34:40.861+00:00 — tnt (@246tnt)

Content

You can't have any too large metal area.
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message-1457668891474923531

2026-01-05T09:35:45.906+00:00 — tnt (@246tnt)

Content

If you have a very large metal without "holes" and so the "solution" is to add elongated holes in it that are called "slots".
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message-1457668959263260752

2026-01-05T09:36:02.068+00:00 — Tholin (@tholin)

Content

That’s not gonna look good
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message-1457669113760714904

2026-01-05T09:36:38.903+00:00 — Tholin (@tholin)

Content

I am frustrated that so much is stacked against me putting art on my die and I’m tired of pretending I’m not
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message-1457669206152708228

2026-01-05T09:37:00.931+00:00 — Tholin (@tholin)

Content

I just don’t understand. This exact macro was fine during GFMPW, but now it needs slots?

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message-1457669281742454816

2026-01-05T09:37:18.953+00:00 — tnt (@246tnt)

Content

Well sorry to say but "art" isn't a primary target of the foundry 😅
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message-1457670050566770804

2026-01-05T09:40:22.255+00:00 — tnt (@246tnt)

Content

One solution is to not have a solid metal zone, but instead have "pixels" with a small gap between them. Or horizontal/vertical lines like scan lines. Looking at the die without magnification with the naked eye, it will still look solid and uniform (compared to random small slots in an otherwise solid plane).
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message-1457670568609583176

2026-01-05T09:42:25.766+00:00 — Tholin (@tholin)

Content

Both the Metal5 and Metal4 layers are visible visually. If the slots in Metal5 and Metal4 were horizontally offset from each other, it would look a little better.
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message-1457670905256874048

2026-01-05T09:43:46.029+00:00 — tnt (@246tnt)

Content

We had the same in tt-ihp 0p1

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message-1457671012333256817

2026-01-05T09:44:11.558+00:00 — Tholin (@tholin)

Content

😬
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message-1457673345276575950

2026-01-05T09:53:27.775+00:00 — tnt (@246tnt)

Content

Is that some modified GDS you got back from ws/gf btw ?
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message-1457674270518939802

2026-01-05T09:57:08.37+00:00 — Tholin (@tholin)

Content

Yes
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message-1457674296972283996

2026-01-05T09:57:14.677+00:00 — Tholin (@tholin)

Content

I downloaded it from the wafer.space platform
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message-1457687118989099028

2026-01-05T10:48:11.684+00:00 — tnt (@246tnt)

Content

@urish Did you check ? Do a xor with the submitted one ?
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message-1457688002347270231

2026-01-05T10:51:42.293+00:00 — urish

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Nope, wasn't aware that it would be modified
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message-1457711324724203610

2026-01-05T12:24:22.781+00:00 — urish

Reply/reference

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Started a thread.
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message-1457791813552443557

2026-01-05T17:44:12.813+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Only some projects had issues with metal slots. The project authors were contacted by email.
None of the Tiny Tapeout projects were affected.

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message-1467818006997372949

2026-02-02T09:44:43.608+00:00 — Egor Lukyanchenko (@egorxe)

Content

During the call I've mentioned my Caravel port to project template. In case it would be useful to someone for future designs, here it is: https://github.com/egorxe/gf180mcu-caravel-template

Embeds

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message-1471674281116041276

2026-02-13T01:08:11.004+00:00 — Mark Anderson (@markemer)

Reply/reference

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Content

Ah, Cheesing. We meet again.
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message-1482918666042347791

2026-03-16T01:49:21.281+00:00 — monkey on keyboard (@.monkeyonkeyboard.)

Content

heya, i noticed that magic and klayout have different DRC errors, and this is reproducible in the upstream template https://github.com/wafer-space/gf180mcu-project-template/actions/runs/22961298626/job/66652405640
```
3503
* DRC
Failed 𐄂
KLayout DRC errors: 0
Magic DRC errors: 126743
Check the report directories of KLayout.DRC and Magic.DRC.
```
is this an issue? do we trust klayout or magic?

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message-1482946676745437204

2026-03-16T03:40:39.553+00:00 — nmz787

Reply/reference

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In my experience at "corporate semiconductor", different tools reporting differently can either be real runset issues, or just differences in how they report errors
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message-1483013256057454798

2026-03-16T08:05:13.298+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1483027724929990736

2026-03-16T09:02:42.946+00:00 — nmz787

Content

I'm seeing a lot of warnings like `Error while reading cell "METAL1_FILL" (byte position 144857526): Warning: cell "Metal1_fill_cell" placed on top of itself.  Ignoring the extra one.` that I don't see in the github actions #55
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message-1483338263057137816

2026-03-17T05:36:41.005+00:00 — nmz787

Content

is there no layerprops/layermap in klayout format (usually lyp, I think)?
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message-1483339542906798092

2026-03-17T05:41:46.145+00:00 — nmz787

Content

ah i got it
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message-1483343882484711496

2026-03-17T05:59:00.781+00:00 — nmz787

Content

the seal ring is interesting, in that the vias are not drawn to be hermetic... I guess GF is swapping that part of the database after they tape-in
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message-1483360184406511716

2026-03-17T07:03:47.462+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

If you open the layout through librelane (`make librelane-klayout`), they layer map will already be loaded.
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message-1483360328845623326

2026-03-17T07:04:21.899+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

No, that's just the structure of the seal ring as specified by the [PDK documentation](https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_12_2.html).
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message-1483360476242116688

2026-03-17T07:04:57.041+00:00 — nmz787

Content

I am fairly positive the fab is swapping out the via layers under the sealring ID
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message-1483360503198646272

2026-03-17T07:05:03.468+00:00 — nmz787

Content

they are not hermetic as-is
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message-1483360546211364997

2026-03-17T07:05:13.723+00:00 — nmz787

Content

(Intel does this)
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message-1483360771965587456

2026-03-17T07:06:07.547+00:00 — nmz787

Content

in that case, depending on the node, they do or do not show the customer the real design... due to process churn and violating DRC
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message-1483361035221078207

2026-03-17T07:07:10.312+00:00 — nmz787

Content

unless they have some other very different way of ensuring hermeticity
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message-1483361515888312382

2026-03-17T07:09:04.912+00:00 — nmz787

Content

has anyone delayered one of these?
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message-1483361881778556980

2026-03-17T07:10:32.147+00:00 — Leo Moser (mole99) (@mole99)

Content

I can guarantee you, they don't - I saw the final mask data.

Why would they specify the exact placement of vias in the guard ring documentation **and** have custom DRC rules for them when they're going to replace it anyway?
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message-1483362825266270440

2026-03-17T07:14:17.092+00:00 — nmz787

Content

Intel does the same
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message-1483362914155888702

2026-03-17T07:14:38.285+00:00 — nmz787

Content

but cross-section and teardown show 100% continuous perimeter rings on every level, metal and via
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message-1483363475240648775

2026-03-17T07:16:52.058+00:00 — nmz787

Reply/reference

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Content

you saw post-OPC database?
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message-1483363517825552456

2026-03-17T07:17:02.211+00:00 — Leo Moser (mole99) (@mole99)

Content

yes
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message-1483363563098734744

2026-03-17T07:17:13.005+00:00 — nmz787

Content

including synthesized layers, etc?
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message-1483363781886087251

2026-03-17T07:18:05.168+00:00 — Leo Moser (mole99) (@mole99)

Content

The final mask data for the complete reticle, yes.
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message-1483363963436531844

2026-03-17T07:18:48.453+00:00 — nmz787

Content

huh, I feel like I'm missing something now
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message-1483365357707329708

2026-03-17T07:24:20.873+00:00 — nmz787

Content

GPT says there's orders of magnitude less risk of "moisture-induced Vt drift" for such a large planar process, hmm
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message-1483366714489176104

2026-03-17T07:29:44.355+00:00 — nmz787

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I suppose you have a point about PDK rules for vias... Intel doesn't have those, they supply X/Y/corner cells for customer to place
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message-1483406176820527156

2026-03-17T10:06:32.908+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

Reply/reference

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Don't know where you get the hermeticity requirement for the vias in the seal ring from ?
AFAIK main purpose of seal ring is to protect the design from cracks and stress caused by wafer sawing. This can be done with normal sized vias in a ring.
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message-1483488920061612184

2026-03-17T15:35:20.434+00:00 — nmz787

Reply/reference

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I am on team that owns seal ring collateral design. Crack arrest is only once function for us
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message-1483659304191000737

2026-03-18T02:52:23.176+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@nmz787 - This process is from the late 1990's / early 2000's -- I'm pretty things have changed a lot since then.
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message-1486728700518203616

2026-03-26T14:09:04.287+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Project Template Update!

Version 1.4.0 has been tagged, which includes an upgrade to LibreLane 3.0 🎉
Read the blog post to find out more about LibreLane 3.0: https://www.librelane.org/blog/2026-03-25-website_release_3-0

- Project Template [1.4.0](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.4.0)

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message-1486728757812396204

2026-03-26T14:09:17.947+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1487913391929430036

2026-03-29T20:36:36.73+00:00 — BreakingTaps (@polyfractal)

Content

kinda related, started to work on a dashboard to make my life easier in the next time I tape something out. right now it's mostly just spewing out the saved metrics, but I'd like it to be my centralized "build manager". Kick off new builds, "fork" existing builds with new settings, investigate performance and metrics, help manage ECO steps, comparisons, etc

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message-1487938216299331794

2026-03-29T22:15:15.321+00:00 — BreakingTaps (@polyfractal)

Content

as an aside, it's kinda tragic how OpenRoad is _close_ to being a nice set of modular tools... but then they baked it all into one binary and duct tape it all together with tcl and odb monstrosity 🙁
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message-1487940984460410980

2026-03-29T22:26:15.302+00:00 — Lofty (@ravenslofty)

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The problem they had was spending so much time serialising and deserialising information between commands.
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message-1487941544123039866

2026-03-29T22:28:28.736+00:00 — Lofty (@ravenslofty)

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Because it *was* a "nice set of modular tools" and it was completely unusable.
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message-1487942227182227526

2026-03-29T22:31:11.59+00:00 — BreakingTaps (@polyfractal)

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aha, interesting! i should do some more reading on the history/context so i'm less judgmental 🙂
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message-1487942238515232839

2026-03-29T22:31:14.292+00:00 — BreakingTaps (@polyfractal)

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You can battle serdes cost with mmap'ing zero-copy serialization though
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message-1487942444392906975

2026-03-29T22:32:03.377+00:00 — BreakingTaps (@polyfractal)

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(which isn't far from what odb is doing anyway from my understanding)
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message-1487942821859164294

2026-03-29T22:33:33.372+00:00 — Lofty (@ravenslofty)

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For the sake of a thought experiment, how would you imagine openroad should be split up?
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message-1487943617543934023

2026-03-29T22:36:43.078+00:00 — BreakingTaps (@polyfractal)

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well in a nice world where everything behaves, all the modules (rsz, gpl, ifp, tap, etc) would be individual tools that LibreLane can bolt together at will. and if you wanted to say develop a new rsz you just drop in your own version that speaks to the shared odb backend.

But right now if you wanted to do that you have to rebuild the whole thing. and the whole orchestration between librelane and openroad seems very fraught. python -> env variables -> tcl -> openroad binary and back

That said, I recognize it's not a nice world and most things don't behave as we'd like 🙂 so just grumping
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message-1487944792355635290

2026-03-29T22:41:23.175+00:00 — Lofty (@ravenslofty)

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Well, I would argue the most core part of openroad is actually sta, because everything needs to reference sta for timing calculations.

But there are a lot of rather intricate connections between the two; if you've ever looked at things like LL's `Odb.InsertECOBuffers`, it relies on being able to modify a pre-placed/routed netlist, insert netlist modifications, and then incrementally re-place and route only the new buffers, rather than ripping up the whole run and starting from scratch.
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message-1487946188928847972

2026-03-29T22:46:56.144+00:00 — BreakingTaps (@polyfractal)

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I haven't to be fair, will take a look! Good points about how intertwined things can be, and not so easy to "just" modularize everything
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message-1487947185705193665

2026-03-29T22:50:53.794+00:00 — Lofty (@ravenslofty)

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I did ask donn about this; there's a native python API for OR, but it's something of a second-class citizen to the main Tcl API, so it has missing things.

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message-1487952653999669339

2026-03-29T23:12:37.537+00:00 — Tim 'mithro' Ansell (@mithro_)

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My understanding is that multiple groups have been pushing for the Python API to be the first class citizen and the TCL API to be an afterthought - but I don't know the current state of that.
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message-1487953031357006006

2026-03-29T23:14:07.506+00:00 — Tim 'mithro' Ansell (@mithro_)

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The great thing about open source is that you can help fix them unlike with the proprietary tooling where groups like Google who are paying hundreds of millions can barely get anything fixed.
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message-1487954996627640430

2026-03-29T23:21:56.063+00:00 — BreakingTaps (@polyfractal)

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hehe part of my grumping is because I've been trying a few experiments, and in the process slowly working "down" the stack discovering how things work and how tightly coupled everything is 🙂
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message-1487973794529411175

2026-03-30T00:36:37.832+00:00 — BreakingTaps (@polyfractal)

Content

huh interestig bit in OpenSTA. What's the story around Parallax SW? Their website is quite bare (http://www.parallaxsw.com/)

> However, OpenSTA is not supported by a public community of developers as many other open source projects are. The copyright and development are exclusive to Parallax Software.

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message-1488072429531037726

2026-03-30T07:08:34.249+00:00 — tnt (@246tnt)

Content

Both TCL and python are swig generated bindings, it's not that hard to add things if something you need is missing, I had to go through it a couple of times. ( Although both times it was missing in both TCL and python, I think in general when adding things they try to add bindings for both at once to keep them in sync ).
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message-1488073083444269116

2026-03-30T07:11:10.154+00:00 — tnt (@246tnt)

Content

And yeah, in MPW1 times, OpenRoad was different tools ... and it was a nightmare 😅    I much prefer the current version.   AFAIU They need to pass quite a bit of info between tools to get good QoR, a lot of which doesn't "map" to standard format, so you ended up with needing the exact right combination of tools so they could talk properly to each other.
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message-1488362100102533202

2026-03-31T02:19:37.095+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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OpenSTA is used in a number of proprietary solutions. The full test suite for the tool is sadly closed source as well.
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message-1488598282493231246

2026-03-31T17:58:07.365+00:00 — BreakingTaps (@polyfractal)

Content

rude 😐
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message-1488598362100994071

2026-03-31T17:58:26.345+00:00 — BreakingTaps (@polyfractal)

Content

never heard of a closed test suite before. I guess maybe they have snippets / test cases from customers under NDA In there?
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message-1488700027798032505

2026-04-01T00:42:25.336+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Yeah, there are a bunch of NDA stuff in it if I understand correctly.
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message-1491138759574552786

2026-04-07T18:13:04.301+00:00 — Brian Swetland (@dnaltews)

Reply/reference

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sqlite has something along those lines (but not *only* that)
> The Test Harness #3 (TH3) is a suite of test cases for SQLite that provide 100% branch test coverage (and 100% modified condition/decision coverage) for the core SQLite in an as-deployed configuration using only published and documented interfaces. TH3 is designed for use with embedded devices, and is compatible with DO-178B. Every release of the public-domain SQLite is tested using TH3, and so all users benefit from the TH3 tests. But the TH3 tests are not themselves public. Hardware or system manufactures who want to have TH3 test run on their systems can negotiate a service agreement to have the SQLite Developers run those tests.
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message-1491476745604436109

2026-04-08T16:36:06.45+00:00 — BreakingTaps (@polyfractal)

Content

wow, TIL!
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message-1491896118169305222

2026-04-09T20:22:32.661+00:00 — Jason Yang (@.pogeg)

Content

In the project template, is there `slot_defines.svh` for maximum, all edges pin configuration variant?
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message-1491896238206091505

2026-04-09T20:23:01.28+00:00 — Jason Yang (@.pogeg)

Content

The slot_defines  in the template seems to be defined for the default configuration, which makes sense
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message-1492048817317740605

2026-04-10T06:29:18.975+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes, those are the default configurations for each slot.

You can try increasing the number of pads to see what fits. Make sure to update the [yaml config](https://github.com/wafer-space/gf180mcu-project-template/tree/main/librelane/slots) for your slot accordingly.

However, you need to consider both the minimum pitch of the bondpads and the capabilities of your PCB supplier.
This depends on the bonding service you are targeting and where you manufacture your PCB.

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message-1492363587631448266

2026-04-11T03:20:06.066+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I did an exploration of what IOs options might be possible at https://mithro.github.io/gf180mcu-project-template/
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message-1499416691644567613

2026-04-30T14:26:37.103+00:00 — Tholin (@tholin)

Content

@Leo Moser (mole99) Setting NUM_ANALOG_PADS to 0 doesn’t work in the project template. Might need to guard some lines with `if NUM_ANALOG_PADS != 0` (is that even valid syntax?)

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message-1499416857214587161

2026-04-30T14:27:16.578+00:00 — Tholin (@tholin)

Content

I think setting it to exactly 1 will also break since that generates `[0:0]`
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message-1499416922318573639

2026-04-30T14:27:32.1+00:00 — Tholin (@tholin)

Content

Same for all of them, actually, but this one feels the most likely to get set to 0
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message-1499416928937181194

2026-04-30T14:27:33.678+00:00 — tnt (@246tnt)

Content

`[0:0]` should be valid AFAIK.
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message-1499417407200956628

2026-04-30T14:29:27.705+00:00 — Dory (@dorythecat_v2)

Reply/reference

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I already reported this a whileago. This is because the generation code is not in an ifdef
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message-1499417464339959944

2026-04-30T14:29:41.328+00:00 — Dory (@dorythecat_v2)

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I believe I had said I would open an issue and try to fix it...
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message-1499417475450667049

2026-04-30T14:29:43.977+00:00 — Dory (@dorythecat_v2)

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And never did...
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message-1499417483780554833

2026-04-30T14:29:45.963+00:00 — Dory (@dorythecat_v2)

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Oops...
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message-1499426694254297168

2026-04-30T15:06:21.911+00:00 — Leo Moser (mole99) (@mole99)

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Yeah, please open an issue so that I remember to fix it (or anyone that comes before me).
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message-1499426849875558550

2026-04-30T15:06:59.014+00:00 — Dory (@dorythecat_v2)

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I will open an issue and try to fix it myself, since I said I would I now feel a bit obligated lol
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message-1499426854560469152

2026-04-30T15:07:00.131+00:00 — Dory (@dorythecat_v2)

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Brb
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message-1499427745925562459

2026-04-30T15:10:32.649+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I suggest opening the issue, then even if you fix it or not you are half way there 🙂
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message-1499428786721259720

2026-04-30T15:14:40.794+00:00 — Dory (@dorythecat_v2)

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Yeah I already opened it
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message-1499428872150843515

2026-04-30T15:15:01.162+00:00 — Dory (@dorythecat_v2)

Content

[#58](https://github.com/wafer-space/gf180mcu-project-template/issues/58)

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message-1499429380336910546

2026-04-30T15:17:02.323+00:00 — Dory (@dorythecat_v2)

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Seeing if a quick fix does it (it should but always gotta test xd)
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message-1499434131946209350

2026-04-30T15:35:55.195+00:00 — Dory (@dorythecat_v2)

Content

@Leo Moser (mole99) please test and lmk if [this pull request](https://github.com/wafer-space/gf180mcu-project-template/pull/59) fixes it! :D

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message-1499450318893748264

2026-04-30T16:40:14.464+00:00 — Leo Moser (mole99) (@mole99)

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Content

Thank you, I will take a look soon.
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message-1499451025206149210

2026-04-30T16:43:02.862+00:00 — Dory (@dorythecat_v2)

Content

No worries;
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message-1501173863046709350

2026-05-05T10:48:59.412+00:00 — Rob Taylor (@robtaylor_52029)

Content

is https://github.com/wafer-space/gf180mcu-project-template/issues/38 still valid?

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message-1501198567245877430

2026-05-05T12:27:09.352+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, this is still valid. I'm in the process of upstreaming the wafer.space changes to open_pdks. I'll take a look at the open issues then.

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message-1503418680451792966

2026-05-11T15:29:05.588+00:00 — BreakingTaps (@polyfractal)

Content

Hmm, _might_ have found a bug in the LVS deck for nw2ps diode? This is pretty outside my knowledge so not sure. I was trying to get an nw2ps photodiode to work in an analog circuit, but the diode kept failing to extract in LVS (remained anonymous pins) despite the geometry looking correct.

AI slop machines helped debug and it looks like the deck ties the n terminal to `nwell` which you can't connect to directly? Other diodes use `ntap` or `nwell_con`

I've switched to a dnwell diode and unblocked, but thought I'd mention here in case someone more knowledgeable than me might know.

```
# diode_nw2ps_03v3 diode
connect(diode_nw2ps_03v3_terminal_p, contact)
connect(diode_nw2ps_03v3_terminal_n, nwell)
```
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message-1503449604736417806

2026-05-11T17:31:58.512+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1509176448223674489

2026-05-27T12:48:24.399+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 It's been a while since the last update to the project template, but we worked on a lot of improvements in the background, which I'm happy to share with you now!

All of the wafer.space PDK changes have finally been upstreamed to [open_pdks](https://github.com/RTimothyEdwards/open_pdks), which allows us to sunset the wafer.space PDK fork.
This is important since we want one common target for community efforts and avoid unnecessary fragmentation. Many of the community-created IPs are already part of open_pdks (SCL, PAD, SRAM and eFuse libraries).
You can now use [Ciel](https://github.com/fossi-foundation/ciel), the PDK manager, to manage your PDKs. The project template will use Ciel as well.

In addition, I have enabled support for the community-created 3v3/5v I/Os, the 3v3 SRAMs and the 3v3 standard cell library in the template. Not all of the IPs have been tested yet, so support for them is experimental!

Give it a try in this pull request: https://github.com/wafer-space/gf180mcu-project-template/pull/60
I plan to merge it soon and would appreciate any feedback beforehand.

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message-1509176501181087835

2026-05-27T12:48:37.025+00:00 — Leo Moser (mole99) (@mole99)

Content

Another major change in this upcoming update is the new KLayout DRC runner by @Clyde Laforge.
Thanks to this, the KLayout DRC deck is now parallelized across rule decks while sharing some of the memory!
This makes it possible to build the 1x1 project template, including DRC checks, in 40 minutes on my machine (24 threads).

Currently, the number of workers is set to "max" in the LibreLane config. If RAM usage is too high, reduce the number of workers. For a best possible utilization choose: threads * workers = hardware threads.

Clyde also considerably improved the KLayout LVS setup, including the handling of substrate cuts. So if you are interested in doing an analog design with KLayout, now is the time to give this a try!

Please let me know if you have any questions regarding these changes.
If you plan to tape out on ws-run #2, you will need to use the updated template, since a few changes are required to pass the precheck. More on that once the update is live.
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message-1509176586190983168

2026-05-27T12:48:57.293+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1509177279438393545

2026-05-27T12:51:42.576+00:00 — tnt (@246tnt)

Content

Huh ... I'd like to know about those change because in TT we don't use the template at all and I'm working right now to finalize the run 2 builder.
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message-1509280353049776358

2026-05-27T19:41:17.24+00:00 — RebelMike (@rebelmike)

Content

I've hit a problem upgrading to this version of the template.  I've tracked it down to the new librelane version - if the only change I make is to switch nix to use the `leo/wafer-space` branch of librelane then I see the same issue.

The problem is undriven net errors, e.g.:
```
Warning: Wire tqvp_uart_tx.\next_fsm_state$func$/home/mdb36/wafer-space/ws02-tinyQV/src/user_peripherals/uart/uart_tx.v:116$2738.tx_en is used but has no driver.
Warning: Wire tqvp_uart_tx.\next_fsm_state$func$/home/mdb36/wafer-space/ws02-tinyQV/src/user_peripherals/uart/uart_tx.v:116$2738.$result [3] is used but has no driver.
```
This particular case is using a verilog function, and I tried changing the uart_tx module to remove the function (inlining it into the process that calls it), and that fixes that instance of the warnings.  So I suspect it's a regression in yosys.
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message-1509285266941153461

2026-05-27T20:00:48.803+00:00 — RebelMike (@rebelmike)

Content

ok, a minimal repro where I just wire up that uart module does hit the error.  See https://github.com/MichaelBell/wafer-space-repro/commit/76eb8c6123fbd1c241e89a2f7ca8dd394ea7112b

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message-1509289387740102661

2026-05-27T20:17:11.278+00:00 — Leo Moser (mole99) (@mole99)

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message-1509590982453104804

2026-05-28T16:15:37.061+00:00 — BreakingTaps (@polyfractal)

Content

3v3 SRAM macros are exciting! Has anyone had a chance to test those yet? I forget who taped them out for this run
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message-1509596612312305996

2026-05-28T16:37:59.324+00:00 — tnt (@246tnt)

Content

@Tim Edwards did, but he has a custom pad frame in his test chip AFAIU so he needs to get them wire bonded himself.
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message-1509599804140032021

2026-05-28T16:50:40.315+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@BreakingTaps :  I did have one full-size chip that I called my "Hail Mary" project, as everything in it was experimental.  But I also had a half-size test chip with the SRAM macros wired out to the pads for testing and characterization.  That was not a custom frame other than that it was a half-size chip.  So I'd appreciate anyone who pushes on @Tim 'mithro' Ansell to get those packaged and mailed out.  The sooner that's done, the sooner I have an answer for you.

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message-1509602909321564313

2026-05-28T17:03:00.648+00:00 — RebelMike (@rebelmike)

Reply/reference

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Content

Is it 1xp5 or p5x1?  I believe some 1xp5 CoB boards have been/are being made.
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message-1509605161218084864

2026-05-28T17:11:57.542+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@RebelMike :  It's `1x0p5` (which I guess is good!).

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message-1509667016259272747

2026-05-28T21:17:44.933+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

Those boards are due to be delivered to the  people who would bring it to the wirebonders on Jun 1

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message-1509705787554005024

2026-05-28T23:51:48.73+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

If your design works with the 1x0p5 CoB that @RebelMike made, then I'll get them bonded at the same time and get them sent out.
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message-1509819009351024671

2026-05-29T07:21:42.91+00:00 — RebelMike (@rebelmike)

Content

As long as the vdd and vss pads were in the same place as the project template it should work, and it should also be usable with the breadboard breakout.
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message-1510072883446022194

2026-05-30T00:10:31.211+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - I believe you kept the VDD/VSS in the same places as the default on that one?
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message-1510073437165453383

2026-05-30T00:12:43.228+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  Yes.  It was only the "openframe" where I was following the original Caravel padframe for reasons of compatibility with my original Efabless Caravel-GF development board.  The SRAM test chip just followed the template pad assignments.
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message-1510318588391854251

2026-05-30T16:26:51.835+00:00 — dmv (@.dmv)

Content

Hi everyone. First time commenter. I've tried to read all the discord first. I am working on a 1×1 slot design with a custom analog-heavy padring (18 'asig_5p0' pads total). LibreLane places everything without error, but I want to confirm the precheck won't flag the supply topology.

My north side has 9 analog pads with 2 DVDD and 3 DVSS power pads interspersed. My east side has 9 analog pads with 4 DVDD and 3 DVSS. Is there any precheck rule that requires a minimum number of DVDD/DVSS pads per side, or a minimum ratio to analog pad count? Or does the precheck only validate physical DRC (spacing, overlap, well rules)?

Right now, this is mostly a design/viability exercise (can I get this idea to simulate, working in a space I'm not very familiar with) so I'm probably going to have more questions about the practical bits. This is the first inquiry where just reading everyone else's progress wasn't enough to resolve. Thank you in advance.
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message-1510320793622413433

2026-05-30T16:35:37.603+00:00 — namibj

Reply/reference

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Content

You don't need that many supply pads; note that if you use a padframe that (beyond customizing what pad type a non-supply-pad is populated with) deviates from the reference, the plain standard COB offer doesn't work.

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message-1510320805110616196

2026-05-30T16:35:40.342+00:00 — tnt (@246tnt)

Content

@dmv Note if you change the power pad position, you will have to handle bonding yourself.

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message-1510323095003467978

2026-05-30T16:44:46.295+00:00 — RebelMike (@rebelmike)

Content

When building my design, which is getting fairly full but from the render seems like there's a bit more space, the metrics now say ```
    "design__instance__utilization": 1.06565,
    "design__instance__utilization__stdcell": 1.1131,
```
I had thought that both of these would max out at 1.  What do these actually measure?  Might going above 1 related to using Tholin's 3v3 library, or is it expected anyway?
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message-1510323665475211466

2026-05-30T16:47:02.306+00:00 — namibj

Content

Do you have a density target set? I'd figure that it's reported relative to that?
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message-1510325035074715648

2026-05-30T16:52:28.844+00:00 — RebelMike (@rebelmike)

Content

Ah, possibly.  My density target is 60%.  Global placement is saying utilization 54.8%, but obviously once buffers, clock tree, etc have gone in utilization to be somewhat higher.
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message-1511722026648338514

2026-06-03T13:23:37.59+00:00 — Leo Moser (mole99) (@mole99)

Content

@everyone 📢 The project template update is now live!

- Project Template [1.5.0](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.5.0)
  - Switch to [open_pdks](https://github.com/RTimothyEdwards/open_pdks) for the PDK, managed by [Ciel](https://github.com/fossi-foundation/ciel). This enables a number of new community IPs.
  - Add SCL, PAD and SRAM environment variables to the flow. This allows building a chip with 3.3V standard cells, 3.3V SRAMs, and 3.3V/5V compatible I/Os, for example.
  - Enable the new DRC runner. The KLayout DRC deck is now parallelized across rule decks while sharing some of the memory.
    For a best possible utilization choose: threads * workers = hardware threads. If RAM usage is too high, reduce the number of workers.
  - Rename the QR code ID, add readable shuttle and project IDs, add a marker. Only required if CoB option is selected.

- Precheck [1.6.0](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.6.0)
  - Switch to [open_pdks](https://github.com/RTimothyEdwards/open_pdks) for the PDK, managed by [Ciel](https://github.com/fossi-foundation/ciel).
  - Add the `--cob` flag.
  - Enable the new DRC runner.

I've seen a significant reduction in runtime running the precheck on my machine with 24 cores: 0p5x0p5 slot: 0:06:36, and 1x1 slot: 0:40:14.
Please note that the platform still needs to be updated to benefit of the new DRC runner and to make the CoB packaging option selectable.

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message-1511722060861145180

2026-06-03T13:23:45.747+00:00 — Leo Moser (mole99) (@mole99)

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message-1511722104717049898

2026-06-03T13:23:56.203+00:00 — Leo Moser (mole99) (@mole99)

Content

If you are planning to tape out on wafer.space GF180MCU Run 2, please ensure your project is updated accordingly.
There will be further updates before the tapeout. Though they won't be as significant as this one, so they can be easily applied to your existing projects.

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message-1512279630692880495

2026-06-05T02:19:20.754+00:00 — Rob Taylor (@robtaylor_52029)

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just checking, is the 3.3v library there @Tholin's?
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message-1512324770312622100

2026-06-05T05:18:42.878+00:00 — Leo Moser (mole99) (@mole99)

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Correct, it's the gf180mcu_as_sc_mcu7t3v3 SCL.

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message-1512408274991841353

2026-06-05T10:50:31.945+00:00 — Rob Taylor (@robtaylor_52029)

Content

@Leo Moser (mole99) just checking, is it required to move to 1.5.0 for the run 2 tapeout?
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message-1512505495628288161

2026-06-05T17:16:51.151+00:00 — Leo Moser (mole99) (@mole99)

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If you use the CoB packaging option, then yes. You need the new ID and marker macros in the correct positions in order to pass precheck.
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message-1512584220915138770

2026-06-05T22:29:40.722+00:00 — Rob Taylor (@robtaylor_52029)

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thanks!
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message-1512737799177240666

2026-06-06T08:39:56.633+00:00 — RebelMike (@rebelmike)

Content

Any idea why I might be getting this error when running the KLayout.XOR step locally (but not on GitHub - it's running fine there!): ```
ERROR: In /nix/store/x0ckywq495x29y1q4bldarafacwzzsxj-python3-3.13.9-env/lib/python3.13/site-packages/librelane/scripts/klayout/xor.drc: 'source': Stream has unknown format: /home/mdb36/wafer-space/ws02-tinyQV/librelane/runs/RUN_2026-06-06_09-45-39/56-magic-streamout/chip_top.magic.gds in Layout::read
```
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message-1512739634692489366

2026-06-06T08:47:14.254+00:00 — RebelMike (@rebelmike)

Content

Only thing I can think of is the nix install is old.  But it's a bit weird it's otherwise working.  Can I upgrade nix by rerunning the install script from https://librelane.readthedocs.io/en/stable/installation/nix_installation/installation_linux.html ?
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message-1512840413877239878

2026-06-06T15:27:41.884+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Minor project template update!

- Project Template [1.5.1](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.5.1)
  - Update PDK to `9233c192`.
  - Automatically fetch new PDK if hash has changed.

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message-1512840461348503723

2026-06-06T15:27:53.202+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1513112664635867288

2026-06-07T09:29:31.523+00:00 — RebelMike (@rebelmike)

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message-1513546884726259844

2026-06-08T14:14:57.66+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Bugfix project template update!

- Project Template [1.5.2](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.5.2)
  - Update PDK to `f6bfbd4d`
    - Fix port attributes on the `gf180mcu_ocd_io__in_s` cell, which previously caused OpenROAD to skip CTS (clock tree synthesis)! Thanks @RebelMike for reporting this issue!
  - Update LibreLane dev to latest
    - Magic scripts use `locking disable`, which prevents the maximum open file descriptor limit from being reached.

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message-1513546939944145138

2026-06-08T14:15:10.825+00:00 — Leo Moser (mole99) (@mole99)

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message-1514747651210477638

2026-06-11T21:46:22.699+00:00 — BreakingTaps (@polyfractal)

Content

Hmm, cautionary note. May be specific to my setup and something I goofed up.

Discovered my project template was on an old verison of the PDK despite being on latest git commit and running `make clone-pdk`. Turns out the newer PDK version was downloaded but the symlink was still pointing at the old version.  No idea how that happened, I might have interrupted it mid-updating or something.
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message-1514765947133755454

2026-06-11T22:59:04.787+00:00 — namibj

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I forgot to put the pdk root env into scope before I updated, then wondered 2 days later why something was buggy that I had thought to have been fixed, just to realize what I had done... 😄

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message-1515250939769127038

2026-06-13T07:06:16.042+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) We need to use librelane dev branch for stuff to work correctly right ?
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message-1515444291995045888

2026-06-13T19:54:34.805+00:00 — tnt (@246tnt)

Content

It would also be nice if the action on the repo could save the resuls ... I'd like an example GDS as "reference" since I'm using a different build process and trying to match it without having to build it myself.
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message-1515454724214624347

2026-06-13T20:36:02.04+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, the project template currently uses LibreLane dev due to some required updates.
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message-1515455574161096806

2026-06-13T20:39:24.683+00:00 — Leo Moser (mole99) (@mole99)

Content

The action in the project template actually builds all of the different slot sizes and uploads their GDS. But I think you can't access them because you're not the owner of the repository.
You can fork the repository and should then be able to download the final GDS.
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message-1515455958766325992

2026-06-13T20:40:56.38+00:00 — tnt (@246tnt)

Content

Mmm, is that a settings ? I mean on TT's action anyone can download the artefacts.
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message-1515456808871788736

2026-06-13T20:44:19.061+00:00 — Leo Moser (mole99) (@mole99)

Content

Maybe. At first, I thought that everyone could download them, but Tim E. let me know that he can't access them.
I'll take a look at the settings tomorrow.

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message-1515613227831001209

2026-06-14T07:05:52.247+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) Oh my bad, I can download the artefact ...
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message-1515631183591899197

2026-06-14T08:17:13.234+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Good to know! I think you at least need to be logged in to GitHub.

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message-1515815789603590256

2026-06-14T20:30:46.737+00:00 — Ian Hanschen (@furanfuranfuran)

Content

hi, I hit the following w/make librelane on the latest template after a successful make clone-pdk:
Writing src/generated_defines.svh
SRAM_DEFINE=SRAM_gf180mcu_fd_ip_sram librelane librelane/slots/slot_1x1.yaml librelane/macros/macros_5v.yaml librelane/config.yaml --pdk gf180mcuD --pdk-root /opt/chip/gf180mcu-project-template/gf180mcu --manual-pdk --scl gf180mcu_fd_sc_mcu7t5v0 --pad gf180mcu_fd_io --save-views-to /opt/chip/gf180mcu-project-template/final
[14:29:35] ERROR    Errors have occurred while loading the       __main__.py:160
                    design configuration file.
[14:29:35] ERROR    Unknown key                                  __main__.py:162
                    'PDN_CORE_RING_CONNECT_TO_PAD_LAYERS'
                    provided.
[14:29:35] ERROR    LibreLane will now quit. Please check your   __main__.py:164
                    configuration.
make: *** [Makefile:94: librelane] Error 1
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message-1515829762512257195

2026-06-14T21:26:18.138+00:00 — RebelMike (@rebelmike)

Reply/reference

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Content

That is surprising, it suggests you have the wrong version of LibreLane.  Have you installed locally rather than running through nix?
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message-1515830481160245378

2026-06-14T21:29:09.477+00:00 — Ian Hanschen (@furanfuranfuran)

Content

running through nix - I'm still digging, might have an old install
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message-1515831918485180537

2026-06-14T21:34:52.162+00:00 — RebelMike (@rebelmike)

Content

`librelane --version` should say `LibreLane v3.1.0.dev1`
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message-1515832616513699961

2026-06-14T21:37:38.585+00:00 — Ian Hanschen (@furanfuranfuran)

Content

[nix-shell:~]$ librelane --version
LibreLane v3.0.4
[nix-shell:~]$ which librelane
/nix/store/qjkqjsc147pnkgdr6lm288f5p757bliv-devshell-dir/bin/librelane
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message-1515833881041834035

2026-06-14T21:42:40.072+00:00 — Ian Hanschen (@furanfuranfuran)

Content

it's my nix install, 1 sec
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message-1515834520471863507

2026-06-14T21:45:12.524+00:00 — Ian Hanschen (@furanfuranfuran)

Content

good to go now - I think I had a newer nix installed, it was erroring updating the ciel package on startup
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message-1515836292787605525

2026-06-14T21:52:15.077+00:00 — Ian Hanschen (@furanfuranfuran)

Content

the error I had before was some sort of issue with the way nixpkgs is used vs the nix I had installed, so I removed/reinstalled using the curl command from the website. here's the error, if it's interesting:
         … while calling the 'import' builtin
           at «string»:1:2:
              1| (import <nixpkgs> {}).bashInteractive
               |  ^

         … while realising the context of a path

         … while calling the 'findFile' builtin
           at «string»:1:9:
              1| (import <nixpkgs> {}).bashInteractive
               |         ^

         error: file 'nixpkgs' was not found in the Nix search path (add it using $NIX_PATH or -I)
  uses bash from your environment
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message-1515836414372085872

2026-06-14T21:52:44.065+00:00 — Ian Hanschen (@furanfuranfuran)

Content

template build is at step 63 so I think I'm set up, thanks

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message-1515987239975518340

2026-06-15T07:52:03.691+00:00 — Leo Moser (mole99) (@mole99)

Content

@Ian Hanschen Nice to see you here!
I'm glad to hear that you managed to set up the project template.

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message-1516040175241789481

2026-06-15T11:22:24.442+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) `f741b96babd3517a01e6cc9efc3ab1eef8cbacee` from the "old" wafer space PDK doesn't seem to have been applied upstream.
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message-1516040210629132369

2026-06-15T11:22:32.879+00:00 — tnt (@246tnt)

Content

`Change ANTENNAGATEPLUSDIFF multiplier from 2 to 15 in gf180mcu_fd_sc_mcu7t5v0 techlefs`
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message-1516040295240958053

2026-06-15T11:22:53.052+00:00 — tnt (@246tnt)

Content

Kind of a useful one 😅
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message-1516040842752692255

2026-06-15T11:25:03.589+00:00 — Leo Moser (mole99) (@mole99)

Content

@tnt Thank you! It looks like that one slipped through. I will update the PDK shortly. However, open_pdks won't be synced until tomorrow.

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message-1516049344480936006

2026-06-15T11:58:50.559+00:00 — Egor Lukyanchenko (@egorxe)

Reply/reference

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@Tim Edwards Is there any know time frame for your 3.3V OCD SRAM tests? I suspect a lot of people are eagerly awaiting your results 😅 .
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message-1516050096024850483

2026-06-15T12:01:49.741+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Wow, can't believe it's been 2 weeks or more since I wrote that. Unfortunately his boards are currently still in China. I am hoping they will ship in the coming day(s)
Then there's a few days for it to get to him.
Yeah, we're all eager 😂 but want to keep a bit of pressure off Tim

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message-1516051333164302429

2026-06-15T12:06:44.698+00:00 — tnt (@246tnt)

Content

But those are just the COB ? Are you shipping some breakout to 100mil headers too ? Because else, he will need to design some kind of host board and getting any kind of results before the submission deadline sounds pretty tight.
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message-1516054137920557287

2026-06-15T12:17:53.404+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Good point.
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message-1516088059425198289

2026-06-15T14:32:40.921+00:00 — Leo Moser (mole99) (@mole99)

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Started a thread.
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message-1516115873448988792

2026-06-15T16:23:12.301+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@tnt :  I was thinking the same thing the other day.  Have any host board designs been made yet that are compatible with the COBs?  I could probably make do with a simple board that just routes the connector pins to a standard header.
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message-1516118547703529553

2026-06-15T16:33:49.893+00:00 — RebelMike (@rebelmike)

Content

I have some of these https://codeberg.org/rebelmike/ws-breakout, but they aren't tested yet as my COBs should arrive at roughly the same time as yours.  Since I made that the breakouts in the WS repo have been updated: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/run-1/motherboards but I don't know if anyone has made any of those yet.  I think various people have tested with the previous version of that (which as far as I'm aware was fine except the pin 1 marker was the wrong side)
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message-1516120547476373668

2026-06-15T16:41:46.676+00:00 — RebelMike (@rebelmike)

Content

The 1x0p5 COB is pinout compatible with the 1x1 COB in terms of power and ground.  The signal pads are mostly in the same order too, but for (probably bad) reasons I reversed the order of pads 67-70.  You can view the schematic here (pin/pad names are those on the default project template): https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2Frun-1%2F1x0p5-cob
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message-1516130611319017502

2026-06-15T17:21:46.083+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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I've used the long breakoutboards from that repo, seem to be working for the minimal tests I've tried.

I have some of the PCBs unpopulated and some of the mezzanine connectors, happy to fedex you one if you want @Tim Edwards . Will have to do the soldering yourself since my soldering skills are terrible and it took me many tries to get one working 😅

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message-1516130898901205253

2026-06-15T17:22:54.648+00:00 — BreakingTaps (@polyfractal)

Content

(oh, mine are the pre-updated version. I think it was just the silkscreen that changed)
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message-1516131271011733556

2026-06-15T17:24:23.366+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@BreakingTaps : Sure, I'll take you up on that offer.  I assume that unless I'm _really_ bad at soldering, I should only need one board.  I can get the connector myself as long as somebody can tell me what the part number is from Digi-Key or Mouser.

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message-1516131656442843257

2026-06-15T17:25:55.26+00:00 — tnt (@246tnt)

Content

It's 0.4mm pitch 🙂
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message-1516132035301871748

2026-06-15T17:27:25.587+00:00 — RebelMike (@rebelmike)

Content

Yeah, I got JLC to solder mine. Though having seen those photos of the CoB boards I might go double check they actually managed that..
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message-1516132696814911761

2026-06-15T17:30:03.304+00:00 — BreakingTaps (@polyfractal)

Content

i definitely regret thinking I could do it by hand 🫣
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message-1516132880626225422

2026-06-15T17:30:47.128+00:00 — tnt (@246tnt)

Content

I believe mouser 798-DF40C2070DS04V51 is compatible.
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message-1516136726131638383

2026-06-15T17:46:03.968+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Thanks for the heads-up on the pin pitch.  That indeed will be difficult to hand solder.
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message-1516137005841514696

2026-06-15T17:47:10.656+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@RebelMike :  Will JLC assemble from parts that you send to them?
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message-1516138966343225385

2026-06-15T17:54:58.076+00:00 — namibj

Reply/reference

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yes, it's expensive
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message-1516139108253044968

2026-06-15T17:55:31.91+00:00 — namibj

Content

like 70$ for each 50qty, each batch seems to be billed in full iirc
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message-1516139238419333272

2026-06-15T17:56:02.944+00:00 — namibj

Content

(I've done so)
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message-1516139548323610784

2026-06-15T17:57:16.831+00:00 — tnt (@246tnt)

Content

But JLC can also get the part from LCSC directly.
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message-1516139587389493343

2026-06-15T17:57:26.145+00:00 — namibj

Content

yes
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message-1516139663688077476

2026-06-15T17:57:44.336+00:00 — namibj

Content

if mouser or digikey have them it's different fee structure if you use global sourcing
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message-1516143927907061890

2026-06-15T18:14:41.005+00:00 — RebelMike (@rebelmike)

Content

At least when I ordered LCSC had the part in stock so it was easy to get them to use it. 5 PCBs and assembly was ~$25 + shipping and duties
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message-1516145112940417224

2026-06-15T18:19:23.539+00:00 — Leo Moser (mole99) (@mole99)

Content

Yeah, I just sent my [PCB](https://github.com/mole99/waferspace-main-pcb) for fabrication via JLCPCB, including assembly with parts from LCSC.

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message-1516300551170686976

2026-06-16T04:37:02.901+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I should have some around as well I can send if you like.
I consider myself a touch above average with soldering. I still mucked a few of them before I got a good one.
0.4mm is quite tiny.
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message-1516475814227480786

2026-06-16T16:13:28.87+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Yeah, I'm decently good at soldering but I struggle with 0.5mm pitch and so I think I'll leave 0.4mm pitch to the experts.
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message-1516476882449596507

2026-06-16T16:17:43.554+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  You need to be selling these boards on the Wafer.Space site!
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message-1516495476428640286

2026-06-16T17:31:36.704+00:00 — BreakingTaps (@polyfractal)

Content

++ i would definitely have bought them (plus some margin for profit/sustainability) over doing it myself

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message-1516683616204099734

2026-06-17T05:59:12.722+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

If someone want to design a "support dev kit" for wafer space chips, I would happily figure out how to get them manufactured and such.
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message-1517130928248586290

2026-06-18T11:36:40.224+00:00 — Leo Moser (mole99) (@mole99)

Content

@everyone 📢 Important update!

A regression was introduced to the LibreLane padring generation script, resulting in the north and south bond pads being off-center by 0.5 µm. This project template update resolves this issue. Additionally, a step has been added to the precheck that compares the pad layer with a golden mask to ensure that the pads match the default CoB padring for the given slot size.

- Project Template [1.5.3](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.5.3)
  - Update LibreLane dev to latest
    - Fix an issue in the padring script, ensuring the pads are correctly aligned again.
  - Update PDK to `019cf7a3`
    - Port a missing fix regarding antenna insertion for the foundry standard cells from the wafer.space PDK fork. Thanks, @tnt!

- Precheck [1.7.0](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.7.0)
  - Add a pad mask check to verify that the layout is compatible with the CoB packaging option. Enabled via the `--cob` flag.
  - Render the layout.

Please update your designs accordingly. The pad mask check will soon be activated on the submission platform. Until then, you can run the precheck locally with the `--cob` option to ensure a compatible layout.
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message-1517130959164674078

2026-06-18T11:36:47.595+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Pinned a message.
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message-1517151279594340447

2026-06-18T12:57:32.363+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  The "support kit" in question is Mike's board at https://codeberg.org/rebelmike/ws-breakout.  It is a trivially simple breakout board---takes the mezzanine connector with absurdly small pin pitch out to a pair of 0.1" row headers.  The sole components are the mezzanine connector and the headers.  Getting the mezzanine connector soldered down professionally on short notice locally is going to cost me in the range of $200.  So I would definitely like to see this cheaply assembled and sold to me on the Wafer.Space online store.  I would pay a considerable markup to avoid a one-off, $200 job.
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message-1517162067541495830

2026-06-18T13:40:24.41+00:00 — gojimmypi

Reply/reference

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Does everyone on the gf180 track need to resubmit? Any local changes needed to GH actions?
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message-1517162583797268683

2026-06-18T13:42:27.495+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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What do you mean by "gf180 track"?
As for the changes to the project template, you need to update `flake.lock` and the PDK hash: https://github.com/wafer-space/gf180mcu-project-template/commit/a4bca2f870986b4232f47378168334cb30b1a0da
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message-1517164595003789423

2026-06-18T13:50:27.004+00:00 — gojimmypi

Reply/reference

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If I'm on the gf26a shuttle due Monday, do I need to rebuild & resubmit?
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message-1517165034399338627

2026-06-18T13:52:11.764+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

If you have a question about the Tiny Tapeout shuttle, you should ask on the Tiny Tapeout Discord server.
But no, this only affects the padring, which the Tiny Tapeout team has already fixed.

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message-1517172407180198089

2026-06-18T14:21:29.572+00:00 — jalcim (@tisse2274)

Content

thanks for information
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message-1519012555975299264

2026-06-23T16:13:35.233+00:00 — Tholin (@tholin)

Content

How can I launch magic in the template and have it load the rcfile correctly? Even when I point it to the .magicrc file for the PDK with `-rcfile` and an absolute path, it claims it can’t find the file.
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message-1519012653497061438

2026-06-23T16:13:58.484+00:00 — Tholin (@tholin)

Content

I am still relying on iic-osic-tools just for magic
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message-1519013352880209970

2026-06-23T16:16:45.23+00:00 — Leo Moser (mole99) (@mole99)

Content

Could you please share the command that you are using?
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message-1519013923951607939

2026-06-23T16:19:01.384+00:00 — Tholin (@tholin)

Content

`magic -rcfile $(pwd)/gf180mcu/gf180mcuD/libs.tech/magic/gf180mcuD.magicrc`
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message-1519014280878489640

2026-06-23T16:20:26.482+00:00 — Tholin (@tholin)

Content

The `$(pwd)` is illustrative, I am not going to paste the whole absolute path of my working directory in there, but imagine I did
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message-1519014340802510989

2026-06-23T16:20:40.769+00:00 — Tholin (@tholin)

Content

A relative path also doesn’t work
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message-1519014516955021393

2026-06-23T16:21:22.767+00:00 — Tholin (@tholin)

Content

```Could not find file '/home/tholin/work/open_pdks/open_pdks/root/ciel/gf180mcu/build/019cf7a3e0de79bb0e4b6213758882d283c65816/gf180mcuD/libs.tech/magic/gf180mcuD.tech' in any of these directories:
         . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current```
it goes in response, which is not the path I entered, and it also doesn’t exist
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message-1519014683183419402

2026-06-23T16:22:02.399+00:00 — Tholin (@tholin)

Content

There is no "work" directory in my home dir
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message-1519074086741999767

2026-06-23T20:18:05.311+00:00 — RebelMike (@rebelmike)

Content

@Leo Moser (mole99) I've integrated the latest template update and I'm hitting a DRC error in the padring.  The problem occurs if a bidir pad is first on the north side on a quarter size slot.  I've just pushed up a branch with a minimal change to the template that repros the problem: https://github.com/MichaelBell/ws02-tinyQV/tree/template

Embeds

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message-1519077261955829780

2026-06-23T20:30:42.341+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Thanks Mike, that issue also happened in a full slot. It should be fixed with the PDK update tomorrow.
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message-1519077702903009442

2026-06-23T20:32:27.471+00:00 — RebelMike (@rebelmike)

Content

Ah that's good to hear it is fixed!  I'll get that integrated tomorrow evening
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message-1519353174622736394

2026-06-24T14:47:05.047+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 PDK update!

This is a minor update that is only necessary if you encountered DRC violations in your padring when using the 3.3V/5V I/Os.

- Project Template [1.5.5](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.5.5)
  - Update PDK to `140b0494`
    - Adjust the layout of `bi_24t` of the `gf180mcu_ocd_io` library to prevent DRC violations in certain cases.
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message-1519353212405026816

2026-06-24T14:47:14.055+00:00 — Leo Moser (mole99) (@mole99)

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message-1521527155178340382

2026-06-30T14:45:42.402+00:00 — bunnie (@bunnievorpal)

Content

stupid question - what's the procedure to submit GDS to the upcoming run? probably there's a link in some obvious place and i've just missed it.
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message-1521527515410075749

2026-06-30T14:47:08.288+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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https://platform.wafer.space/

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message-1521590629468082237

2026-06-30T18:57:55.852+00:00 — Olle (@osvel)

Content

Is there a template for writing hierarchical designs and hardened macros? I assume I can just copy the normal one and remove some IO restrictions and padding? Is there something else one should consider?
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message-1521601595509440612

2026-06-30T19:41:30.36+00:00 — tnt (@246tnt)

Content

How you handle PDN for macros is usually a pain point ... different options with different trade-offs and often incompatible between then so you got to pick one.
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message-1521634849625079910

2026-06-30T21:53:38.759+00:00 — bailey (@bailey8889)

Reply/reference

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Does this help? https://platform.chipfoundry.io/knowledge-base/article/hardening-options
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message-1521791559832567818

2026-07-01T08:16:21.384+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

Content

Also having CTS done separately on different blocks is dangerous as the clock tree depth may be different between blocks causing unexpected hold/setup violations for signals going between different blocks.
If I'm not mistaken, LibreLane supports P&R on subblocks separately but still CTS on top block.
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message-1521792356339290152

2026-07-01T08:19:31.286+00:00 — tnt (@246tnt)

Content

I know that CTS recently(-ish) got the ability to place macro at different depth of the CTS depending on the min/max clock delay specified in the liberty file of the macros/sub-blocks.  ( https://github.com/The-OpenROAD-Project/OpenROAD/issues/3759 )
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message-1521794674665459752

2026-07-01T08:28:44.018+00:00 — Olle (@osvel)

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Cool, thanks for all the tips. I guess I will have a play around with this and see what I come up with. 🙂
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message-1521796270635880492

2026-07-01T08:35:04.527+00:00 — tnt (@246tnt)

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But TBH I'm not sure how common it is to harden various block independently. That prevents optimization at boundary and also cost area since macro are rectangular and blocks often harden more into blob shapes.
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message-1521796509765730345

2026-07-01T08:36:01.54+00:00 — tnt (@246tnt)

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The only case where I see blocks hardened as macro are highly optimized ones where there was significant manual/scripted/layout/... work to make it a separate block. Something like a SRAM / memory or something like that.
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2026-07-01T08:36:18.532+00:00 — tnt (@246tnt)

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Or of course analog-ish block like say a PLL.
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message-1521796740209184788

2026-07-01T08:36:56.482+00:00 — tnt (@246tnt)

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But I wouldn't say ... harden a SPI controller independently ... that'd be a lot of headache for virtually no benefits.
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message-1521796837143740568

2026-07-01T08:37:19.593+00:00 — tnt (@246tnt)

Content

Just my 2 cts ...
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message-1521803184941830294

2026-07-01T09:02:33.026+00:00 — Olle (@osvel)

Content

Thanks, appreciate the input. I'm not super familiar with this field and trying to learn. In my case, I'm studying SIMD lanes and thought to make the separate arithmetic units (say 32 of them) as I thought this is how 'real' designs are made. I had some severe congestion issues when trying to synth my top module
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message-1521950406056480910

2026-07-01T18:47:33.275+00:00 — namibj

Reply/reference

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I'd consider looking into the placement/partitioning tuning options in librelane for how to possibly selectively nudge the density around congested blocks to be lower and/or nudge SIMD lanes to be substantially less-overlapping.
If your SIMD instructions are complex enough it might be practical to force them into slices, though, to spend much more compute on optimizing a slice, afforded by then getting to just make 31 already-routed copies at no extra PnR compute for the dense intra-slice situation.
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message-1521958443785650226

2026-07-01T19:19:29.619+00:00 — Olle (@osvel)

Reply/reference

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Right. Yeah, its basically option 2 I have been considering (slicing it into a module and instancing it 32 times). At least, that makes sense in my mind. But I understand now that this is a bit more complex than I first thought. I believe I need to specify where I/O to this 'macro' will be placed (like inputs on the left, outputs on the right), but I'm also having issues getting this to close. Well.
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message-1521958470012899439

2026-07-01T19:19:35.872+00:00 — Olle (@osvel)

Content

Thanks for all the tips! 🙂
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message-1521988548520050688

2026-07-01T21:19:07.147+00:00 — namibj

Reply/reference

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yeah ideally you'd somehow be able to tell it just that in this region there are 32 identical slices and that they're instances for the 32-wide datapath around it, and that it has to figure out PnR inside, outside, and has to figure out how it likes the ports placed.

I'd probably give it opportunity to just place the ports wherever on the grid on one side in teh small slice and just roll with what it likes best there.
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message-1523236999517962380

2026-07-05T08:00:01.06+00:00 — Leo Moser (mole99) (@mole99)

Content

📢 Minor update!

It turns out that the changes to the density rules have not yet been upstreamed to Open PDKs from our legacy wafer.space PDK fork. This update addresses this issue.

- Project Template [1.5.7](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.5.7)
  - Update PDK to `d658698b`

- Precheck [1.7.1](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.7.1)
  - Update PDK to `d658698b`

The filler generation has already considered these rules. The platform will automatically rerun the latest precheck for your designs.
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message-1523237046557081650

2026-07-05T08:00:12.275+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1526579676183662662

2026-07-14T13:22:37.281+00:00 — Leo Moser (mole99) (@mole99)

Content

@everyone 📢 Critical update!

If you are using the community-created 3.3V standard cell library for your tapeout, please update your design, as the PDK update fixes a critical issue.

- Project Template [1.5.8](https://github.com/wafer-space/gf180mcu-project-template/releases/tag/1.5.8)
  - Update PDK to `f6eeac7d`
    - Fix an issue in `gf180mcu_as_sc_mcu7t3v3` regarding buffer cells.

- Precheck [1.7.2](https://github.com/wafer-space/gf180mcu-precheck/releases/tag/1.7.2)
  - Fix the text ID generation for narrow letters such as "I".

If there are any questions, please let us know.

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message-1526579702297526362

2026-07-14T13:22:43.507+00:00 — Leo Moser (mole99) (@mole99)

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Pinned a message.
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message-1526659423051972760

2026-07-14T18:39:30.416+00:00 — J-Lo (@crockpotveggies)

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This impacts us and while we have already updated, we are dealing with new timing violations. This is really inconvenient as we’re trying to make the deadline for Run2, what options do we have?
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message-1526659886006669503

2026-07-14T18:41:20.793+00:00 — Tholin (@tholin)

Content

What kinds of timing violations?
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message-1526662256363044999

2026-07-14T18:50:45.93+00:00 — Leo Moser (mole99) (@mole99)

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message-1526663711203524718

2026-07-14T18:56:32.791+00:00 — RebelMike (@rebelmike)

Content

Obvious thing to try would be to exclude the newly added cells (mux4_1, mux4_2, oai21_2, oai21_4) that incidentally got added in the same pdk update.  But if it's the improved timing of the buff_8 causing issues that is going to be harder to fix...
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message-1526669336884940930

2026-07-14T19:18:54.058+00:00 — J-Lo (@crockpotveggies)

Content

@Tholin taking a look now sorry it’s a long run from synth to pnr to gds so reports aren’t done yet on latest run
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message-1526670948449910886

2026-07-14T19:25:18.285+00:00 — J-Lo (@crockpotveggies)

Content

Takes around 12 hrs
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message-1526673524985430166

2026-07-14T19:35:32.579+00:00 — namibj

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Just use a buf2 into a buf4 maybe?
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message-1526701660397895763

2026-07-14T21:27:20.584+00:00 — Essen (@essen__)

Content

~~Hi, I think there is an issue with the default template for the 1x0.5 slot.
Seems to only have 54 IO pins, not the expected 56 :
https://github.com/wafer-space/gf180mcu-project-template/blob/33194e694f02a392dcf561d7d9fbcc70714cf3af/src/slot_defines.svh#L33-L47~~

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message-1526702181330321549

2026-07-14T21:29:24.784+00:00 — namibj

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message-1526702183775469608

2026-07-14T21:29:25.367+00:00 — namibj

Content

@Essen was so nice as to help with the project wrapper aspects for the _multiplexed e-test,_ but has run into breakage of some kind trying to set up the COB-supported default pad ring of the 1x0.5 slot.
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message-1526702315891982386

2026-07-14T21:29:56.866+00:00 — namibj

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message-1526702317339148359

2026-07-14T21:29:57.211+00:00 — namibj

Content

The repo where things are happening
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message-1526703292456108183

2026-07-14T21:33:49.697+00:00 — Essen (@essen__)

Content

~~Same for 0.5x0.5 it looks suss:
```
56 (48 IO + 8 power)
```
But there are only have 46 ? Is there something I am missing here ?~~
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message-1526707000593874995

2026-07-14T21:48:33.786+00:00 — Essen (@essen__)

Content

Ah ! I figure it out, I am in idiot 🤦 ( I really need to sleep more )
**It's clk and rst !**
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message-1526707027664048239

2026-07-14T21:48:40.24+00:00 — Essen (@essen__)

Content

Sorry for the noise.
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message-1526754604099043438

2026-07-15T00:57:43.346+00:00 — namibj

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this still applies though
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message-1534031841550536866

2026-08-04T02:54:51.959+00:00 — carlfk

Content

https://github.com/evezor/wafer_space_docker_based_starter_kit

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