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#📦-cob

1,374 Discord messages from 📐 - Designing/cob/channel.md.

Category: 📐 - Designing Channel ID: 1408134567491145728

Messages: 1,374

message-1408134952205291557

2025-08-21T17:05:34.488+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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message-1408165457587998800

2025-08-21T19:06:47.538+00:00 — Tholin (@tholin)

Content

Essentially, my goal for my next gf180 tapeout is it to ditch caravel and build a headless setup for my multi-project dies while also providing at least one analog output pin. In other words, I need a custom padring. And I heard there are people here already making progress towards such a thing.
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message-1408337109282066512

2025-08-22T06:28:52.491+00:00 — Leo Moser (mole99) (@mole99)

Content

You can create a custom padring using the [leo/padring](https://github.com/librelane/librelane/tree/leo/padring) (experimental) branch in LibreLane. I had a setup for gf180mcu lying around somewhere, will have to see if I can find it again.
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message-1408876101576556646

2025-08-23T18:10:38.268+00:00 — Andrew Wingate (@anfroholic)

Content

Is the padring you're referring to for wirebonding, or a wscp layout?
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message-1408887178238361610

2025-08-23T18:54:39.15+00:00 — Leo Moser (mole99) (@mole99)

Content

We focus on wire bonding. GF180MCU would also support solder bumps, but for that you need the MetalTop option afaik.

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message-1414653947137757204

2025-09-08T16:49:43.997+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I just found

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message-1415505394641666151

2025-09-11T01:13:04.901+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - Lots of discussion about padrings and such is happening here.
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message-1416131416068194324

2025-09-12T18:40:40.04+00:00 — Tholin (@tholin)

Content

I designed and ordered a PCB layout to let me test COB, even though I don't have a wire bonder yet.
But I'm increasingly ready to experiment!
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message-1416159889943695572

2025-09-12T20:33:48.741+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - Have you uploaded your PCB layout somewhere?
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message-1416161758074109972

2025-09-12T20:41:14.138+00:00 — Tholin (@tholin)

Content

Not yet
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message-1416174270127800391

2025-09-12T21:30:57.244+00:00 — Tholin (@tholin)

Content

Going to wait at least until the board house has reviewed the layout and declared it manufacturable
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message-1416465237292351649

2025-09-13T16:47:09.222+00:00 — Tholin (@tholin)

Content

Alright, no complaints so far and its mid-production. Hold on.
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message-1416465414539444244

2025-09-13T16:47:51.481+00:00 — Tholin (@tholin)

Content

https://cdn.discordapp.com/attachments/1355137289390391538/1416096601876987904/image.png?ex=68c6ebbb&is=68c59a3b&hm=fbb99a124cca8622f7dba83653df52c0276cb52851cbb75dda48164c1b6f1fc5

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message-1416465423179972629

2025-09-13T16:47:53.541+00:00 — Tholin (@tholin)

Content

Here's a preview
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message-1416471190457024738

2025-09-13T17:10:48.567+00:00 — urish

Content

Nice!
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message-1416482616827318283

2025-09-13T17:56:12.826+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - Where are you getting it manufactured?
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message-1416489217873150124

2025-09-13T18:22:26.638+00:00 — Tholin (@tholin)

Content

JLCPCB
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message-1416489327692742688

2025-09-13T18:22:52.821+00:00 — Tholin (@tholin)

Content

I selected ENIG so all the pads are gold-plated. Hopefully that will be enough.
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message-1416489348060418192

2025-09-13T18:22:57.677+00:00 — Tholin (@tholin)

Content

Its not actually too terribly expensive.
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message-1416489923875307671

2025-09-13T18:25:14.962+00:00 — Tholin (@tholin)

Content

JLC quotes $120 for 100 4-layer PCBs up to 100mm by 100mm with ENIG, which comes down to just $1.20 per board.
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message-1416490452558942399

2025-09-13T18:27:21.01+00:00 — tnt (@246tnt)

Content

But where do you get them wire bonded ?
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message-1416492242989744178

2025-09-13T18:34:27.882+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

FWIW - I finally got a contact at JLCPCB, will see if I can get to someone who can help with getting wire bonding offered.

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message-1416496816358166589

2025-09-13T18:52:38.258+00:00 — Tholin (@tholin)

Content

I am trying to obtain a wire bonder of my own
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message-1416496819868930078

2025-09-13T18:52:39.095+00:00 — Tholin (@tholin)

Content

https://github.com/AvalonSemiconductors/gf180mcu_cob/tree/main/COB_test_board

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message-1416497994567651518

2025-09-13T18:57:19.165+00:00 — Tholin (@tholin)

Content

Based on the RISC-V core on my multi-project die
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message-1416498051094417508

2025-09-13T18:57:32.642+00:00 — Tholin (@tholin)

Content

Outside of the COB, the rest of the PCB is as simple and bodge-able as possible.
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message-1416498065962962997

2025-09-13T18:57:36.187+00:00 — Tholin (@tholin)

Content

Just in case
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message-1416509340440854589

2025-09-13T19:42:24.232+00:00 — urish

Content

Have you ever tried working with a wire bonder?
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message-1416509446993084598

2025-09-13T19:42:49.636+00:00 — urish

Content

@stuart and Matt did in the past, and it was... pretty challenging
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message-1416543211647668235

2025-09-13T21:56:59.757+00:00 — Tholin (@tholin)

Content

Well, practice makes perfect, right?
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message-1416582167223341066

2025-09-14T00:31:47.49+00:00 — BreakingTaps (@polyfractal)

Content

can confirm they are pretty hateful machines 😅
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message-1416582281468055563

2025-09-14T00:32:14.728+00:00 — BreakingTaps (@polyfractal)

Content

fun while working, very frustrating when not
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message-1418673893131943966

2025-09-19T19:03:33.809+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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message-1418673895405387788

2025-09-19T19:03:34.351+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate was playing with some castellated edge boards.
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message-1418674790805278864

2025-09-19T19:07:07.831+00:00 — urish

Content

Nice! One power domain?
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message-1418678587808288878

2025-09-19T19:22:13.107+00:00 — tnt (@246tnt)

Content

What's the pitch on those ?   1.27 mm ? or 1 mm ?
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message-1418679018793730068

2025-09-19T19:23:55.862+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I think 1mm but have to wait for what @Andrew Wingate says
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message-1418683822073057292

2025-09-19T19:43:01.053+00:00 — Andrew Wingate (@anfroholic)

Content

Yes, the pitch is 1mm as shown.
I hadn't realized how large the ring for the bonding wires was so there's a lot more room than I had thought.

All this is a bit of an exploration into what's the best form factor for:
- ease of use
- easiest for the wire bonders themselves
- if you want many of them

I am open to suggestions.
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message-1418686679597711536

2025-09-19T19:54:22.34+00:00 — Tholin (@tholin)

Content

tbh that COB footprint I made could be scaled down. The power/ground rings can be closer to the die, I think.
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message-1418687962530578573

2025-09-19T19:59:28.215+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Sounds great. Thank you for the baseline. I am just playing around a bit.
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message-1418688113605349509

2025-09-19T20:00:04.234+00:00 — tnt (@246tnt)

Content

@Andrew Wingate Also see https://discord.com/channels/1361349522684510449/1418540236148838461 thread which has the pad frame and how it should be bonded out.
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message-1418688156890304552

2025-09-19T20:00:14.554+00:00 — Andrew Wingate (@anfroholic)

Content

This whole panel is 100mm on a side.
and from what I've seen should fit in the wire bonding machines I've seen.

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message-1418688760626937947

2025-09-19T20:02:38.496+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell What's the die thickness ? Are they going through thinning ?
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message-1418689505623408652

2025-09-19T20:05:36.117+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I am seeing 64 pins?
Is that what we should be shooting for.
I was under the assumption there were no hard standards and was shooting for something that could cover most use cases while being easy for people to work with.
There were also some suggestions for this same kind of thing but with .1" spacing and the ability to breadboard.

Is there interest in that variation as well?
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message-1418689857387233380

2025-09-19T20:06:59.984+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Not currently planned as it is quite expensive in very low volume.
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message-1418689982721167510

2025-09-19T20:07:29.866+00:00 — tnt (@246tnt)

Content

So around 750um then ?
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message-1418690030460731403

2025-09-19T20:07:41.248+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I don't think people can access that thread?
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message-1418690081358614529

2025-09-19T20:07:53.383+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I can see it
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message-1418690122332766240

2025-09-19T20:08:03.152+00:00 — urish

Content

Same
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message-1418690140238381229

2025-09-19T20:08:07.421+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Maybe just my phone being weird?
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message-1418690147557445732

2025-09-19T20:08:09.166+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell why not ? It's in #general in this discord.
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message-1418690455574548651

2025-09-19T20:09:22.603+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - I would definitely like to have some DIP style templates. I believe @ReJ aka Renaldas Zioma needs that for the z80?

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message-1418690828318150697

2025-09-19T20:10:51.472+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Just seems to be some weirdness of the phone client, working now. Sorry.
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message-1418690960283668590

2025-09-19T20:11:22.935+00:00 — Tholin (@tholin)

Content

The current COB footprint is too large to fit a DIP footprint
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message-1418690989392138271

2025-09-19T20:11:29.875+00:00 — Tholin (@tholin)

Content

I’ll need to make a new one
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message-1418691020853608659

2025-09-19T20:11:37.376+00:00 — Tholin (@tholin)

Content

But as it stands, I can’t even test the current one
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message-1418691059289948181

2025-09-19T20:11:46.54+00:00 — Tholin (@tholin)

Content

Still do not own a wire bonder and won’t for a few more months
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message-1418694550536454226

2025-09-19T20:25:38.918+00:00 — Tholin (@tholin)

Content

But, theoretically, should be possible. After all, the dies are of the right dimension to fit inside one of those ceramic DIP carriers.
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message-1418695730406621357

2025-09-19T20:30:20.221+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell So you want one pad frame but different breakout options ?
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message-1418696013170085889

2025-09-19T20:31:27.637+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

Just for reference, this is what it looks like currently.
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message-1418696022020063284

2025-09-19T20:31:29.747+00:00 — Andrew Wingate (@anfroholic)

Content

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message-1418696202756554882

2025-09-19T20:32:12.838+00:00 — tnt (@246tnt)

Content

That's definitely not bondable. Wires can't be at more than 45 deg.
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message-1418696312769085473

2025-09-19T20:32:39.067+00:00 — tnt (@246tnt)

Content

Ah wait, nm, that footprint is not the die itself, forget it.
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message-1418696650351710333

2025-09-19T20:33:59.553+00:00 — Andrew Wingate (@anfroholic)

Content

I was more making a visual model than anything concrete, just trying to engage some conversation and see if there are opinions so I may gather a consensus of sorts.
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message-1418697631592480950

2025-09-19T20:37:53.499+00:00 — Tholin (@tholin)

Content

Okay, I don’t think it needs to be scaled down much to fit routing to the pins

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message-1418699608548446269

2025-09-19T20:45:44.842+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - I think there are missing traces from the bond pads to the edge pads?
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message-1418699754497507472

2025-09-19T20:46:19.639+00:00 — Andrew Wingate (@anfroholic)

Content

correct, there are no traces on anything
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message-1418700122178588702

2025-09-19T20:47:47.301+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Eventually, multiple standard templates for everything and it being someone else's problem 😛
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message-1418700380425949235

2025-09-19T20:48:48.872+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But in the short term, one or two pad frames and one or two breakouts.
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message-1418706257287712849

2025-09-19T21:12:10.025+00:00 — Tholin (@tholin)

Content

For reference, this is what it looks like inside an actual DIP-40 ceramic carrier.
https://www.spectrum-semi.com/sites/default/files/pdfs/CSB04079.pdf
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message-1418708444805861496

2025-09-19T21:20:51.57+00:00 — Tholin (@tholin)

Content

Relevant section. I believe I can design a COB footprint based on these dimensions. I also have diagrams for DIP-48 and DIP-64 carriers to reference if more pads are needed.

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message-1419394972049739929

2025-09-21T18:48:52.42+00:00 — Tholin (@tholin)

Content

Done!

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message-1419435114034892851

2025-09-21T21:28:23.015+00:00 — Tholin (@tholin)

Content

Well, that works!

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message-1419842938753777804

2025-09-23T00:28:56.005+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - Cool! What size is that?
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message-1419843043443605624

2025-09-23T00:29:20.965+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - What design rules does that end up being?
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message-1419950892521623604

2025-09-23T07:37:54.189+00:00 — Tholin (@tholin)

Content

Its JLCPCB’s two-layer PCB rules
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message-1419950940022116484

2025-09-23T07:38:05.514+00:00 — Tholin (@tholin)

Content

Its basically just a DIP-40 carrier, but on PCB
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message-1420145349531533373

2025-09-23T20:30:36.353+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tholin - Link to repo?
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message-1420145840852308099

2025-09-23T20:32:33.493+00:00 — Tholin (@tholin)

Reply/reference

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https://github.com/AvalonSemiconductors/gf180mcu_cob

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message-1420147151727755325

2025-09-23T20:37:46.03+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Awesome, thanks!
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message-1420175492455202929

2025-09-23T22:30:22.986+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I wonder if you could "drop" the chip in a cut out to make the whole thing flatter, bond wires shorter.....
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message-1420218723721281667

2025-09-24T01:22:10.123+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

4-layer PCB, and a die-shaped hole milled out of the top substrate, you mean?
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message-1420227212182949969

2025-09-24T01:55:53.93+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@algofoogle (Anton Maurovic) - yeah, something like that
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message-1420270333113532436

2025-09-24T04:47:14.761+00:00 — urish

Content

How would that work with the epad?
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message-1420273511741521952

2025-09-24T04:59:52.605+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@urish - You mean the backside silicon connection? I believe you can still have pads in the hole.

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message-1420274242338947073

2025-09-24T05:02:46.793+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Is the back of the die electrically connected, though? I don’t think it was in the Efabless runs (or at least not intentionally); @Tim Edwards ?
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message-1420274537013968907

2025-09-24T05:03:57.049+00:00 — Leo Moser (mole99) (@mole99)

Content

No, it should be not. The epad refers to QFN packaging and is also wire bonded.
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message-1420275050573070387

2025-09-24T05:05:59.491+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Btw, I think the hole I was talking about is called a “PCB Cavity”, and there are different ways to do it and different options supported.

https://www.pcbway.com/blog/PCB_Basic_Information/What_is_Cavity_PCB_0882350d.html

Related: die embedding

https://www.pcbway.com/blog/Engineering_Technical/Use_Embedded_Components_To_Improve_PCB_Performance_And_Reduce_Size.html
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message-1420282001503555595

2025-09-24T05:33:36.722+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Yeah PCB Cavity is proper name.
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message-1420282609358995459

2025-09-24T05:36:01.646+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

They have an picture on that last page like this

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message-1420580092513615902

2025-09-25T01:18:07.157+00:00 — BreakingTaps (@polyfractal)

Content

oooh that's interesting re: image sensors, since it'd provide some protection to the bond wires without encapsulation
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message-1420857467558170655

2025-09-25T19:40:18.521+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

BTW - People here might be interested in the discussions in #🏗️-die-sorter as well.
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message-1421032040920383489

2025-09-26T07:14:00.054+00:00 — jbowen (@jwbowen)

Reply/reference

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*(sorry, I was just directed here by someone chatting about garage phabs and just wanted to say I'm a fan of your videos! I'll go back to being a normal person now)*

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message-1421183481156862017

2025-09-26T17:15:46.22+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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Started a thread.
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2025-10-02T20:28:35.425+00:00 — m_w (@mwelling)

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ah I have not been paying attention here 🙂
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message-1424108533766688861

2025-10-04T18:58:53.107+00:00 — Andrew Wingate (@anfroholic)

Content

Another option could be mezzanine connectors (similar to the Raspberry pi compute module)
The connectors are sub $0.10 each.

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message-1424109062542331964

2025-10-04T19:00:59.177+00:00 — urish

Content

We're planning to use those in Tiny Tapeout
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message-1424109087670669412

2025-10-04T19:01:05.168+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Andrew Wingate - My understanding was those connectors tend to be hugely expensive in anything but 100k units (which is why everyone ends up using PCIe or other similar connectors) but maybe things have changed?
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message-1424109287223066674

2025-10-04T19:01:52.745+00:00 — Andrew Wingate (@anfroholic)

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https://www.lcsc.com/product-detail/C2763968.html
Nah, they seem to be available and cheap

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message-1424109412632756412

2025-10-04T19:02:22.645+00:00 — urish

Content

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message-1424113420147359754

2025-10-04T19:18:18.111+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Cool! Maybe we should offer that as a COB optoin then?
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message-1424113601286897785

2025-10-04T19:19:01.298+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@urish - You going to annoy @carlfk by making the board size/shape change again? So he has to redo the mounting for tt.fpgas.online ? 😛

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message-1424113794615087105

2025-10-04T19:19:47.391+00:00 — urish

Content

What exactly are you referring to with "that"?
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message-1424113890601472051

2025-10-04T19:20:10.276+00:00 — urish

Content

yes, we figured out the current 2x2x20 DIP headers is pretty bad UX
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message-1424114744263966891

2025-10-04T19:23:33.805+00:00 — Andrew Wingate (@anfroholic)

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> So he has to *[tell @Andrew Wingate]* to redo the mounting for tt.fpgas.online
ftfy 😝

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message-1424115266706735244

2025-10-04T19:25:38.365+00:00 — Andrew Wingate (@anfroholic)

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Content

Carl has a rack of tiny tapeout boards connected to raspberry pis and cameras that are accessible to play with remotely.
Every version of TTO boards you all have released has a different layout for the mounting holes
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message-1424115420725645312

2025-10-04T19:26:15.086+00:00 — urish

Content

I was asking about
> Cool! Maybe we should offer **that** as a COB optoin then?
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message-1424116050072436877

2025-10-04T19:28:45.134+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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To have the dies mounted to a PCB and have a mezzanine connector on the back opposed to castellated or dip options.
What form factor works best for people to use? What would they like (and at what scale?)

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message-1424116286484381778

2025-10-04T19:29:41.499+00:00 — Andrew Wingate (@anfroholic)

Content

These mezzanine connectors can be hand soldered as well, they're available and inexpensive, so think it sounds viable

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message-1424127082279075950

2025-10-04T20:12:35.417+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate - I think we just need to create some options and give them a go
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message-1424335698646929530

2025-10-05T10:01:33.435+00:00 — Andrew Wingate (@anfroholic)

Content

Example of a mezzanine connected COB
This would probably be the one I'd choose. Example has 40 pins, but there's room for a lot more.

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message-1424336512035590156

2025-10-05T10:04:47.362+00:00 — urish

Content

Looks nice - though, having the connector exactly in the middle means that you have better chances of inserting it in the wrong orientation
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message-1424336957390979163

2025-10-05T10:06:33.543+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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That's why I put the pin1 designator 😜
But good call. Not sure how the best way to do that would be. Even if it's offset still doesn't help.
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message-1424337511982829740

2025-10-05T10:08:45.768+00:00 — urish

Content

yes, pin1 helps but it requires you to pay extra attension
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message-1424337641087963237

2025-10-05T10:09:16.549+00:00 — urish

Content

I imagine most carrier boards will have some rect marked where you insert the daugtherboard.
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message-1424337783274868757

2025-10-05T10:09:50.449+00:00 — urish

Content

So if you tried to insert it wrong orientation, the offset would cause these not to match (and in some cases, the daugther board might get of of the host board boundaries)
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message-1424337860906979369

2025-10-05T10:10:08.958+00:00 — urish

Content

so it's not full-proof either, but it gives you another cue that you did something wrong.
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message-1424337969648500809

2025-10-05T10:10:34.884+00:00 — urish

Content

If this wasn't BOM sensitive, I'd suggest just using two smaller connectors (20+30?), then this would be pretty much foolproof
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message-1424338064406478919

2025-10-05T10:10:57.476+00:00 — Andrew Wingate (@anfroholic)

Content

I was thinking that.
I could also make a footprint that already contains all that so people don't need to reinvent.
I also thought maybe knocking a corner off, or a hole
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message-1424338298666618941

2025-10-05T10:11:53.328+00:00 — urish

Content

Yep, corner could also help here
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message-1424338383127445545

2025-10-05T10:12:13.465+00:00 — urish

Content

I think there are also keyed connnectors, but they are probably more expensive
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message-1424338586291142697

2025-10-05T10:13:01.903+00:00 — Andrew Wingate (@anfroholic)

Content

If we do put it way over to the side there could  be a warning message that says something
*DANGER*
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message-1424338622957486122

2025-10-05T10:13:10.645+00:00 — Andrew Wingate (@anfroholic)

Content

only shows when it's reversed
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message-1424338968366940223

2025-10-05T10:14:32.997+00:00 — aedancullen

Content

do it like Intel Edison
corner/side connector placement and maybe throw a single M2 hole on the opposite corner or something
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message-1424339709630611517

2025-10-05T10:17:29.728+00:00 — Andrew Wingate (@anfroholic)

Content

Something like this maybe?

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message-1424350788909793282

2025-10-05T11:01:31.234+00:00 — tnt (@246tnt)

Content

I would definitely like to see such a connector for the default pad frame of the example project and that would include the decoupling caps and separate io/core voltage on the power pins.

And yes, if it's in the middle it can be inserted backward but then same for a QFN that can be soldered at wrong orientation or a DIP inserted backward ... when it's on the edge the routing of sigcal can become a pain. You could actually just notch the PCB (or put a couple of hole) and put a pin header on the main board to prevent wrong orientation while keeping it in the center.

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message-1424389555842187425

2025-10-05T13:35:33.991+00:00 — Andrew Wingate (@anfroholic)

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Content

I  think we can find something much more elegant, but I love the idea!!

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message-1424391460282695692

2025-10-05T13:43:08.045+00:00 — Tholin (@tholin)

Content

I should maybe prepare a padring config template that's designed to work with my 40-pin COB footprint
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message-1424391713920909512

2025-10-05T13:44:08.517+00:00 — Andrew Wingate (@anfroholic)

Content

Also does anyone have a suggestion for the number of pins?
50p would fit fine. There's not really any extra cost for extra even if they're unused.
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2025-10-05T13:44:56.797+00:00 — Andrew Wingate (@anfroholic)

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I guess maybe wait?? Tim was saying there may be a couple version of padrings?
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message-1424399703893872741

2025-10-05T14:15:53.475+00:00 — tnt (@246tnt)

Content

@Andrew Wingate Default pad frame needs more than 50 pins 🙂
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message-1424400896057671842

2025-10-05T14:20:37.709+00:00 — Andrew Wingate (@anfroholic)

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There's a fairly significant jump going to 60 pins. Is that adequate?
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message-1424401363147821138

2025-10-05T14:22:29.072+00:00 — tnt (@246tnt)

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Significant jump of what ?
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message-1424401428721696898

2025-10-05T14:22:44.706+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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price and availability
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message-1424401491111972876

2025-10-05T14:22:59.581+00:00 — tnt (@246tnt)

Content

2x30 ? 🙂 or 2x40 ...
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message-1424401570812006493

2025-10-05T14:23:18.583+00:00 — Andrew Wingate (@anfroholic)

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So, 60 is the target?
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message-1424401593213649006

2025-10-05T14:23:23.924+00:00 — tnt (@246tnt)

Content

or 30 + 40 will also prevent wrong way insertion ...
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message-1424401951117934674

2025-10-05T14:24:49.255+00:00 — tnt (@246tnt)

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Actually ideally it'd be like 70 ( well don't think there is anything between 60 and 70 ) so you can put a couple more ground pins in there and double up the power ...
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message-1424402359517188226

2025-10-05T14:26:26.625+00:00 — Andrew Wingate (@anfroholic)

Content

The price and availability is pretty flat up to 50 pins, so if there are 2, 90 is also probably fine?
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message-1424402480774512842

2025-10-05T14:26:55.535+00:00 — tnt (@246tnt)

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Sure more is never an issue 😅

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message-1424402557186347028

2025-10-05T14:27:13.753+00:00 — Andrew Wingate (@anfroholic)

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Then depending on what Tim wants to do he has some high pin count for some of the less complex COB if desired
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message-1424403025425989642

2025-10-05T14:29:05.39+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Can you point me to where I can find the default pad frame?
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message-1424403583843041291

2025-10-05T14:31:18.527+00:00 — tnt (@246tnt)

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https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?usp=sharing

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message-1424403774889398282

2025-10-05T14:32:04.076+00:00 — tnt (@246tnt)

Content

That's the TT padframe that was picked as the default pad frame for the user project ( except all the "names" are irrelevant, just that signal pins are signal pins and power/ground pins are power/ground pins ).
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message-1424409208249389136

2025-10-05T14:53:39.49+00:00 — Andrew Wingate (@anfroholic)

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@tnt Something more like this then?

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message-1424409552115339417

2025-10-05T14:55:01.474+00:00 — tnt (@246tnt)

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Yup.

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message-1424410252027236474

2025-10-05T14:57:48.346+00:00 — Tholin (@tholin)

Content

Do I create a COB footprint based on this padring from a DIP-64 ceramic carrier?

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message-1424410410555150509

2025-10-05T14:58:26.142+00:00 — Tholin (@tholin)

Content

Pro: would be compatible with real DIP carriers
Con: requires awkward padring setup on the die
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message-1424418105194451026

2025-10-05T15:29:00.687+00:00 — Xobs (@xobs)

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I thought it was generally not advisable to use multiple of those kinds of connectors because then SMT alignment becomes an issue, and the tolerance for alignment gets very tight.
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message-1424419587604222152

2025-10-05T15:34:54.121+00:00 — Andrew Wingate (@anfroholic)

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That is a valid concern
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message-1424478118143332385

2025-10-05T19:27:28.889+00:00 — Tim 'mithro' Ansell (@mithro_)

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I don't think you should underestimate SMT alignment issues with multiple connectors.
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message-1424478516287639572

2025-10-05T19:29:03.814+00:00 — Tim 'mithro' Ansell (@mithro_)

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Well, it is 1c per wire bond and you need one wire bond per pad at least. So 80 pins doubles the cost from 40 pins.
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message-1424479116370907198

2025-10-05T19:31:26.885+00:00 — Tim 'mithro' Ansell (@mithro_)

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Frequently people seem to double bond power stuff.
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message-1424498636557123604

2025-10-05T20:49:00.86+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

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Supporting customers at Efabless, 64 pins on Caravel and even OpenFrame was always a bit limiting. That’s why I was excited when 74 was described for the TT default padframe
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message-1424685824582090793

2025-10-06T09:12:49.963+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@algofoogle (Anton Maurovic) - I've pondered a bit about how people are using all these pins
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message-1424687568569761874

2025-10-06T09:19:45.762+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell When you want to test things, you often try to export internal signals to have some visibility and you can quickly run out that way.
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message-1424688212864929823

2025-10-06T09:22:19.374+00:00 — tnt (@246tnt)

Content

In the pad frame above, only 56 are actual user IO, rest is power/ground ( multiple rails, multiple bond per rail ).
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message-1424688439852273765

2025-10-06T09:23:13.492+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

I think that is why we need to create a decent internal logic analyser / oscilloscope
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message-1424689238217068595

2025-10-06T09:26:23.837+00:00 — tnt (@246tnt)

Content

Both of these need memory ... which is huge on-chip ...
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message-1424690521825214466

2025-10-06T09:31:29.873+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Yeah, having better memory options/solutions would help with that.
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message-1424690634475831356

2025-10-06T09:31:56.731+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

And better connectivity like high speed USB and such
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message-1424691096184688682

2025-10-06T09:33:46.811+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

However, we are not there yet with such things.
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message-1425123434593259611

2025-10-07T14:11:44.32+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt I've been playing in my mind with the number of pins you're looking for and how to best accomplish that.
On one hand we just have the sheer number of pins and I am not sure how  many wire bonds @Tim 'mithro' Ansell is wanting to let people have.

That said, the picture here has 78pins and there is some room for some other things as well--and/or instead.
Instead could also just be testpoints. They don't need to be brought down to the main PCB board and can remain on the COB

Another idea, is to have some solderable jumpers or 0R resistors that can bridge a pin from the COB to the pcb.

And finally if something like the solderable jumper is a viable option, is there some way to have the same effect on the die itself with a MUX or the like. I am trying to wrap my head around the actual utility here. There are *user_pins* and *power_pins* I can understand the desire for more pins, but don't know what that means in practice and if it could/should be more *shared_pins*

Thanks

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message-1425166259611504783

2025-10-07T17:01:54.6+00:00 — RebelMike (@rebelmike)

Content

I asked in the discord of another product (tinyclunx) that uses two of these connectors about alignment issues, this was the reply FWIW:
"As in the 2 DF40 Hirose connectors being misaligned/slightly rotated?
So far, have not seen anything liek this. Have got fabrication done at the local SMT, Elecrow and JLCPCB. All have been perfect over more than 100 units. These connectors seem to self align with solder surface tension. I could see them moving to the right spot when hand placing them and reflowing.
PS: these connectors are used in very high volume products so am sure they've been optimized for self alignment. Must have ENIG plating for this pitch to help."
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message-1425168528067006495

2025-10-07T17:10:55.442+00:00 — tnt (@246tnt)

Content

@Andrew Wingate Of those 74 bond pads it's important to note only 56 are "user io". The other being power and if you include decaps on board that means you could probably get by with only say 1 power pin per rail on the breakout and maybe 4 gnd pads. So that's "only" 63 external castellated pins.

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message-1425168817855922176

2025-10-07T17:12:04.533+00:00 — tnt (@246tnt)

Content

The chips needs several bond pads for power because the rings inside the chip are not that good of a conductor, a PCB trace is much better to move power around and feed it at several place around the die. But to connect to the "mother board" you don't necessarely need multiple castellated pins.
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message-1425169457751523561

2025-10-07T17:14:37.096+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I see, thank you. I think I am understanding a bit better now.
Any ideas on how many decoupling caps? I am assuming a few .1uF?
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message-1425169825629736980

2025-10-07T17:16:04.805+00:00 — tnt (@246tnt)

Content

I'd go with a couple of 1uf for each rail.

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message-1425262751584092332

2025-10-07T23:25:20.079+00:00 — Andrew Wingate (@anfroholic)

Content

I put together a few numbers so we can get a feel for the cost to put dies on COB to present to you all and @Tim 'mithro' Ansell

**COB Cost Breakdown**
```
| Item              | Price (1k COB) | Each     | Notes / Link |
|-------------------|----------------|----------|---------------|
| **PCB**           | $45.00         | $0.0450  | PCB cost is always needed — assumed 6×6 grid @ qty 30 panels |
| **Wire Bond**     | $500.00        | $0.5000  | For 50 wirebonds |
| **Castellated**   | $100.00        | $0.1000  | Extra cost on top of other PCB cost |
| **70p Mezzanine** | $291.20        | $0.2912  | [LCSC C19089236](https://www.lcsc.com/product-detail/C19089236.html) |
| **60p Mezzanine** | $247.40        | $0.2474  | [LCSC C294544](https://www.lcsc.com/product-detail/C294544.html) |
| **50p Mezzanine** | $83.20         | $0.0832  | [LCSC C2763977](https://www.lcsc.com/product-detail/C2763977.html) |
| **1µF Decap**     | $11.60         | $0.0116  | Assume 4 per COB |
| **Assembly Fees** | $50.00         | $0.0500  | 1¢ per component |
```
The general idea is that COB will be panelized in ~100mmx100mm panels. Some components can be put on the pcb before (or after) the die like connectors--mezzanine most likely--and decoupling caps reducing the number of pins that may need to connect to the motherboard like TinyTapeout and @tnt with high pinout demands would like.

Please let me know if there are any other variations anyone would be looking for and/or interested.
DIP like @Tholin has been working on are still available too, but didn't really have a place on this sheet I don't think
link to spreadsheet https://docs.google.com/spreadsheets/d/17oUlsN1SRM1lt5fsIiS17jE1C9ZgoKSnC5zECYs8Bc4/edit?gid=0#gid=0

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message-1425522277503602728

2025-10-08T16:36:35.88+00:00 — asc (@asc9742)

Content

Hi, nice to meet you all. My name is Andrew and my team and I are very excited to start work on porting the MOSbius chip (mosbius.org) to GF180 with the wafer.space project. I have just now started working on this project so please forgive my ignorance in the following questions.
1) I recall from a previous email chain that @Tim 'mithro' Ansell had kindly let us know that we can use our own padframe. Is that still true for the COB option ($8500), or is there a default padframe we would need to follow?
2) If we can use our own padframe, I’m assuming we would also need to design the wire bond as well?
3) For the default padframe that @tnt mentioned above with the 56 “user io” bond pads, can that be generated with the following template? https://github.com/wafer-space/gf180mcu-project-template
4) Would the template also generate a seal ring? We had an issue with the 2025 Chipathon where a seal ring was not generated with the padframe. I believe GF will end up adding the seal ring for us.
Apologies for the many questions. I would greatly appreciate your time and help clearing these questions up for us. Thank you.

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message-1425523958123335831

2025-10-08T16:43:16.571+00:00 — tnt (@246tnt)

Content

@asc for (3), yes, the default padframe in that template is the one I was talking about.

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message-1425533983294226453

2025-10-08T17:23:06.758+00:00 — asc (@asc9742)

Content

@tnt are all the "user" type pads a single type of pad (Analog, digital, bidirectional, etc) ? I noticed that the pads have different "TT Function"s but I'm assuming that is specific only to the TT padframe?
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message-1425534208587071508

2025-10-08T17:24:00.472+00:00 — tnt (@246tnt)

Content

The "TT" function is just for TT. In the template above they have some type defined, but you can pick/change to whichever you need for your needs.

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message-1425534515178110986

2025-10-08T17:25:13.569+00:00 — asc (@asc9742)

Content

I see, thank you
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message-1425547801068048404

2025-10-08T18:18:01.172+00:00 — Leo Moser (mole99) (@mole99)

Content

@asc 1) Yes, the CoB option for $8500 uses the default padring. You can change the I/O pad types, put you shouldn't change the number of pads, as this would change the position of the bondpads.

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message-1425596171669471292

2025-10-08T21:30:13.622+00:00 — asc (@asc9742)

Content

Hi all, is the config.yaml file the only file I would need to alter to generate a custom padframe? Also, of the 74 pads, are all of them fair game to customize?
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message-1425698647798186084

2025-10-09T04:17:25.835+00:00 — peterkinget

Content

Hi Everyone,

We just got into the wafer.space design, so excuse me if I ask questions that have been answered. Looked around a bit but I am left with the following question.

I was talking to @asc and he mentioned that you are developing a template with 74 pads; ( 20 + 17 ) x 2

The reticle is sqrt(20) so about 4.5mm on the side (although maybe the reticle is rectangular). In any case 20 pads on 4 mm would mean 200um center-to-center pitch. That sounds large. Obviously we do not need to push is to 50um which likely might not work for COB, but what is the guideline for the COB?

What is the center-to-center pitch on the PCB pads?

74 pads would work for out MOSbius chip (https://mosbius.org) , but more pins can always be put to very good use for our application ...

Finally, we would like a version which is dual in line style so we can put it in a breadboard. You can see our current PCB (with a chip in a package) attached.

@Tim 'mithro' Ansell  So how would we go about this? Do all the designs in the run use the same # pins and positions for the COB at 8,500. Or if we do the designwork of the PCB, can we make our own, or does that come at a higher cost?

Many thanks! Looking forward to be part of this exciting opportunity for cheap 'packaged' silicon. For those that have paid for chip packaging they probably realize that silicon cost is one thing, packaging is a whole other painful expense ...

-- Peter Kinget
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message-1425749959227080724

2025-10-09T07:41:19.433+00:00 — Leo Moser (mole99) (@mole99)

Content

Hi Peter,

Yes, there is the default template which has 74 pads, 54 of which are used for signals.
The $8,500 USD option with CoB packaging can only be used with this exact padframe, since the setup cost is shared across all designs.

While you should not change the position of any pads, you can change the pad types. For example, all of the 54 pads could be used for analog. The remaining 20 pads are used for power and ground and should not be changed, since they will be connected to the power/ground rings of the CoB footprint on the PCB.

If you do your own packaging, you could fit more pads into the padframe, or remove the padframe completely - this is up to you.

I believe there are different daughter boards in development in the #📦-cob channel.

- Leo

@Tim 'mithro' Ansell would it be possible for someone to design their own padframe and choose the CoB option? What would the additional cost be?

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message-1425756428513312768

2025-10-09T08:07:01.831+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I'm open to potentially having more options around pad frames / PCBs if we can make them come in within the required budget.

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message-1425898130892652668

2025-10-09T17:30:06.311+00:00 — asc (@asc9742)

Content

@Leo Moser (mole99) The padframe template seems to have 56 user pads and 18 power/ground pads instead of the 20power/ground you mentioned. Can you confirm the correct number?

Is there some sort of guide I can follow to switch out the different IO types? I am getting lost in what needs to be done in the system verilog and yaml files to generate a custom padframe.

Looking at the system verilog files, it seens that the BIDIR pads are actaully digital pin cells "gf180mcu_fd_io__bi_24t".
Is it possible to use the analog pin cells "gf180mcu_fd_io__asig_5p0" instead?

Thank you, Andrew

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message-1425899431441596546

2025-10-09T17:35:16.386+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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You're absolutely right! I only counted the INPUT and BIDIR pads in the template, but we also have a clock and reset. So, 56 user pads and 18 power/grounds pads is right.
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message-1425899773658927197

2025-10-09T17:36:37.977+00:00 — Leo Moser (mole99) (@mole99)

Content

Basically, you just instantiate a different pad type in the Verilog and swap out the instance name in the LibreLane config.yaml
Let me know if you encounter any issues.
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message-1425900031424204870

2025-10-09T17:37:39.433+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, the bidir pads are digital input/output pads. You can swap them against the analog pad you mentioned.
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message-1425900208881139713

2025-10-09T17:38:21.742+00:00 — asc (@asc9742)

Content

Sounds good, thank you

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message-1425904251569180734

2025-10-09T17:54:25.594+00:00 — peterkinget

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Content

How do we go about this. Given the time constrains we will start with the standard for now, but for MOSbius we need pins, pins, pins ... So it would be great if you could take a stab at trying to increase the # of pins.

Also we need analog pads, i.e.  only ESD and no buffers or other active components in the pads.

Finally our need for VDD/VSS pads is less since we are operating at lower frequencies so we can worry a bit less about bondwire inductance.
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message-1425904492536397824

2025-10-09T17:55:23.045+00:00 — peterkinget

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Content

What is the pad type for a basic analog pad: only ESD and no active components like buffers etc.
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message-1425906078591225878

2025-10-09T18:01:41.19+00:00 — peterkinget

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Thank you, Leo. There are 74 pads. Fully understood that location should not change, so that the bonding setup is the same for all. I can assign the type of the pads as I see fit. But I have to assign 20 to VDD/VSS. Can I change the location of those 20 pads or they are fixed?
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message-1425906189786415125

2025-10-09T18:02:07.701+00:00 — tnt (@246tnt)

Content

They're fixed.
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message-1425906266521341952

2025-10-09T18:02:25.996+00:00 — tnt (@246tnt)

Content

The idea is those power pads will get bonded to the various power rails in the "common" bonding setup.

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message-1425906798996750402

2025-10-09T18:04:32.948+00:00 — tnt (@246tnt)

Content

The analog pads don't have buffer no. Just ESD diodes to both the `DVDD` and `DVSS` ( which are IO voltages )
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message-1425907363961114785

2025-10-09T18:06:47.646+00:00 — asc (@asc9742)

Content

@peterkinget  I will try to use the template to generate the analog pads from the Chipathon for the design. (https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/IO/gf180mcu_fd_io/datasheet.html) They only have double diode protection. No buffers.

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message-1425907952375693312

2025-10-09T18:09:07.935+00:00 — tnt (@246tnt)

Content

Of course if you have your own packaging provider, you can do whatever you want and just get dies 🙂  I guess you had to have the other mosbius chips packaged somehow 😅
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2025-10-09T18:13:40.733+00:00 — asc (@asc9742)

Content

@tnt we cant say no to 1.5$ per chip for packaging 😆

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2025-10-09T21:28:21.873+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@asc / @peterkinget - I'm hoping that the stuff behind the $1.5 per chip packaging will be available generally in the future for any bare die packaging through the PCBA houses, then you can choose how much you want to pay, like $0.10 for 6 wire bonds and a $0.04 PCB or $5.00 for 400 wire bonds and $1.00 PCB.
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2025-10-09T21:28:45.745+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

And then wafer.space can ignore packaging stuff 🙂
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2025-10-09T21:29:31.112+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

The general costs are the PCB and ~$0.01 per bond.
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2025-10-09T21:31:30.351+00:00 — Tim 'mithro' Ansell (@mithro_)

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If you can create a PCB design + padframe which is open source and under the budget amount and the PCBA house is happy with, then I'm willing to try and make it happen and publish as an example/template for others to reuse.
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2025-10-09T21:32:56.064+00:00 — Tim 'mithro' Ansell (@mithro_)

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The people in this channel are probably the best people to help you figure out if you can make it work l.
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2025-10-09T22:47:36.056+00:00 — asc (@asc9742)

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Sounds good. We may give that a try. Given the time constraint, this might be a project for a future run.
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message-1425993215743496405

2025-10-09T23:47:56.306+00:00 — dshadoff

Content

Are the bare dies really that resilient to feed into pick-and-place ?  I always understood that they were very sensitive and needed special tools for handling the dies without damaging them
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2025-10-09T23:48:48.426+00:00 — dshadoff

Content

(If we are talking about places like JLC doing mounting in the future)
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2025-10-10T14:42:03.764+00:00 — Andrew Wingate (@anfroholic)

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While they're talking about having a company like JLC do the wire bonding, I wouldn't call it pick and place. It's wire bonding and is just being performed by JLC
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message-1426219400410955969

2025-10-10T14:46:42.933+00:00 — Andrew Wingate (@anfroholic)

Content

So I have been going around and around about this.

**70pin Mezzanine:** I really think that version would be great, but I am concerned about users being able to get their own components for the mating side. Availability seems very low for this size

**Castellated:** This is another viable option, but this means that users must either supply the COB to a PCBA at the time of assembly, or try to solder this chip on their motherboard themselves. This is doable but ~70 pin castellated solders gets old fast.

**2row 1.27 headers:** This is my latest iteration. This option has all the pins broken out (76) so users can do whatever they like. The picture on the right can probably be wave soldered, reducing the cost as much as possible because things add up fast when there's a lot of pins.

Personally, I would like to see the 50pin mezzanine connector version stay on the smallest footprint version for anyone wanting to use these in application (not sure if there are any) but that option allows a PCBA to assemble an entire board and user does not need to supply anything, then can just plug in themselves easily. This decision is based on price and availability as well.

@asc, I don't know what where you'd land on desires here, but an option as well for you would be the 50pin mezzanine and a bunch of testpad/breakout type areas where you could attach a probe for any pin that is not part of the 50 on the connector.

*We don't know the variability granted by the wirebonders. Ideally the PCB portion could be anything and as long as the pads are all in the same positions, granting @asc and others more pins taken from the power rails needed for @tnt*

Opinions/ suggestions anyone?
@Tim 'mithro' Ansell

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message-1426224298988671170

2025-10-10T15:06:10.845+00:00 — tnt (@246tnt)

Content

I'd definitely avoid 1.27 headers, they're a pain.
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2025-10-10T15:08:39.825+00:00 — tnt (@246tnt)

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I prefer mezzanine, HCTL seems to have quite a few 70~100 pin options if using 2 conectors is not acceptable.
Also instead of castellated, you can do just plain LGA with just 0.5 mm pitch pads on the bottom to be reflowed on a host PCB.

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2025-10-10T15:19:24.555+00:00 — dshadoff

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Thanks. I asked because there was a point in the CrowdSupply talk where Mithro said it might be possible to supply the chips (as wafer slices) as tape spools, which made me wonder about how fragile (or robust) they might be.

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2025-10-10T15:31:57.241+00:00 — Andrew Wingate (@anfroholic)

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Content

Thanks.  While they're *available* from a couple suppliers availability seems low. Wafer.space will be able to purchase whatever because the qty is there given this will be spread across multiple projects, it does not seem places like lcsc stock very many.

Ill try drawing up an lga later tonight hopefully.

There seems fo be a fair amount of pushback on the 2 connectors regarding tolerances. But like I said above,  hopefully the wire bonders will allow different pcbs as long as the pads stay the same, Ill draw you whatever you want if you're willing to risk it!
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2025-10-11T01:10:19.224+00:00 — Andrew Wingate (@anfroholic)

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@tnt, I think we may have a winner here.
Originally, I dismissed LGA as something that's hard to work with, but everything is pretty relative here and this actually seems like a really viable option. Depending on how the sizes of everything work out someone could even put this on  some other daughterboard that does whatever they want.
As shown there's 100 pins (not including the large pads in the middle) I figure sprinkling grounds all over for the analog and differential pins is a huge bonus.
Let me know what you think and I think I can start to harden this design.
@Tim 'mithro' Ansell thoughts?

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2025-10-11T01:11:12.04+00:00 — Andrew Wingate (@anfroholic)

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also of note, the way this is layed out gives an effective pin pitch of 1.13mm so it's not even that super small.
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2025-10-11T01:14:37.63+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Andrew Wingate - I think we probably want these options uploaded and listed somewhere.
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2025-10-11T01:16:40.8+00:00 — Andrew Wingate (@anfroholic)

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Agreed, but nothing is even real at the moment. There isn't even a schematic. I've just been dropping footprints in the editor. The pictures have been the only real thing.

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message-1426379388190195753

2025-10-11T01:22:26.992+00:00 — Tim 'mithro' Ansell (@mithro_)

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Well, I created https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs

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message-1426385417057468659

2025-10-11T01:46:24.386+00:00 — Andrew Wingate (@anfroholic)

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I have uploaded my working files,
But more importantly probably, I have compiled all the different designs and notes here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/scratch

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message-1426385547605315655

2025-10-11T01:46:55.511+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Probably should add a "Work in progress" warning?

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message-1426405068168630443

2025-10-11T03:04:29.576+00:00 — asc (@asc9742)

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@Andrew Wingate thank you for working on this. Just to confirm, with the new 100 pin LGA design, which of the 74 pads would we be able to customize? Is it still the same where we cannot touch the location of the 18 power/ground pads?
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message-1426454915579904040

2025-10-11T06:22:34.125+00:00 — tnt (@246tnt)

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@Andrew Wingate Looks good.  I would definitely do a test solder ( make some empty board  and carrier and actually test reflow ) before making thousands, but it looks nice.
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message-1426455092139393155

2025-10-11T06:23:16.22+00:00 — tnt (@246tnt)

Content

Maybe just notch a corner 🙂
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message-1426544946571247668

2025-10-11T12:20:19.186+00:00 — Andrew Wingate (@anfroholic)

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@asc I would like to defer to @tnt a bit here and ask what/where do you need nets tied in the COB
I am referring to https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?gid=0#gid=0

I would assume that we want `GND IO` to be the ground pour and have these all tied together on the COB.
I am assuming that the rest were tied mostly because you were shooting for a QFN 64 so just tied them all to EPAD. Does this need to remain the case? I am counting 6 wirebonds to `GND IO` can the rest of the pads be on their own nets? @asc this would leave you (74-6) 68 pins to do with as you wish.

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message-1426545793552351273

2025-10-11T12:23:41.122+00:00 — Andrew Wingate (@anfroholic)

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Yeah I was hoping as soon as possible to just get some made and do some testing.
I will see what I can come up with for pin1 marking. I am planning on V-scoring all these and that makes notches more interesting.
maybe a plated through hole with a sizable annular ring? That should stand out.
or now that I'm thinking about it, just a plated shape with no mask over it. It will be a bright gold spot
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message-1426548877590532262

2025-10-11T12:35:56.414+00:00 — Andrew Wingate (@anfroholic)

Content

I kinda like this

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message-1426552541658742896

2025-10-11T12:50:29.996+00:00 — Andrew Wingate (@anfroholic)

Content

I am imagining `GND_IO` to be laid out like this?
Is that too many? Should I try reducing the pitch some?

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message-1426602992399814676

2025-10-11T16:10:58.39+00:00 — asc (@asc9742)

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68 pins would be great.

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message-1426831813682135223

2025-10-12T07:20:13.635+00:00 — tnt (@246tnt)

Content

@Andrew Wingate Anything marked GND should be wired together with as big traces/planes as possible 🙂
The power pins I was originally thinking of wiring them together on the breakout and bypass them there, but in the case of the LGA, if we can put the bottom pads of power close enough to where they get bonded on the top, it's probably fine to not treat them differently.  I maybe  would use 0.8 mm PCB too. Not sure if JLC offers ViP plated over ?
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message-1426833139925385246

2025-10-12T07:25:29.836+00:00 — ewen (@ewenmcneill)

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Looks like JLC can do POFV (Plated Over Filled Via), and on 6+ layer boards it looks like they'll do it at no extra cost since 2024 -- https://jlcpcb.com/blog/Free-Via-in-Pad-on-6-20-Layer-PCBs-with-POFV  (and  https://jlcpcb.com/blog/jlcpcb-free-via-in-pad)

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message-1427003933573775431

2025-10-12T18:44:10.215+00:00 — Andrew Wingate (@anfroholic)

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I've been planning to use .8mm this whole time.
@asc  it looks like 10 pins will be used for GND this will leave (74-10) 64 pins to use as you see fit.
Thank you @tnt , I will try to get something drawn today sometime maybe and hopefully get something off to manufacture in the next few days.
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message-1427011851736191097

2025-10-12T19:15:38.052+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt Does this look ok for a bonding ring layout?
It looks like you wanted to keep the power inputs in the corner pads so I kept that. The power pins will be broken out individualy and you can link/bypass them on the motherboard. I will try to get those pads as close to--if not directly under--the vias for power.
Is there anything else you'd like to see
The pin spacing (21 on each side and 16 on top/bottom) have been preserved
-# the bondwire layout has obviously not been updated

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message-1427012598271967232

2025-10-12T19:18:36.04+00:00 — Andrew Wingate (@anfroholic)

Content

@Tim 'mithro' Ansell would you like to add anything in here.
Previous discussions have revolved around keeping as many pins available for project specific needs over tying some nets together such as VDD.
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message-1427014273716191363

2025-10-12T19:25:15.497+00:00 — tnt (@246tnt)

Content

@Andrew Wingate The pwr aux are actually in the middle of the left/right side, not at the corners.
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message-1427014595112861786

2025-10-12T19:26:32.124+00:00 — Andrew Wingate (@anfroholic)

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Dangit, I had it there for previous revisions.
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message-1427015935230738584

2025-10-12T19:31:51.633+00:00 — Tholin (@tholin)

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I'd check if it was possible to bring the pads in closer without violating the 45 degree limit. I feel like this could be smaller.
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message-1427016668256796803

2025-10-12T19:34:46.4+00:00 — Andrew Wingate (@anfroholic)

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Thanks @Tholin
I thought about that, but decided against hoping I could squeeze half the vias under the bond wires for the inner ring io's

Is there a huge reason to try to shrink it down much further?

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message-1427016756999753739

2025-10-12T19:35:07.558+00:00 — Andrew Wingate (@anfroholic)

Content

*this is still the old padring shown
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message-1427017018103566469

2025-10-12T19:36:09.81+00:00 — Andrew Wingate (@anfroholic)

Content

although I guess it would anyways. Sure, I can shrink it a bit
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message-1427025368543658014

2025-10-12T20:09:20.71+00:00 — tnt (@246tnt)

Content

If the wires are too long they can have too much slack and end up touching.
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message-1427029138576773230

2025-10-12T20:24:19.556+00:00 — Andrew Wingate (@anfroholic)

Content

Alright, I think I got it.
Whatever is going on in that top left corner threw me for a loop every time.
@tnt and @Tholin do you see any problems if I start moving forward with this?

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message-1427029382219956435

2025-10-12T20:25:17.645+00:00 — Tholin (@tholin)

Content

I'd do what I did and check your work by using a comment layer to map out the bond wires.
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message-1427029674692841615

2025-10-12T20:26:27.376+00:00 — Andrew Wingate (@anfroholic)

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Yeah, just wanted to check overall layout before going that far. the two bottom left wires have been placed and are within 45deg
Thank you again
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message-1427029822508634122

2025-10-12T20:27:02.618+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt Is there somewhere I can find the pitch for the bond pads?
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message-1427030660127789168

2025-10-12T20:30:22.322+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) do you have a GDS handy ?
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message-1427030795221991436

2025-10-12T20:30:54.531+00:00 — tnt (@246tnt)

Content

In theory they're equally spaced, so just dividing the die size by number of pins should be close enough.
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message-1427030876604334160

2025-10-12T20:31:13.934+00:00 — tnt (@246tnt)

Content

Note that the 45 deg rule is also not strictly required for the corner ones.

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message-1427031097228792018

2025-10-12T20:32:06.535+00:00 — Andrew Wingate (@anfroholic)

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Ok, I'll go with that.
Afterall, I think this is more of a map for manually placing the bond points.
Thank you
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message-1427043332260888678

2025-10-12T21:20:43.594+00:00 — Andrew Wingate (@anfroholic)

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@tnt @Tholin
Thanks again.
I think this is the final rev

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message-1427043606417375364

2025-10-12T21:21:48.958+00:00 — Tholin (@tholin)

Content

How big is it?
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2025-10-12T21:22:25.829+00:00 — Andrew Wingate (@anfroholic)

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message-1427044286775693434

2025-10-12T21:24:31.168+00:00 — Tholin (@tholin)

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That is pretty small!
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message-1427044394225111171

2025-10-12T21:24:56.786+00:00 — Andrew Wingate (@anfroholic)

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too  small?
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2025-10-12T21:25:01.898+00:00 — Tholin (@tholin)

Content

No

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message-1427044611351773348

2025-10-12T21:25:48.553+00:00 — Andrew Wingate (@anfroholic)

Content

We're well within JLC's capabilities as far as PCBs go
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message-1427045974022295733

2025-10-12T21:31:13.439+00:00 — Andrew Wingate (@anfroholic)

Content

New vs old.
I think this will look really nice

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message-1427046607060209675

2025-10-12T21:33:44.367+00:00 — Tholin (@tholin)

Content

This might fit onto a DIP-40 compatible carrier.

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2025-10-12T21:34:01.24+00:00 — Andrew Wingate (@anfroholic)

Content

not quite. I checked that already...
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message-1427047370746630228

2025-10-12T21:36:46.444+00:00 — Andrew Wingate (@anfroholic)

Content

LGA is 16mm and space in DIP is only 12mm

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message-1427047586220609566

2025-10-12T21:37:37.817+00:00 — Andrew Wingate (@anfroholic)

Content

I don't think trying to squeeze lga by that much is worth it.
Things become very small
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2025-10-12T21:43:47.039+00:00 — Andrew Wingate (@anfroholic)

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oh, you probably thought just the padring.
it might 🙂

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message-1427049749869232168

2025-10-12T21:46:13.671+00:00 — Tholin (@tholin)

Content

Would require some intense routing on a 4-layer PCB, but doable
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message-1427049795368779866

2025-10-12T21:46:24.519+00:00 — Tholin (@tholin)

Content

Assuming supporting components are required
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message-1427049797835165716

2025-10-12T21:46:25.107+00:00 — Andrew Wingate (@anfroholic)

Content

You wouldn't be using all the pins then either, so that would save a bunch of space for traces.
Still not sure how things will land on different formats. Is the pattern more important? or what makes one something *new* that they consider it different
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message-1427050056615465021

2025-10-12T21:47:26.805+00:00 — Andrew Wingate (@anfroholic)

Content

There are 32 pins that go out the top and bottom. That's close to satisfying the 40
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message-1427064534631317614

2025-10-12T22:44:58.633+00:00 — asc (@asc9742)

Content

@Andrew Wingate final is 64 customizable pins and 10 unchanged ground pins? I’m assuming the ground pin locations are identical to the 10 ground pins locations already in the template (from the TT padframe spreadsheet)?
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message-1427064675023061004

2025-10-12T22:45:32.105+00:00 — Andrew Wingate (@anfroholic)

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That is correct.
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2025-10-12T22:45:43.526+00:00 — Andrew Wingate (@anfroholic)

Content

Hope that works for you all
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message-1427064981035290679

2025-10-12T22:46:45.064+00:00 — Andrew Wingate (@anfroholic)

Content

We can get a final sign-off from @Tim 'mithro' Ansell, but I feel pretty confident.
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message-1427067933917581444

2025-10-12T22:58:29.086+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

This is a nice step up from the original Caravel and OpenFrame, which offered 38 (technically 40) and 44 signal pins respectively... so now we'd get at least 54 signal pins, and each of them as customisable pads.
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message-1427067970936508467

2025-10-12T22:58:37.912+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Great work @Andrew Wingate and team 🙂

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message-1427069922365669438

2025-10-12T23:06:23.169+00:00 — peterkinget

Content

Great work.

I would still like to suggest to have more signal pins. I am not sure why you are using so many VSS pins. Now I might be missing something in terms of the limitations w.r.t. COB bonding, but 10 GNDs out of 74 is a lot, in particular for those of us who are not going after high speed or RF designs (which are going to be challenging in GF180MCU anyway).

We need 68 pins (and preferrably more) for MOSbius. But I do not think we are unique in the "need for pins". I did a quick area estimate planning exercise yesterday -- see below -- and we have tons and tons of spare area and could put in a lot of functions, but just need more pins ... That is in part due the nature of our MOSbius design, but is true for many designs by starting designers where you want a good number of pins for debug. We saw the same in the chipathon.

Can we set up a zoom call to discuss. I am on pacific time but can accommodate times the work for US or EU.

Many thanks.

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message-1427070556641038421

2025-10-12T23:08:54.392+00:00 — peterkinget

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Have you considered putting the chip footprint on the PCB under a 45 deg angle (see e.g. the arduino nano board), that often simplifies the routing. If it is allowed by the COB packaging process.
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message-1427071448534483026

2025-10-12T23:12:27.036+00:00 — Andrew Wingate (@anfroholic)

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I thought about that as well. The main argument that came to mind was what the wirebonders would think of it.
I think there are still a lot of negotiations happening, so I'm not sure what they feel a *new design* would consist of, whether it be changing orientation, number of pins while still sharing locations from default, different spacing on a panelized PCB.
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message-1427071889938841601

2025-10-12T23:14:12.275+00:00 — Andrew Wingate (@anfroholic)

Content

Another option for those like @Tholin would be to create a board that can just accept the LGA and do whatever you like there.
This particular design kinda makes me feel yucky, but not entirely sure why, but figured I'd share

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message-1427075177635643444

2025-10-12T23:27:16.123+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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> Can we set up a zoom call to discuss. I am on pacific time but can accommodate times the work for US or EU.
I'm not sure who outside @tnt wants to speak for the default padframe.
I personally don't have any opinions but would offer to be present if you all think I would add anything.
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message-1427082663134761141

2025-10-12T23:57:00.805+00:00 — Andrew Wingate (@anfroholic)

Content

Also I've been following the recommendations laid out by STMicro on LGA patterns and am opting for non solder mask defined (NSMD) pads for reliability and feel there shouldn't be a lot of rework done on these chips (you're getting 1000 anyways)
https://www.st.com/resource/en/application_note/an5886-guidelines-for-design-and-board-assembly-of-land-grid-array-packages-stmicroelectronics.pdf
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message-1427084527154626641

2025-10-13T00:04:25.222+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate / @peterkinget / @tnt / @asc / @Tholin

I have a couple of random thoughts (not in any particular order):
 * *Ultimately* my thoughts don't really matter, the only ones who really do are the PCBA house & the customers. If the result is under budget, actually can be manufactured and makes people happy then it is perfectly fine by me.
 * In terms of PCBA negotiation, PCB Way is the furthest along, then Seeed and JLCPCB the furthest behind. We should make sure the PCBs are manufacturable at PCB Way as P0.
 * I'm happy to have multiple PCBs and pad frame designs -- 4-6 is fine, >10 is probably too many.
 * I really want to have at least one option which is DIP for breadboard compatible usage.
 * I have square & symmetrical designs, just gives one another way to screw things up.
 * The **only** silicon we have today uses either Mehdi/OpenFASoC or the caravel padframe. Hence to test the cob wire bonding before we get back Run 1 silicon we need some designs which are compatible with that. I think we **do** really need to test this whole process before Run 1 gets back.
 * I believe @stuart is the only person who has actually done cob wire bonding before (as part of the Tiny Tapeout test) we should ask him for advice and thoughts.
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message-1427084764086669445

2025-10-13T00:05:21.711+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

There are also design rules from one house found @ https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view?usp=sharing
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message-1427088280721162253

2025-10-13T00:19:20.142+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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> design rules from one house found
Awesome, thanks. Giving that a read. Seems I'm out of spec in a couple areas

> I'm happy to have multiple PCBs and pad frame designs -- 4-6 is fine, >10 is probably too many.
- @peterkinget  Personally I would like to keep my just one LGA pattern but would be happy to create a bond pad version for you all. Let me know what you have in mind and I can try.
- In this case I can connect some nets back up if you'd like @tnt?

> [...] We should make sure the PCBs are manufacturable at PCB Way as P0.
I just glossed over capabilities. I tried to keep everything very loose. Seems we're still on point

> The only silicon we have today uses either Mehdi/OpenFASoC or the caravel padframe [...] we need some designs which are compatible with that.
Is the TT frame compatible?
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message-1427089757384478781

2025-10-13T00:25:12.206+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate - Afraid I have no idea, would have to ask @tnt on the frame compatibility.

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message-1427103003470598255

2025-10-13T01:17:50.319+00:00 — Andrew Wingate (@anfroholic)

Content

Fiducials added and ground landings moved to adhere to design constraints
edit: I also changed pin #s to harmonize with TT pin #s

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message-1427159166308454440

2025-10-13T05:01:00.583+00:00 — peterkinget

Reply/reference

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Thanks, @Andrew Wingate, what timezone are you in? It would be great to connect in a webmeeting.

Your design looks nice. Where do you think you are out of spec?

How big are your bondpads on the chip? They seem bigger than my 100um pads at a 200um pitch. I left a 1.5mm spacing around the die to statisfy the 1.5 x die thickness clearance (die are typically way thinner than 1 mm, don't know if the dies are backlapped in GF180); then I placed a row of 200x100 bondfingers (PCB side) at a 200um pitch on top. Not sure if the PCB house can support that, but it seemed to satisfy the requirements in the doc that @Tim 'mithro' Ansell shared above. If the PCB can support, then we can have straight wires, or am I missing something?

Why are some of your bondfingers bigger?

What CAD are you using for the PCB design? I attach a PDF export of an Altium webpage https://resources.altium.com/p/pcb-design-rules-chip-board-layout?utm_source=chatgpt.com. That tool seems to have a nice COB built in tool. In any case, notice how they rotate the pads to be aligned with the bondwire. This is also clearly visible on the picture that is on the wafer.space front page. Have you considered doing that or are there reasons why you can not?

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message-1427163329717080135

2025-10-13T05:17:33.217+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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>  what timezone are you in?
I'm in Chicago - UTC-6. And you?

> Your design looks nice. Where do you think you are out of spec?
The minimum distance to a pad based on the height of the die. (just a couple of the ground wires.)

> How big are your bondpads on the chip? They seem bigger than my 100um pads at a 200um pitch.
If you're talking about what you see above, those are **not** the real pad sizes. they're just drawings for reference.
I also am not well versed enough to answer some of the other questions, you'll have to ask someone else.

> Why are some of your bondfingers bigger?
In an effort to get some more pads broken out for you all, I talked to tnt about breaking some nets up so you could use them for your purposes. In that we wanted to keep the traces as short as possible so there is a via directly in those.
I feel I will be going back and changing that portion as it's less necessary now. We'll see. Long story short is they don't have to be.

> What CAD are you using for the PCB design?
I'm using KiCad

> Altium webpage [...] seems to have a nice COB built in tool. In any case, notice how they rotate the pads to be aligned with the bondwire. Have you considered doing that or are there reasons why you can not?
This would be kindof a pain in Kicad and I don't think this is necessary. You're welcome to design your own.

It seems like you have the same layout as the TT layout with 74 bonds.
https://docs.google.com/spreadsheets/d/1sZCpz6yy-bHGaV2BVG4IZOLBWn--WIddM9pkCQm_Vyc/edit?gid=0#gid=0

If you want to make your own pin map, I will make a version for you.
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message-1427189768911065138

2025-10-13T07:02:36.812+00:00 — Leo Moser (mole99) (@mole99)

Content

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2025-10-13T07:02:58.536+00:00 — Leo Moser (mole99) (@mole99)

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This is generated using the project template. The pad positions are fixed, the signal pad types can be changed.
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message-1427363471191838871

2025-10-13T18:32:50.663+00:00 — stuart (@saladchap)

Content

Not sure how realistic this timing is but I'm going to be in Shenzhen next month (7-20th) and will be visiting my friend's cob factory for some TT projects and tests, would be happy to take other boards and dies too.

They only do aluminium bonding, not gold wires - and can do either black or colourless transparent glob top
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message-1427363678985912341

2025-10-13T18:33:40.205+00:00 — stuart (@saladchap)

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https://youtu.be/XJmWoBJjvlI?si=Bj2e63CKN8ztEQ2d

Here's a video with more about what we did last year

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2025-10-13T18:35:58.824+00:00 — stuart (@saladchap)

Content

One thing to consider is making sure there's nothing too big / tall near the bonding area so the machine head has enough clearance. The cob process has to be done after smta afaik as the bonds wouldn't survive the reflow oven temps - they had to do some creative programming to get around the headers on the boards we took last time
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message-1427365034333569196

2025-10-13T18:39:03.345+00:00 — tnt (@246tnt)

Content

"The cob process has to be done after smta afaik as the bonds wouldn't survive the reflow oven temps"
Oh well that would kind of kill the LGA or castellated pad idea and only leave mezzanine connects as the only option if you can't reflow after wire bonding ....
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2025-10-13T19:17:32.019+00:00 — Andrew Wingate (@anfroholic)

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Yeah, that would really be a problem lol.
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2025-10-14T00:45:58.849+00:00 — Tim 'mithro' Ansell (@mithro_)

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I thought that the wire bonds were pretty protected after the covering blob was done?
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message-1427457590413234289

2025-10-14T00:46:50.434+00:00 — Andrew Wingate (@anfroholic)

Content

I've been trying to track that down as well. My google-foo has been poor.
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2025-10-14T00:47:16.972+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

This is also why I think we need to try and do some experiments / runs ASAP.
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message-1427457712886906921

2025-10-14T00:47:19.634+00:00 — Andrew Wingate (@anfroholic)

Content

It's covered in epoxy which should hold up to the heat just fine
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2025-10-14T02:55:56.311+00:00 — peterkinget

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I am on Pacific time, feel free to suggest some times and I will try to accommodate.
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2025-10-14T03:02:15.054+00:00 — Andrew Wingate (@anfroholic)

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Typically later in my evenings work the best. Some time around now some other day would be fine.
If you're up for it, I would like to leave this semi-public and let others here join in if they'd like to join in.
Tonight does not work for me. Tomorrow I will be out of town. I think I'm pretty free for the rest of the week, so let me know what works for you with that.
Others please let us know if these times work for you.
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2025-10-14T03:02:52.112+00:00 — peterkinget

Content

Rest of week should work for me; wednesday best.
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message-1427491969659043861

2025-10-14T03:03:27.085+00:00 — Andrew Wingate (@anfroholic)

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Ok, let's tentatively shoot for Wed evening!
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message-1427493145062408272

2025-10-14T03:08:07.323+00:00 — peterkinget

Content

How about 8:15pm Pacific 10/15 -- here is a meeting room: https://columbiauniversity.zoom.us/j/98265793354?pwd=sXsJvzRF9rmJt1YTb6MCpkd0PXew7E.1

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message-1427514323407994951

2025-10-14T04:32:16.634+00:00 — Andrew Wingate (@anfroholic)

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I asked the reddit and got a response that you could reflow. There are wire bonds in many (most) regular packages.

Their response in the post https://www.reddit.com/r/AskElectronics/comments/1o61zzx/boards_with_wire_bonded_die_and_epoxy_coating_can/
> es, it can. This is a pretty common setup for cheap products where all the high integration stuff is located on a module. A lot of the handheld NES games do that.
>
> This is also not that different from the ICs. It is also epoxy coated wire bonded die.

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message-1427521658599772184

2025-10-14T05:01:25.48+00:00 — Andrew Wingate (@anfroholic)

Content

Looked into it a bit. Found this, but doesn't seem like it's reflowed after..

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message-1427527559729516544

2025-10-14T05:24:52.419+00:00 — Andrew Wingate (@anfroholic)

Content

While I have not been able to find anything specifically, There are a ton of BGA that seem to follow the pattern we're looking for.

Found these people and if somewhere did have something suitable, these guys would probably know
https://dm.henkel-dam.com/is/content/henkel/COST_EFFECTIVE_AND_RELIABLE_MATERIALS_FOR_WIREBOND_PACKAGING

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message-1427527603006341161

2025-10-14T05:25:02.737+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Also, are all epoxies equal? For example, does the clear epoxy have the same qualities as the “usual” black COB epoxy?
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message-1427528227160719452

2025-10-14T05:27:31.547+00:00 — Andrew Wingate (@anfroholic)

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There are a ton of varieties in the pdf I just posted.
Page 22 has a bunch of COB style encapsulants. BGA is also listed so I would assume it's suitable for LGA as well

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message-1427563642777243730

2025-10-14T07:48:15.288+00:00 — stuart (@saladchap)

Content

I did a bit more looking and seems like gold wire bonds may be more resilient than aluminium - I don't have experience with gold wire bonds but have seen alu bonds fail after glob top then going through the reflow oven
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2025-10-14T08:05:50.181+00:00 — tnt (@246tnt)

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The plastic encapsulation of "normal" packages ( like QFN and such ) might also provide a lot more protection than whatever the COB process uses, so that could be a difference too
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2025-10-14T08:07:22.633+00:00 — urish

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Shall we try to find some packaging expert to consult?
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2025-10-14T08:08:06.465+00:00 — Andrew Wingate (@anfroholic)

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If you know someone, I'm sure we'd love to hear what they have to say
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message-1427568819131383860

2025-10-14T08:08:49.427+00:00 — urish

Content

I don't know, but we can try to find (LinkedIn is a good starting point)

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message-1427570591245930590

2025-10-14T08:15:51.932+00:00 — Andrew Wingate (@anfroholic)

Content

I want to say that we'll be fine here
And the reason this is not seen much in industry has more to do with the fact that low pressure molding has an extremely lower cycle time that is more in line with what packagers are used to and are willing to put up with. They also don't need additional processes like baking or UV treating.
Like, if we weren't in the situation we're in and the packagers were willing to work with our quantities we would have a QFN or similar package.
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message-1427573827134820423

2025-10-14T08:28:43.428+00:00 — Andrew Wingate (@anfroholic)

Content

another example
https://www.qptechnologies.com/services/ic-assembly/encapsulation-options/

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message-1427573947226128516

2025-10-14T08:29:12.06+00:00 — tnt (@246tnt)

Content

Semi-related is I wonder how pick and place machine deal with glob top parts ... like would those LGA module work fine or would the top not be flat enough for vacuum pickup and proper placement ...
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message-1427575721370325046

2025-10-14T08:36:15.049+00:00 — Andrew Wingate (@anfroholic)

Content

The biggest tip i have i think would be alright

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message-1427577343123259473

2025-10-14T08:42:41.705+00:00 — tnt (@246tnt)

Content

It also needs to sit flatish in it or it would screw up when it places it I think.
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message-1427578682708594750

2025-10-14T08:48:01.087+00:00 — Andrew Wingate (@anfroholic)

Content

All the encapsulations I've come across seem to self level pretty well.
I think it should be alright
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message-1427673626034962432

2025-10-14T15:05:17.34+00:00 — db (@ddddbbbb)

Content

Hi all, here's a few pieces of information on COB mfg in case it's useful to the recent discussions going on. It took us over a year to establish a flow that didn't break most of our assemblies :( This was a combination of company negotiation time and lots of surprise temperature incompatibilities.
* You will likely find wirebond/COB houses and SMT assembly houses who will each want to do their process first on a bare PCB. I have set up prototyping runs in both situations, and only once found a company that could do both (at higher cost than the two phases individually, unfortunately). I have not gone back to that company because initial project setup took months and over 150 emails. Then that sales engineer retired and I loathed the idea of explaining our assembly to another person. I think they contracted out the COB portion but at least they were responsible for ensuring order of operations.
* Advantages to SMT going first: get the high temperature steps out of the way. We were using transparent epoxy that swelled in high temperature, ripping off bondwires. As others have already mentioned, opaque epoxies can generally withstand high solder temperatures.
* Advantages to COB going first: wirebond heads work easiest when the bonding surface is flat and there's nothing for the bond head to crash in to. Also they are often attached via vacuum chuck which cannot seal if there are parts on the backside of the board. Custom chucks can be fabricated to enable vacuum seal, at increased NRE cost.
* We had some designs packaged QFN but the hassle and cost wasn't ultimately worth it. Packages were not bonded correctly in some cases, with no way to inspect the bonds' correctness via microscope.
* COB houses will often require PCBs with ENEPIG or soft bondable gold surface finishes which increase PCB cost and mfg time significantly. Some COB houses are fine with more widely available ENIG but with more risk to yield.

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message-1427825041835561013

2025-10-15T01:06:57.68+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

The current plan is that the PCBA house is also doing the wire bonding.

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message-1427825466156257410

2025-10-15T01:08:38.846+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

That would likely solve the availability problems if we end up going with some kind of connector. They would likely offer to stock them hopefully.
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message-1427870869497053195

2025-10-15T04:09:03.846+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But the 150 email nightmare problem is what I'm hoping we can solve
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message-1427871115312889976

2025-10-15T04:10:02.453+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But also why I want to get something actually bonded and such
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message-1427871609854627911

2025-10-15T04:12:00.361+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But I would also guess we are okay with a higher failure rate than industry as well
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message-1428031266883633203

2025-10-15T14:46:25.563+00:00 — dshadoff

Content

Probably good to set a numerical target on that
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message-1428050410299461824

2025-10-15T16:02:29.709+00:00 — db (@ddddbbbb)

Content

To clarify, the yield risk of ENIG is number of parts successfully assembled --in contrast to flip chip bumps, it's pretty obvious under a microscope if a wirebond doesn't want to stick to its pad. As long as the assembly house notices the failed bond before covering it in epoxy, "low yield" should mean some wasted dice and otherwise a very high percentage of functional assemblies that are shipped back (assuming anything else on the board is assembled perfectly).
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message-1428142143649742898

2025-10-15T22:07:00.644+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@dshadoff - I would say somewhere between 1% and 10% of whole parts.
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message-1428142769729179728

2025-10-15T22:09:29.913+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@dshadoff - Like you if you want 1,000 pieces and I send the board house 1,100 and then you get 100 failures, that seems fine to me.

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message-1428152978832888071

2025-10-15T22:50:03.953+00:00 — dshadoff

Content

fair enough.  Just wanted people thinking about the number.
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message-1428244011508039801

2025-10-16T04:51:47.834+00:00 — Andrew Wingate (@anfroholic)

Content

Hey @tnt
I just had a meeting with @peterkinget and @asc and they were telling me about their needs.
I have changed the padframe layout a bit and wanted to run it past you.
The intent here is for anyone using the 74 pad layout can customize it to their needs, but the actual wirebond layout will remain unchanged between versions.
The example here I have your GND pins all tied together and we can also tie together VDD and other nets too if you'd like.

@peterkinget I have uploaded the latest versions. The newest padframe footprint is also here.
https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs
https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/scratch/footprints

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message-1428244390115152036

2025-10-16T04:53:18.101+00:00 — peterkinget

Content

Thanks! We make a pcb rough design and share in the coming days.

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message-1428249015337881650

2025-10-16T05:11:40.84+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

This is nice @Andrew Wingate 🙂

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message-1428253368190767155

2025-10-16T05:28:58.641+00:00 — tnt (@246tnt)

Content

@Andrew Wingate Sure looks fine.  It's a bit confusing to have the waferspace logo not in the pad 1 corner  though no ?
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message-1428254646908223508

2025-10-16T05:34:03.511+00:00 — Andrew Wingate (@anfroholic)

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You are correct. It's an artifact from before I was following your pinout.
I had never made a design that didn't have pin 1 at the top before.
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message-1428254950257066014

2025-10-16T05:35:15.835+00:00 — tnt (@246tnt)

Content

Fee free to rotate the die footprint if you want the pin 1 on the top 😁
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message-1428255062731395133

2025-10-16T05:35:42.651+00:00 — Andrew Wingate (@anfroholic)

Content

Haha, sounds good thanks
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message-1428255125025193984

2025-10-16T05:35:57.503+00:00 — tnt (@246tnt)

Content

I think we just used that pin numbering / orientation because the original IHP script in ORFS was using it and so this is what we ended up with.
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message-1428255180658442302

2025-10-16T05:36:10.767+00:00 — Andrew Wingate (@anfroholic)

Content

I understand
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message-1428913611149148191

2025-10-18T01:12:32.829+00:00 — Andrew Wingate (@anfroholic)

Content

@Tim 'mithro' Ansell I figured CS was about to be bugging you for an update so I made this.
Then I checked my email. Let me know if there's some other kind of content I can drum up.
-# this is meant to look pretty and is not real, but is very close to what the real one could look like.

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message-1428958265836048424

2025-10-18T04:09:59.336+00:00 — peterkinget

Content

Hi @Andrew Wingate, @Tim 'mithro' Ansell , we made a quick design of the DIL version. (Thanks to @asc and Xianglin Pun)

Not routed but we wanted to figure out the size. There are 37 pins across now, but we will likely reduce to 34. The vertical dimension might grow a bit in steps of 100mil  if we face routing contention at the bottom and top.

Let us know what you think. This would be great for our purpose since we can plug it right in the breadboard or custom PCB with headers without needing a motherboard and reflow solder oven.

We are happy to share the design once it is done.

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message-1428959062888022107

2025-10-18T04:13:09.368+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Thanks! I know that Tim is wanting a breadboard version so it's good to see one mocked up!
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message-1429068742108909638

2025-10-18T11:28:58.932+00:00 — Andrew Wingate (@anfroholic)

Content

70 pin Mezzanine COB
I have a pretty strong feeling this will be one that makes it to the end.
If you want a motherboard *stick it on there*
If you want a DIP package *stick it on there*
If you want a breadboardable *stick it on there*
If you want a test board *stick it on there*
If you need revisions *stick it on there*, revise, then *stick it on there*
If you want other people to design motherboards for you, send them one so they can *stick it on there*
If you're worried about wirebond failures *stick it on there* and test without worries

Side benefits, PCBA house does not need to stock these for you and/or you do not need to ship them to them when you need more motherboards

The extra cost will probably be < $0.30 but may be washed out if the wirebond house only has to deal with a single format.
If half a run wants COB that's 20k. Setup costs trend towards zero, and 1k chips almost perfectly fit on a 7" reel making a PCB changeout also low/no cost.
@db mentioned above that some of the wirebonders use a vacuum chuck to hold the parts. If we think we want to move the bottom traces into an inner layer and accommodate some decoupling we may want to consider that now before tooling is made (even if we never do)

Is there anything I missed?
@tnt @Tim 'mithro' Ansell @peterkinget @Tholin @asc

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message-1429088512086638623

2025-10-18T12:47:32.462+00:00 — Jianxun Zhu (@jianxunzhu_54325)

Reply/reference

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Nice, is the mezzanine connector polarized? It appears symmetric and could be connected both ways?
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message-1429089146256887879

2025-10-18T12:50:03.66+00:00 — Jianxun Zhu (@jianxunzhu_54325)

Content

If there are retention strength concerns maybe we can design a 3D printed bracket for it.
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message-1429089616710864957

2025-10-18T12:51:55.825+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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It is symmetric, but there are multiple pin 1 markers.
These connectors are quite strong it's the same ones that hold on the Raspberry Pi compute modules. Also these COB are fairly small. I don't think I would worry.
But thank you for your input, I plan to create some tests to be sure.
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message-1429090228068679852

2025-10-18T12:54:21.584+00:00 — tnt (@246tnt)

Content

@Andrew Wingate Looks good.  One comment (both for LGA and mezzanine), the tracks could probably be thicker for the power pins, there does looks like there is space.   I think there should also be space for decoupling in the corners on the top to put a few 1u 0201 there.
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message-1429090786934394931

2025-10-18T12:56:34.828+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Ah, I hadn't considered putting them further out. That could work.
Also yes, power pins could be widened.
Thank you
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message-1429091604450246827

2025-10-18T12:59:49.739+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt  Do you have an idea on how many? I see 8 pins that have power
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message-1429092693925171252

2025-10-18T13:04:09.49+00:00 — Jianxun Zhu (@jianxunzhu_54325)

Reply/reference

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Could you share the part number of the connector? Thanks
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message-1429092809193033801

2025-10-18T13:04:36.972+00:00 — Andrew Wingate (@anfroholic)

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https://www.lcsc.com/product-detail/C19089236.html

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message-1429108195506257983

2025-10-18T14:05:45.355+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt power traces thickened and 8 decaps added.
I also wrote some notes for others if they want to add some kind of components. If bonders want some kind of vacuum chuck, they can provision for components to sit here.

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message-1429108783384367146

2025-10-18T14:08:05.516+00:00 — urish

Content

No notch?
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message-1429109080907317258

2025-10-18T14:09:16.451+00:00 — Andrew Wingate (@anfroholic)

Content

The plan is to have these all v-cut.  That makes notches a little more tricky.
There are qty(2) pin 1 markers

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message-1429109137857450038

2025-10-18T14:09:30.029+00:00 — urish

Reply/reference

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Started a thread.
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message-1429109314861273098

2025-10-18T14:10:12.23+00:00 — urish

Content

What if you just drill at the edge?
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message-1429109369366384892

2025-10-18T14:10:25.225+00:00 — urish

Content

As in adding a large via
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message-1429109533468397761

2025-10-18T14:11:04.35+00:00 — Andrew Wingate (@anfroholic)

Content

We could... I kinda like the golden rocket
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message-1429109636463726775

2025-10-18T14:11:28.906+00:00 — urish

Content

You can have both
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2025-10-18T14:12:31.099+00:00 — urish

Content

I was thinking about drilling out just the part that doesn't have the solder mask
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message-1429110091356835911

2025-10-18T14:13:17.361+00:00 — Andrew Wingate (@anfroholic)

Content

The window in the rocket?
It's too small.
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message-1429110208545689753

2025-10-18T14:13:45.301+00:00 — Andrew Wingate (@anfroholic)

Content

This entire thing is itty bitty
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message-1429110504290259025

2025-10-18T14:14:55.812+00:00 — Andrew Wingate (@anfroholic)

Content

The vias are the smallest drill without being charged more
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message-1429265501145534516

2025-10-19T00:30:49.942+00:00 — Andrew Wingate (@anfroholic)

Content

*The following is my opinion alone*

Based on notes like above about 150 emails between @db and their wirebonder, this is something we want to avoid. And given the most I’ve seen for passing bond layouts has been glorified napkin sketches. We don’t want to be doing this all the time.
The overall layout here has 74 bondpads and 70 pins that can be brought through the mezzanine connector.
Again, it’s my suspicion, but keeping things the same will pay in dividends.
I think the process looks something like this.

### COB PCB
PCB houses already deal with variety, I don’t see why this would be different. The current layout is a 7x6 grid (42) dies per panel. 25 panels is 1050 COB. We will likely share a few basic designs and all most would do is change the silkscreen to their liking.
From @Tim 'mithro' Ansell side, he is looking at purchasing 10s of thousands of these connectors making for happy conversations with suppliers. With Crowd Supply’s connections with Mouser, there may be a way to get them to stock the mating components.

### Glue and Die Placement
All the die are the same size. If there is a mechanical solution for adding the glue (I believe there is) having the same layout for everything will make them very happy. Cost is inversely proportional to happy. Furthermore, from my estimation, roughly 1k die fit on a 7” reel and the die can likely be placed by standard pick and place machinery, further increasing happiness.
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message-1429265514567438376

2025-10-19T00:30:53.142+00:00 — Andrew Wingate (@anfroholic)

Content

### Wirebonding itself
**Wirebonding:** Like I said above, it seems like wirebonds are identified by napkin sketches. Even moving 1 pad creates 74 unhappys. I am going to go out and and say that in the beginning at least it’s going to be cheaper for someone who only wants 50pins and a 50pin mezzanine ($0.20 cheaper per connector) to actually get all 74 wirebonds even if they remain unused.
**Vacuum Chuck** @db  had mentioned above they may—likely—use a vacuum chuck. For our needs they will likely need to create a custom harness, decreasing hundreds of happy every time there is something new. In the design I have allocated a space we can keep clear for any number of components that can fit that area. *Stack height can  be changed on motherboard side if needed*

### Goober
Once the wirebonding is completed, the dies need to be protected. There are machines that can place the epoxy. Again, if all the panels are the same, there is no setup cost, increasing happiness.
@Matt Venn shared a table in one of his recent videos about where all the cost is compared across different quantities. If there is an LGA version, I suggest it *still* use the same layout. If @Tim 'mithro' Ansell  can get the throughput enough that he’s making runs every week—which would be super cool!!—I bet the cost for this would drop below $0.50 or even less for some variations.
Enough happiness to go around.
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message-1429676570972393594

2025-10-20T03:44:16.626+00:00 — Andrew Wingate (@anfroholic)

Content

Just to keep the creative juices flowing, I made a couple examples of motherboards. While I think it would be a squeeze to fit this on a dip with all the pins, if there were less I see no problem working with the .3" space.  70pin DIP does not seem like anything anyone would want anyways.

Both have 35 pins on each side. Since we cannot know what the pinout will be from the die, we can't really pour grounds, but would be simple enough for someone to change if they did want it. (I also feel like someone would want to label pins as well?)

One is castellated, one is meant to plug into a breadboard and has .5" spacing between .1" headers

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message-1429721987726704761

2025-10-20T06:44:44.824+00:00 — Leo Moser (mole99) (@mole99)

Content

@Andrew Wingate looks great!

"Since we cannot know what the pinout will be from the die, we can't really pour grounds"

Does that mean the current plan is to give each pad a separate pin?
I thought, the ring in the image above was a ground ring?
Sorry if this has already been answered :)

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message-1429723841252556830

2025-10-20T06:52:06.739+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

No worries.
Judging only from the TT layout and the MOSbius layouts they're both using the *standard* 74 pads on the die.
MOSbius wants access to as many pins as possible, while TT wants many more ground pads--and some decoupling.
Correct me if I'm wrong, but users can choose to use any pad in any way they wish on the die?
Finally, *personally.* I think that using a mezzanine connector will be a good choice for us all going forward. That leaves 70pins that can make it down to a motherboard. The two projects I've listed here are incompatible and don't necessarily even share the same GND pins on the die let alone what makes it down to the motherboard.
I imagine, eventually there will be some conventions which will allow for some standards, but does not seem that we're there
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message-1429724636253257738

2025-10-20T06:55:16.282+00:00 — Andrew Wingate (@anfroholic)

Content

> Does that mean the current plan is to give each pad a separate pin?
I think the disconnect may be:
Yes, there are 74pads on the COB. But some COB will be unique--but hopefully only on pin/pad signal and routing
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message-1429725019789066260

2025-10-20T06:56:47.724+00:00 — tnt (@246tnt)

Content

ATM the only way to accomodate both is to have different "breakout" ( bonding -> connector ) PCBs.  The dimensions of the PCB, connector position and wirebonding plan will be the same but actual traces on the PCB will be different.

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message-1429726493545726023

2025-10-20T07:02:39.095+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks for the explanation. So I understand that MOSbius will use a separate "breakout" PCB compared to the default one (TT).
This means that they will have to modify any of the motherboards they want to use anyway, in order to pour grounds.
But then, why don't develop the motherboards for the default "breakout" PCB in mind?
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message-1429726963517620275

2025-10-20T07:04:31.145+00:00 — Andrew Wingate (@anfroholic)

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Correct. I posted the current TT version here https://discord.com/channels/1361349522684510449/1408134567491145728/1429108195506257983
And @xianglin_pu created a derivative version here https://discord.com/channels/1361349522684510449/1429068742108909638/1429520076536811622

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message-1429727153532178473

2025-10-20T07:05:16.448+00:00 — Andrew Wingate (@anfroholic)

Content

Also the TT version has 8 1uF decoupling caps
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message-1429727392414302302

2025-10-20T07:06:13.402+00:00 — Andrew Wingate (@anfroholic)

Content

With the intent to future-proof I have outlined an area people can put components and *hopefully* not interfere with the wirebonders.
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message-1429728916070989835

2025-10-20T07:12:16.67+00:00 — Leo Moser (mole99) (@mole99)

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Right! But what I meant, in the example motherboards you posted above, why don't you just pour the grounds for the default breakout PCB? For any non-default breakout PCBs, the ground pours will have to be modified anyways?
This way it would be just a bit easier to go the default route, but it shouldn't make any difference for any non-default projects.
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message-1429730381845889084

2025-10-20T07:18:06.138+00:00 — Andrew Wingate (@anfroholic)

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I guess, there just is no default breakout yet. I may be naive, but I don't think that either are exactly generic.

MOSbius is probably closer, choosing to break out more pins instead of ground, but this isn't necessarily true for someone wanting super highspeed differential signals?
So I just don't know, and in my not knowing I decided not to make a choice 😉

If anyone wants to suggest a default, I am more than willing to listen. Even if it's allocating certain specific pins to GND?
These questions are also why I've been rapid firing different examples and configurations.
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message-1429730769366155315

2025-10-20T07:19:38.53+00:00 — Andrew Wingate (@anfroholic)

Content

In the end, these are pretty generic, and I see people wanting to customize them at least a little bit anyways. Even if it's just to put the project name and version on it.
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message-1429731131212693564

2025-10-20T07:21:04.801+00:00 — tnt (@246tnt)

Content

MOSBius doesn't care about separating IO GND and Core GND because they use neither ... all their pins are analog logic so there is no IO current, they use none of the digital pad at all afaiu.

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message-1429731692373086268

2025-10-20T07:23:18.592+00:00 — Leo Moser (mole99) (@mole99)

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Well, the choice we had made was the TT padring, since TT has to be fabricated anyway and is reasonably generic as a default padring.
It will not be possible to find a pinout that matches every application.
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message-1429731708579745825

2025-10-20T07:23:22.456+00:00 — tnt (@246tnt)

Content

It's true that TT has probably more than strictly necessary, but I'd rather err on the side of caution. It's also because of the way TT work, our "in-chip" PDN has more resistance than a "normal" chip would have, so one way of compensating for that is to feed it externally at more points.
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message-1429732057986236557

2025-10-20T07:24:45.761+00:00 — Leo Moser (mole99) (@mole99)

Content

So when it comes to digital designs, the TT padring is a good default.
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message-1429732569913491527

2025-10-20T07:26:47.814+00:00 — Andrew Wingate (@anfroholic)

Content

I am probably getting a little lost with language.
When you say "padring" you're only referring to the pads on the die itself?
Or how/where/what signal/power goes to each pad?
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message-1429732777909288991

2025-10-20T07:27:37.404+00:00 — Andrew Wingate (@anfroholic)

Content

-# forgive my ignorance
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message-1429733118390046750

2025-10-20T07:28:58.581+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1429733199273001023

2025-10-20T07:29:17.865+00:00 — Leo Moser (mole99) (@mole99)

Content

The padring is really the ring around your design, which defines the type and placement of the pads.
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message-1429733295180218501

2025-10-20T07:29:40.731+00:00 — Leo Moser (mole99) (@mole99)

Content

We've chosen the TT padring as a reasonable default padring.
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message-1429733406165696614

2025-10-20T07:30:07.192+00:00 — Andrew Wingate (@anfroholic)

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Ok, yes. I am also suggesting that *all* projects use this padring as default. Anything not this is not default
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message-1429733497941262367

2025-10-20T07:30:29.073+00:00 — Leo Moser (mole99) (@mole99)

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Therefore, it would be great if the default "breakout" PCB and motherboards could be optimized for that.
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message-1429733807224782910

2025-10-20T07:31:42.812+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I'm all for that too, but am not skilled enough to understand these choices fully
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message-1429733957544448080

2025-10-20T07:32:18.651+00:00 — tnt (@246tnt)

Content

Some numbers I got was 500 mA per bond wire ( for 25u Al wedge bonded) _fusing_ current, so you'd want to stay way away from that, say half.   I don't know the short circuit current of the IO but on IHP for instance it's 32 mA, so you'd want like 1 power wire for like ... 8 IOs or so to survive the user shorting all. So for the default frame that has 54 user IO, you'd want at least 6 GND IOs.

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message-1429734068446167041

2025-10-20T07:32:45.092+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Well, yes, they should use the same pad positions and power/ground pads if they want to use the default bonding setup :)
The signal pad types can actually be changed and it is still compatible.

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message-1429734420662845473

2025-10-20T07:34:09.067+00:00 — Leo Moser (mole99) (@mole99)

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Content

That's why I suggested to pour the ground planes for the default "breakout" board, as this is what most people will be using.
If you use a non-default "breakout" board, you need to change the ground pours anyway.

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message-1429734884338958416

2025-10-20T07:35:59.616+00:00 — Leo Moser (mole99) (@mole99)

Content

Great work on the PCBs by the way. I'm really looking forward to seeing all of this coming together!

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2025-10-20T07:36:37.099+00:00 — Andrew Wingate (@anfroholic)

Content

Thanks, please don't hesitate to make suggestions. I often share things before they're pretty to get feedback

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message-1429736600123736114

2025-10-20T07:42:48.691+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt and  @Leo Moser (mole99)
I would like to document this somehow.
In the TT layout there is `VDD IO` `PWR Aux` and `VDD Core` These are not tied together on the COB PCB how should they be labeled?
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message-1429736613751296082

2025-10-20T07:42:51.94+00:00 — Andrew Wingate (@anfroholic)

Content

https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0#gid=0
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message-1429736776213463111

2025-10-20T07:43:30.674+00:00 — Andrew Wingate (@anfroholic)

Content

I made a copy of your document to figure some stuff out when I was trying to make the first PCB
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message-1429737132922114100

2025-10-20T07:44:55.72+00:00 — Andrew Wingate (@anfroholic)

Content

sorry, wasn't shared, it is now
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message-1429737688424120381

2025-10-20T07:47:08.162+00:00 — tnt (@246tnt)

Content

@Andrew Wingate They should not be wired together, they might be at different voltages.
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message-1429738075491401828

2025-10-20T07:48:40.446+00:00 — tnt (@246tnt)

Content

VDD IO / VDD Aux / VDD Core.  ( The IO and Core one directly map to the main rings. The "Aux" is meant as bias voltage / aux power for analog stuff ... )
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message-1429738378387263488

2025-10-20T07:49:52.662+00:00 — Andrew Wingate (@anfroholic)

Content

> rings
I do not have those rings on the current COB PCB. Should they be added (or at least tie them together on an inner layer?)
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message-1429738766024708207

2025-10-20T07:51:25.082+00:00 — Leo Moser (mole99) (@mole99)

Content

As for the naming: At the moment there are no separate IO and Core domain since we don't have the pads for that yet (actually we have them, but they are untested).

So for the default wafer.space pinout, all GNDs should be "GND IO/Core" and VDD should be "VDD IO/Core" (even for Aux).

This will change in the future once we have separate domains.
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message-1429738800317464666

2025-10-20T07:51:33.258+00:00 — Andrew Wingate (@anfroholic)

Content

*they* being only `VDD IO` to the other `VDD IO` pins?
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message-1429739074763358260

2025-10-20T07:52:38.691+00:00 — Leo Moser (mole99) (@mole99)

Content

Oh, if we already do power rings for IO/Core then we can think about keeping the naming 🤔
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message-1429739110381129758

2025-10-20T07:52:47.183+00:00 — Andrew Wingate (@anfroholic)

Content

I guess what I'm asking is do we tie them together on the COB, if not, then maybe find different words?

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2025-10-20T07:53:15.751+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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*they currently are not tied*
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message-1429739827875545159

2025-10-20T07:55:38.247+00:00 — Leo Moser (mole99) (@mole99)

Content

@tnt should there be power rings on the breakout for TT?
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message-1429740885406384198

2025-10-20T07:59:50.382+00:00 — tnt (@246tnt)

Content

I don't think that's really necessary. Traces to the pins are thick, and short decoupling is near.

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message-1429741654704783452

2025-10-20T08:02:53.797+00:00 — Andrew Wingate (@anfroholic)

Content

Just call them out as
`VDD{i}`
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message-1429741713819177082

2025-10-20T08:03:07.891+00:00 — tnt (@246tnt)

Content

They should be tied together on any mother board since you don't want to feed different voltages to them.
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message-1429741912214081616

2025-10-20T08:03:55.192+00:00 — tnt (@246tnt)

Content

Like feeding different voltage to VDD IO and VDD Core is fine, but feeding different voltage to different VDD IO pin is a sure way to obliterate the chip.
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message-1429742266565660782

2025-10-20T08:05:19.676+00:00 — Andrew Wingate (@anfroholic)

Content

I am imagining the default layout also comes with decaps as well.
But trying to be forward-looking do you have a suggestion for naming convention?
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message-1429742398363275315

2025-10-20T08:05:51.099+00:00 — Andrew Wingate (@anfroholic)

Content

I'm also content to not change anything and if someone cares enough they can look closer
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message-1429742481427140678

2025-10-20T08:06:10.903+00:00 — tnt (@246tnt)

Content

Well what I said above  GND/VDD  IO/Core/Aux.

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message-1429742697006108742

2025-10-20T08:07:02.301+00:00 — tnt (@246tnt)

Content

It's true that for the current pads, some are technically tied internally ATM, but in the future they should be split so might as well start with that naming now IMHO.

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message-1429751589341630516

2025-10-20T08:42:22.399+00:00 — Andrew Wingate (@anfroholic)

Content

@Tim 'mithro' Ansell There has been significant discussion on what the defaults should be. I have tried to compile the latest/best information I have here
https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs
Please let me know if there's anything you think should be added.

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message-1429753855134007457

2025-10-20T08:51:22.606+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

What's the thinking behind the mezzanine connectors rather then bonding directly?
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message-1429754172533641267

2025-10-20T08:52:38.28+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I'm also not seeing info on the connectors in that repo?
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message-1429754208936263732

2025-10-20T08:52:46.959+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate -^
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message-1429756520522059796

2025-10-20T09:01:58.084+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I have laid out some of the case here: https://discord.com/channels/1361349522684510449/1408134567491145728/1429068742108909638
and here: https://discord.com/channels/1361349522684510449/1408134567491145728/1429265501145534516

A lot of it is logistical. The LGA package can ride along with this as well with no changes.
Some back of the envelope math expecting 1000 pcs is:

panelized mezzanine cob pcbs would need 25 panels (a stack <20mm high)
panelized castellated board from [here](https://discord.com/channels/1361349522684510449/1408134567491145728/1429676570972393594) would need 70 pcbs (a stack ~60mm high)
And the last breadboard version would be **170** pcb panels (a stack ~**275mm** high)

We still should see what the wirebonders have to say, but logistically, if we can keep the panels small we get a lot of gains and think they'd be more willing to work with us.
Also having a standard that's easily customizable and approachable has some benefits of themselves.

Also, good call on the links. I am/was still unsure to lock this in, but sounds good.
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message-1429757514664382474

2025-10-20T09:05:55.106+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate - No reason not to put as much information there even if we remove it later.
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message-1429757701168042068

2025-10-20T09:06:39.572+00:00 — Andrew Wingate (@anfroholic)

Content

Are you going to want all that in the CS update?
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message-1429757853031469176

2025-10-20T09:07:15.779+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Say I want the DIP packaging, it seems like I now have to pay for 2 * connectors which adds ~$0.60 to the cost of packaging?
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message-1429758644932837449

2025-10-20T09:10:24.583+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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That sounds true on the surface, but may be washed out by wirebonders pricing.
If they have a standard setup and they just crank through these, I bet we can get a significant reduction in the $0.01/wire cost
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message-1429759266608255087

2025-10-20T09:12:52.802+00:00 — Andrew Wingate (@anfroholic)

Content

*connector links added to git repo*
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message-1429760529760784435

2025-10-20T09:17:53.961+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Also I don't know where $0.60 is coming from?
Any reasonable qty is <$0.35 for the mating connector. The first connector is included in your COB cost.
https://www.lcsc.com/product-image/C19089262.html

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message-1429761975679975558

2025-10-20T09:23:38.695+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

$0.30 for connector on the COB side and $0.30 for the mating connector on the DIP package side?
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message-1429762390106312745

2025-10-20T09:25:17.502+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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But you have a fixed cost ($1,500) for bonding. The one already fits into that equation.
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message-1429763341441568778

2025-10-20T09:29:04.318+00:00 — Andrew Wingate (@anfroholic)

Content

Furthermore, if there is a true standard, I believe the wirebonders could be more willing to support the people who only want some minimum like (5 panels/ ~250 COB) making it actually cheaper for them
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message-1429763713149435997

2025-10-20T09:30:32.94+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Each 1,000 unit run is pretty much a seperate run as far as the wire bonders are concerned.
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message-1429763947728343161

2025-10-20T09:31:28.868+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

It's $1.50 USD per part - with $0.60 going to connectors?
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message-1429765268858470480

2025-10-20T09:36:43.85+00:00 — tnt (@246tnt)

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I thought the idea was just to ship the modules to customer, so the mating connectors and the board to put them on would be their responsability so to speak.
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message-1429765793356447807

2025-10-20T09:38:48.9+00:00 — Andrew Wingate (@anfroholic)

Content

That as well
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message-1429766102229192734

2025-10-20T09:40:02.541+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I'm thinking of the person who wants DIP ICs
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message-1429767654436110369

2025-10-20T09:46:12.616+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

Furthermore, if someone didn't need as many pins, they could drop down to the 50pin mezzanine connectors dropping the overall cost of connectors by $0.50.
I feel very confident in saying that the cost in the end would be comparable (if not less) adding the mezzanine connectors.
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message-1429767978546630696

2025-10-20T09:47:29.89+00:00 — Andrew Wingate (@anfroholic)

Content

hell, you could even just add the dip pcbs with opposing connectors for the same cost giving the benefit of all worlds
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message-1429778454970372160

2025-10-20T10:29:07.664+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Ultimately, I'll do whatever people ask for / want
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message-1429778792217575495

2025-10-20T10:30:28.07+00:00 — Andrew Wingate (@anfroholic)

Content

Of course
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message-1429782542109769799

2025-10-20T10:45:22.114+00:00 — Andrew Wingate (@anfroholic)

Content

@Tim 'mithro' Ansell You can use these when talking to the wirebonders

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message-1429797180801155074

2025-10-20T11:43:32.25+00:00 — tnt (@246tnt)

Content

There might be a min distance for vscoring between edge of connector and edge of board for the blade to go through.
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message-1429797471336402954

2025-10-20T11:44:41.519+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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It's .4mm and is already added in

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message-1429797534133391453

2025-10-20T11:44:56.491+00:00 — tnt (@246tnt)

Content

Oh wow, they're much better than I though.
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message-1429797730351321179

2025-10-20T11:45:43.273+00:00 — Andrew Wingate (@anfroholic)

Content

Oh you said connector. The v-score is done before PNP at any rate.
All clearances have been accounted for though

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message-1430128990538170532

2025-10-21T09:42:01.856+00:00 — Andrew Wingate (@anfroholic)

Content

https://www.youtube.com/watch?v=JzdelpyRW9E
Wirebonding machine working

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message-1430841776104800287

2025-10-23T08:54:23.178+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt and @Leo Moser (mole99)
I'm designing all the symbols in kicad
I have the COB `Wirebond pads -> Mezzanine`
And then will be making a default `Mezzanine -> Motherboard`
My question is regarding naming conventions for the user pins.
Ideally whatever the pins are called in HDL or wherever the original name comes from would be used or whatever label they contain as generic from the [default template](https://github.com/wafer-space/gf180mcu-project-template) .
*I assume this has the 74pad default?*
Can I get a convention please
-# I also understand there will be a TT specific version but would like to make the generic first

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message-1430843213002051684

2025-10-23T09:00:05.761+00:00 — Andrew Wingate (@anfroholic)

Content

I see the convention starts at index 0 here
https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/config.yaml

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message-1430851801074368522

2025-10-23T09:34:13.317+00:00 — tnt (@246tnt)

Content

Yes it starts at 0 and is usually called pad not pin and 0 is bottom left to match gds orientation

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message-1430853773097697290

2025-10-23T09:42:03.484+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Cool, thanks. So this is what will eventually filter down to the motherboard connector

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message-1430856584480686181

2025-10-23T09:53:13.77+00:00 — Leo Moser (mole99) (@mole99)

Content

Looks good to me, the power/ground pads all match up. The naming is different in the template with pad_0 is clk_PAD, pad_1 rst_n_PAD and pad_3 bidir_PAD[0] ...
But it wouldn't make sense to use that naming as you are free to change the signal pads in any way you like, and this way is more generic 👍
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message-1430857271734173777

2025-10-23T09:55:57.624+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Thanks,
I guess I'm having trouble separating TT specific pin specifiers and what anyone else will do with them.
I'll make a TT version that has
```
ctrl_ena
ctrl_sel_inc
ctrl_sel_rst_n
analog[0]
analog[1]
analog[2]
ui[7]
u_rst_n
u_clk
```
and so on.
But to keep them generic, this is appropriate?
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message-1430870623651106876

2025-10-23T10:49:00.969+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

To keep them generic for the project template, your previous symbol with pad_0 to pad_69 is fine.

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message-1431128538484052179

2025-10-24T03:53:52.657+00:00 — Andrew Wingate (@anfroholic)

Content

Ok, made some much more pretty symbols for the COB components.
That was not fun trying to unwind the pin numbers and nets.

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message-1431132353870303322

2025-10-24T04:09:02.316+00:00 — Andrew Wingate (@anfroholic)

Content

I don't like that the ground pins are not spaced well.
I am going to do some pin shuffling. I plan to move one of the grounds from the pink pin to the green location.

@Leo Moser (mole99) or @tnt Are there any changes you'd like to see?

Also KiCad allows to have aliased pin names. So I'm going to do that for the TT pins and it all can remain the same symbol. It also allows you to have different electrical properties so I'll fill those in for the people who want to do ERC

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message-1431147871863967754

2025-10-24T05:10:42.094+00:00 — Andrew Wingate (@anfroholic)

Content

Not sure if people know about this other project @Tim 'mithro' Ansell helped to bring us. He helped bring Kicanvas.
I have created a link to see these designs in your browser [here](https://kicanvas.org/?github=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2Fscratch%2Fmezzanine%2Fmezzanine)
Thanks Tim, I've used this on a number of occasions!
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message-1431167974030573700

2025-10-24T06:30:34.824+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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I would prefer the symbol on the right, as it resembles the actual positions of the pads in the padring. What is the reason or benefit of the symbol on the left? Too many options might also be confusing.
Pin aliases sound great for the TT symbol!
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message-1431173767928746064

2025-10-24T06:53:36.197+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

The one on the left is the mezzanine connector, these are how the signals make it down to the motherboard.
I will likely change it a bit then when I get the pin mapping sorted and we can see what we like.
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message-1431177275574976582

2025-10-24T07:07:32.485+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Thanks for the clarification, that makes sense :)
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message-1431517499001798737

2025-10-25T05:39:28.071+00:00 — Andrew Wingate (@anfroholic)

Content

@Leo Moser (mole99) The one on the far left would be for someone that wants to design a motherboard for TT COB
The one on the right is wild west and the one in the middle is the exact same as the one on the right, but is using pin alias names.
Let me know if you want a different arrangement of the one on the left, but all 3 are electrically identical.

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message-1431637886314352834

2025-10-25T13:37:50.643+00:00 — Andrew Wingate (@anfroholic)

Content

I've also updated the example motherboards with the new footprints/pin mappings.

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message-1431639061461991484

2025-10-25T13:42:30.82+00:00 — Andrew Wingate (@anfroholic)

Content

There are some open questions regarding what pins we decide to break out like if we only keep 2 grounds and combine all the power pins on their respective nets we save like 10 pins.
Keeping it on the COB itself there are some tight spots (I can do much better, just wanted something now) or we can move to 4layer boards.

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message-1431640609545781378

2025-10-25T13:48:39.912+00:00 — tnt (@246tnt)

Content

For me the power rails could be shorted on the mother board.
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message-1431640702139502703

2025-10-25T13:49:01.988+00:00 — tnt (@246tnt)

Content

Actually it would even be better they are
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message-1431640741284941854

2025-10-25T13:49:11.321+00:00 — Andrew Wingate (@anfroholic)

Content

VDD_IO, VDD_VORE and PWR_AUX?
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message-1431641037146816623

2025-10-25T13:50:21.86+00:00 — Andrew Wingate (@anfroholic)

Content

in the example above each respective is shorted, but all are broken out as well adding to 70pins
*current schematic*

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message-1431641345650462872

2025-10-25T13:51:35.413+00:00 — Andrew Wingate (@anfroholic)

Content

I feel like people will want to make neat boards for TT, but don't know what the demand is, or if these are what anyone would even be looking at.
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message-1431641827533918260

2025-10-25T13:53:30.303+00:00 — Andrew Wingate (@anfroholic)

Content

coincidentally LCSC has just added another even cheaper connector of the same size
https://www.lcsc.com/product-detail/C49451471.html

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message-1431949282944221267

2025-10-26T10:15:13.385+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt and @Leo Moser (mole99)
I'm working to get some padframe/ cob/ wirebonding standards that will be offered compiled for an upcomming update.
Obviously there is the 74pad version with the 70pin mezzanine. I think that's been pretty solidified.

I am looking for anything else, and what we think people would want. @Tholin you seem to be the only other one who has expressed interest in another--that being a dip version. Is this what you want? Would you be opposed to having a dip version that looks like these versions above, where the actual dip layout is in fact a carrier? https://discord.com/channels/1361349522684510449/1408134567491145728/1431637886314352834

If we're looking for some other version that would be lower cost, what would you all think of a 50pin mezzanine, this could have 55pads or so? The cost difference from 40pin to 50pin is basically 0, so real difference is offers from wirebonder.

Sharing the source and production files will already be done. But also have a relationship to Mouser through CS so if we wanted them to stock panels of DIP carrier boards that fit our *to be determined standard* I'm sure this is something that can happen if we think there will be some kind of demand.

@Leo Moser (mole99) I'm pretty sure there are some other files somewhere that map the [config](https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/config.yaml) to the actual pad locations. Having another padframe obviously has some overhead, do you want to speak for a second standard?

@Tim 'mithro' Ansell your opinions as well?

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message-1432035294785569019

2025-10-26T15:57:00.206+00:00 — Andrew Wingate (@anfroholic)

Content

Still a little curious about wirebonder capabilities/ input medium.
I found this one by [yamaha](https://www.yamaha-robotics.com/en/products/process/utc-5000super)
work area:
Width: 20– 95 mm (20–93 mm when carrier type)
Length: 95～300mm
https://www.youtube.com/watch?v=-43dpkL5N7w

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2025-10-27T07:30:49.074+00:00 — Leo Moser (mole99) (@mole99)

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Started a thread.
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2025-10-31T08:59:59.366+00:00 — Leo Moser (mole99) (@mole99)

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Poor Man's Intro to Bonding: https://youtu.be/_xRH6R4bn-4?si=Rb_vWIx_BTgcD5vM

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message-1434260402845388901

2025-11-01T19:18:47.308+00:00 — Mark Anderson (@markemer)

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NIST lets you rent dicing saws and wire bonders by the hour. So does RPI in Troy, NY.

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2025-11-04T00:02:51.031+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Andrew Wingate / @carlfk -^
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2025-11-04T00:18:35.452+00:00 — Brian Swetland (@dnaltews)

Content

So the <https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs> repository talks about "default" designs that must share the wirebonding layout, PCB size (14mm x 16mm), connector location (if present).  Is the implication here that the crowd supply run will allow one to provide their own design that fits those constraints or is it expected that there will be one specific layout selected to be used by all COB orders?
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2025-11-04T00:34:20.224+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Brian Swetland - The expectation is that a number of designs will be selected as supported by the crowd supply run.
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2025-11-04T01:13:31.48+00:00 — Andrew Wingate (@anfroholic)

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I did see that. Where is NIST?
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2025-11-04T01:14:48.131+00:00 — Tim 'mithro' Ansell (@mithro_)

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No idea 🙂
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message-1436319557626232883

2025-11-07T11:41:08.065+00:00 — Leo Moser (mole99) (@mole99)

Content

@Tim 'mithro' Ansell @Andrew Wingate Could you please tell me what the minimum spacing between the bondpads is for CoB packaging? The bondpads are 60µm x 60µm.
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2025-11-07T11:42:17.091+00:00 — Andrew Wingate (@anfroholic)

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Are you talking about the PCB? Or the die?
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2025-11-07T11:42:29.766+00:00 — Leo Moser (mole99) (@mole99)

Content

About the die.
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message-1436320815216984125

2025-11-07T11:46:07.898+00:00 — Andrew Wingate (@anfroholic)

Content

I really have no idea other than the document Tim sent me.
https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view
Looks like 15µm between pads

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message-1436321745001910272

2025-11-07T11:49:49.576+00:00 — Leo Moser (mole99) (@mole99)

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Thanks! That's much better than I had expected.
@Tim 'mithro' Ansell can you confirm?

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2025-11-07T11:52:24.811+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Weren't you going to bed? 😛

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message-1436322685234974871

2025-11-07T11:53:33.745+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

I don't have any actual specs from the Chinese vendors at the moment -- the more spacing we can get the better I think?

@stuart - What are the requirements for your vendor?
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message-1436923058945396919

2025-11-09T03:39:13.992+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://www.youtube.com/watch?v=_xRH6R4bn-4

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message-1436926129138303089

2025-11-09T03:51:25.983+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Seems like the full talk can be found at https://www.youtube.com/watch?v=dNBwY7L6niI (with worse audio it seems)

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message-1438469141483753556

2025-11-13T10:02:48.794+00:00 — Matt Venn (@mattvenn)

Content

@stuart 's doing some TT COB today, and I wanted to share this lovely photo!

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message-1438514780078997514

2025-11-13T13:04:09.883+00:00 — db (@ddddbbbb)

Content

looks nice! is that by manual wirebonder or programmed?
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message-1438551642558435388

2025-11-13T15:30:38.583+00:00 — stuart (@saladchap)

Content

Programmed, we'll be sharing some more photos and info about the process soon 🦋
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message-1438552043324440638

2025-11-13T15:32:14.133+00:00 — stuart (@saladchap)

Content

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message-1438552065260519539

2025-11-13T15:32:19.363+00:00 — stuart (@saladchap)

Content

Here's one post-glob
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message-1438558458495500328

2025-11-13T15:57:43.629+00:00 — db (@ddddbbbb)

Content

programmed is the dream. I've assembled a lot of parts with a west-bond but someday I hope to find an affordable programmable bonder
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message-1438566326305030145

2025-11-13T16:28:59.461+00:00 — Tholin (@tholin)

Reply/reference

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Content

Yes, please share! I need to learn more about wire bonding if I wanna be able to bond my own chips one day soon.
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message-1439007257730879672

2025-11-14T21:41:05.705+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

Who's padring and die is that?
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message-1439008922903253103

2025-11-14T21:47:42.713+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell It's TT08, sky130 default pad ring.
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message-1439014195789299813

2025-11-14T22:08:39.867+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I guess I actually ment the cob ring
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message-1439151682557841459

2025-11-15T07:14:59.267+00:00 — tnt (@246tnt)

Content

Ah, it was done by @htamas  ( https://github.com/htfab/breakout-tt08-cob )
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message-1441467554517487678

2025-11-21T16:37:26.169+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Hello, I am really late to the party, just finished reading the channel contents. On the plus side Z80 is all dandy and passing prechecks without violations.

Similar to @Tholin I am interested in the DIP PCB.

DIP is for Z80. That means only 40 pins all digital 5V. Classical DIP40.

My preferences:
1) first would be **small LGN** pcb as long as it can be soldered onto DIP PCB without destroying the wirebonding.
2) second would be binding chip directly to **DIP40 PCB** where I can route GND **(to pin 29)** and VDD** (to pin 11 of the DIP40)**.

Mezzanine - while very flexible I am worried that it would make the final package look "weird" and too high, also I still not sure what would that mean to the final cost. So for Z80 I would say it as a Plan C.

**Just to clarify, is LGN option still on the table?**
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message-1441467846780518492

2025-11-21T16:38:35.85+00:00 — Tholin (@tholin)

Content

On a PCB, you can route any pad on the COB footprint to any pin on the headers - that’s no problem.
I am trying to keep compatibility with DIP-40 ceramic carriers where those connections are fixed.
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message-1441467889088462972

2025-11-21T16:38:45.937+00:00 — Tholin (@tholin)

Content

So I had to move around some VDD/VSS pads
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message-1441467985347870852

2025-11-21T16:39:08.887+00:00 — Tholin (@tholin)

Content

And can thus no longer use the mezzanine breakout as it makes assumptions about the locations of the ground pads and wires them all to a ground plane.
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message-1441468036640014398

2025-11-21T16:39:21.116+00:00 — Tholin (@tholin)

Content

So, I’m also interested in other options.
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message-1441468259361751131

2025-11-21T16:40:14.217+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Content

Just to clarify VDD/VSS pads - you had to move them on the chip ring layout or outside (on PCB)?
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message-1441468286536515785

2025-11-21T16:40:20.696+00:00 — Tholin (@tholin)

Content

The chip ring layout

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message-1441470066578296853

2025-11-21T16:47:25.091+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Content

I looked at your reference to DIP-40 ceramic carrier and I wonder how did they managed to put Z80 in ceramic back in the day, because they have VDD/GND not on 40/20 pins.

Did they have special ceramic packages for them? (unfortunately I don't have Z80 in ceramic for inspection)
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message-1441470292827574345

2025-11-21T16:48:19.033+00:00 — Tholin (@tholin)

Content

The ceramic carrier makes no assumptions about the location of the power pins. It simply breaks the 40 pins out to 40 bonding pads.
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message-1441470512625619179

2025-11-21T16:49:11.437+00:00 — Tholin (@tholin)

Content

There is a metal plane at the base of the cavity, but you have to bond it to the ground pin yourself by running a wire from the carrier’s bond bad to the plane.
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message-1441470529750958284

2025-11-21T16:49:15.52+00:00 — Tholin (@tholin)

Content

At least, that is how I understand it.
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message-1441470666279878686

2025-11-21T16:49:48.071+00:00 — Tholin (@tholin)

Content

But I still had to customize my die’s padring since I am replicating existing chips and thus need specific ground/power connections.
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message-1441471877305471168

2025-11-21T16:54:36.802+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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OK, I think I understood what you are saying. Ceramic unlike PCB enforces a very strict wiring between the padring and DIP pins.

So you have to match the pin locations to the original chip essentially.
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message-1441472087884697743

2025-11-21T16:55:27.008+00:00 — Tholin (@tholin)

Content

Yes. And now I can’t use the mezzanine breakout because it assumes that the ground pads are in specific locations.
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message-1441472224476528721

2025-11-21T16:55:59.574+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Yes, makes sense.
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message-1441472360887746561

2025-11-21T16:56:32.097+00:00 — Tholin (@tholin)

Content

This could technically be solved by creating a "dumb" version of that breakout that just routes each pad to a pin on the mezzanine without making any assumptions, with the PCB ground plane unconnected to any chip pads and routed to a spare mezzanine pin. This I *could* use for prototyping, as long as I also still get raw dies for my ceramic carrier experiments!

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message-1441472509408051470

2025-11-21T16:57:07.507+00:00 — Tholin (@tholin)

Content

But ultimately, I resigned myself to coming up with my own solution.
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message-1441476506982289532

2025-11-21T17:13:00.603+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

For LGN option, I also wonder, if it would be possible to have a narrower LGN board? (while keeping bonding pattern in the same way as “normal” LGN if it reduced the price / headache. Some internal pads would simply left unconnected for some pads)
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message-1441476557657870346

2025-11-21T17:13:12.685+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Sorry for extremely crude art
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2025-11-21T17:13:58.697+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

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message-1441477672147488892

2025-11-21T17:17:38.4+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

The reasoning here is that it might not fit on DIP otherwise.

Classic DIP has less than 14 mm on the top and “fake” PCB DIPs might have protruding pins from below
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message-1441477691558592563

2025-11-21T17:17:43.028+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

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message-1441516762196607026

2025-11-21T19:52:58.194+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I will be taking one more pass at the cob PCB, I will try to be more amenable to changes with this revision.
Ultimately there are more pins on the die than there are on the mezzanine, so there will be some considerations needed there.

Afaik we still have not had any real conversations with wirebonders so are still not sure on what they are willing to accept for deviations from the norm.
I still think that as long as bonding locations and overall form factor remain constant we should be able to have a lot of variations.
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message-1441518540019466462

2025-11-21T20:00:02.06+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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The LGA version is temporarily abandoned given concerns over reflowing and types of epoxies after wirebonding.
I have also ordered some 50pin mezzanine connectors to play with for a lower pin count version. The cost for these connectors is quite affordable even at quantity.

https://www.lcsc.com/product-detail/C2763977.html
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message-1441528914425020607

2025-11-21T20:41:15.511+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Is there a prototype bonding plan for 50pin mezzanine connector somewhere I could take a look? I think I only found a 70pin version in the repo.
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message-1441529047724200106

2025-11-21T20:41:47.292+00:00 — Andrew Wingate (@anfroholic)

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Sorry, no, It's just something I've been talking about doing.
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message-1441529239118807101

2025-11-21T20:42:32.924+00:00 — Andrew Wingate (@anfroholic)

Content

There is no padring yet, so not sure what anything will look like.
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message-1441530105313624196

2025-11-21T20:45:59.441+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

For retro DIP40 I am gravitating to use primarily North and South side (32 pins) of the padring and the rest put as close to the corner as possible.

Dunno if that might be a stupid idea?

The reasoning is to keep sides as empty as possible in case LGA comes back and I could keep it narrow.
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message-1441530784501731430

2025-11-21T20:48:41.372+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Would / could that be compatible with 50pin mezzanine layout you are thinking about?
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message-1441532429494911017

2025-11-21T20:55:13.569+00:00 — Andrew Wingate (@anfroholic)

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That sounds close to what I had in mind.
Like I said above to @Tholin I think for now the safest bet could be to consider this a subset of the standard wirebonding frame.
I have ordered the board you see posted here and I'll be taking another pass at it and probably be shrinking some parts making the whole thing more narrow.
Also hopefully soon we will have open dialogs with wirebonders and we'll get a lot more info about what's best/possible/etc.

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message-1441539406908493856

2025-11-21T21:22:57.114+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Could you explain why do you say that it is a *subset* of a wirebonding scheme?

I think I see all the pads from the chip pad frame (at least @Leo Moser (mole99)’s template) exposed and bondable. I am I missing something?
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message-1441541392374698077

2025-11-21T21:30:50.486+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I mean (and this is still my opinion only) that toolchains could remain more simple if we only change a few things at a time with the wirebonders, so the wirebonding frame would still have bonds at the same locations. Again, I don't know a lot of things, and what constitutes *different* as far as their pattern matching and other toolchains consider the same or not.
With the deadline looming, I don't know how many variations there will be in this run. But will try to keep everyone updated as I go along.

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message-1441709551840923782

2025-11-22T08:39:02.827+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Leo Moser (mole99) what is more advisable & future proof when **defining the mapping between the core signals and pads on a padring**?
 Imagine I have 16-bit address bus of the retro chip and I want to assign them to a particular physical pads, should I better
a) change the binding order in `config.yaml` modifying `PAD_SOUTH`,`PAD_EAST` ...
NOT changing power pad locations! Those stay always the same as in the template.
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message-1441709683629887508

2025-11-22T08:39:34.248+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

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message-1441710338838892595

2025-11-22T08:42:10.462+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

or
b) only change how it is defined in Verilog file, say in `chip_core.sv`, but never touch `config.yaml` PADs
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message-1441710355494469692

2025-11-22T08:42:14.433+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

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message-1441750156478382232

2025-11-22T11:20:23.727+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Hi ReJ! I'm not sure what you mean by "future proof". Do you mean in regards to code changes to the template?

The easier way is to change it in the RTL, as you only need to connect your signals to the bidir vector. However, it may be confusing to keep track of all the signals in bidir.

That's why I think the better apporach would be to make another `generate` loop that instantiates the pads for the address bus and give it a better name than `bidir`, e.g. `addr_bus`. You would then need to reduce the number of bidir pins accordingly.
Finally, you can add the `addr_bus\\[x\\].pad` instances to the yaml (and remove some of the bidir instances).

Unfortunately, when the upstream template changes, this approach may lead to more conflicts.
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message-1441774136874762350

2025-11-22T12:55:41.099+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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TBH, I am mostly worried that if touch something in `config.yaml` the pad's physical locations will change 😓  maybe an unfound fear
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message-1441780160008294410

2025-11-22T13:19:37.126+00:00 — LukeW (@luke_w)

Content

I did update my pad config (here https://github.com/Wren6991/RISCBoy-180/blob/b3dc3bb41600123395ae37ca25f37694c35ff448/librelane/config.yaml#L150-L260) and left in lots of comments for the fixed locations of the VDD/VSS pads. Still quite paranoid and it's on my list of things to re-check before submission, but I thought this was less painful overall because I can use the correct pad names in IO constraints etc.

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message-1441780251758821480

2025-11-22T13:19:59.001+00:00 — LukeW (@luke_w)

Content

Are there any automated checks for VDD/VSS locations remaining compatible with the COB breakout?

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message-1441787240367001732

2025-11-22T13:47:45.215+00:00 — Leo Moser (mole99) (@mole99)

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As long as you keep the same number of pads on each side, you will be fine :)
All of the I/O pads in gf180mcu are the same width. So, when LibreLane places them equidistant from each other, you will always get the same bondpad loactions.

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message-1441787967042490440

2025-11-22T13:50:38.468+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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There aren't any checks for that yet.

I could add one based on the XOR of the pad layer. However, this would probably only be for the second shuttle, as it requires information from the online platform on whether the user has selected the CoB option or not.
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message-1441789001848848596

2025-11-22T13:54:45.185+00:00 — Leo Moser (mole99) (@mole99)

Content

If you mean checking whether there are actual VDD/VSS cells at these locations. This would require checking the cells themselves, which would be impratical. Someone could do a custom design which uses a different kind of power/ground cells.
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message-1441792274525847714

2025-11-22T14:07:45.452+00:00 — LukeW (@luke_w)

Content

Ok, I'll do a "manual DRC" for this run 😄

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message-1442105482599731280

2025-11-23T10:52:20.076+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Please excuse my ASCII art, but I am struggling to map the names from the https://github.com/wafer-space/gf180mcu-project-template to the https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs
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message-1442105632550420520

2025-11-23T10:52:55.827+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

```
                              52  50  48  46  44  42  40  38
                            53| 51| 49| 47| 45| 43| 41| 39| 37
                            | | | | | | | | | | | | | | | | |
                     ,------v-v-v-v-v-v-v-v---v-v-v-v-v-v-v-v-------.
                     |      a a b b b b b b G b b b b b b b b       |
               54 -->|i_0   1 0 3 3 3 3 3 3 N 3 3 3 3 2 2 2 2   VDD |+-- 36
               55 -->|i_1       9 8 7 6 5 4 D 3 2 1 0 9 8 7 6   GND |--- 35
               56 ---|GND                                       VDD |+-- 34
               57 --+|VDD                                       GND |--- 33
               58 -->|i_2                                       b_25|<-> 32
               59 -->|i_3                                       b_24|<-> 31
               60 -->|i_4                                       b_23|<-> 30
               61 -->|i_5                   |                   b_22|<-> 29
               62 ---|GND                 WAFER                 b_21|<-> 28
               63 --+|VDD                -SPACE-                b_20|<-> 27
               64 -->|i_6                 GF180                 GND |--- 26
               65 -->|i_7                   |                   VDD |+-- 25
               66 -->|i_8                                       b_19|<-> 24
               67 -->|i_9                                       b_18|<-> 23
               68 -->|i_10                                      b_17|<-> 22
               69 -->|i_11                                      b_16|<-> 21
               70 ---|GND                                       b_15|<-> 20
               71 --+|VDD                                       b_14|<-> 19
               72 ---|GND   c r b b b b b b G b b b b b b b b   GND |--- 18
               73 --+|VDD   l s 0 1 2 3 4 5 N 6 7 8 9 1 1 1 1   VDD |+-- 17
                     |      k t             D         0 1 2 3       |
                     `------^-^-^-^-^-^-^-^---^-^-^-^-^-^-^-^-------'
                            | | | | | | | | | | | | | | | | |
                            0 | 2 | 4 | 6 | 8 | 10| 12| 14| 16
                              1   3   5   7   9  11  13  15
```

Is this reasonable?
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message-1442106401198444554

2025-11-23T10:55:59.087+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

`i_0` .. `i_11` input_PADs
`b_0` .. `b_39` bidir_PADs
`a_0`, `a_1` analog_PADs
based on the template default configuration
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message-1442106609621799114

2025-11-23T10:56:48.779+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Andrew Wingate , @Leo Moser (mole99) could you please validate if I didn't screw up the orientation here?
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message-1442107471505260687

2025-11-23T11:00:14.268+00:00 — tnt (@246tnt)

Content

pad 0 is what you called pad 20 on the drawing above. But the position of power pads seems to match at least.
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message-1442107686023074015

2025-11-23T11:01:05.413+00:00 — Andrew Wingate (@anfroholic)

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You unfortunately did. You made the same mistake I did when I was originally trying to unwind all this.
I will continue to push that something similar to what you have here should be the standard, but the way it is now is that pin 0 is at the bottom left and then goes counterclockwise.
I have a spreadsheet here that may help you to unwind it.
https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0#gid=0
My brain thinks it's backwards as well

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message-1442109079974838292

2025-11-23T11:06:37.757+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

fixing
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message-1442110862444855482

2025-11-23T11:13:42.731+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

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message-1442111042070122497

2025-11-23T11:14:25.557+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Andrew Wingate thanks for adding template pin names in that spreadsheet! That's very helpful!
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message-1442111195988492389

2025-11-23T11:15:02.254+00:00 — Andrew Wingate (@anfroholic)

Content

I'm trying to but things are still backwards..... ugh...
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message-1442114419839467664

2025-11-23T11:27:50.88+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt can you look at my spreadsheet and tell me if I got this right?
I am pretty sure I have east and west correct, but not sure if north and south line up.
https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0#gid=0

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message-1442114625159168031

2025-11-23T11:28:39.832+00:00 — Andrew Wingate (@anfroholic)

Content

I'm trying to match them up from the pad instance names from the template https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/config.yaml

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message-1442119192072687699

2025-11-23T11:46:48.669+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Now if I put it into COB orientation (**that is the most important part for me**):

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message-1442119981297958922

2025-11-23T11:49:56.835+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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~~I'm going to say that  I think you have what  is the bottom row mirrored here.~~
@ReJ aka Renaldas Zioma sorry no, I think this is correct
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message-1442120265260863528

2025-11-23T11:51:04.537+00:00 — Andrew Wingate (@anfroholic)

Content

But **do not** take my word for it
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message-1442129203947638864

2025-11-23T12:26:35.686+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

So the chip is **180 degrees rotated** (in relation to GDS orientation) when put on COB PCB and is NOT flipped, is that correct?
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message-1442129620903268372

2025-11-23T12:28:15.096+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Yes, I should update the picture.
The schematic symbol could be more useful.

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message-1442129929541259347

2025-11-23T12:29:28.681+00:00 — Andrew Wingate (@anfroholic)

Content

You can have this one if you like

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message-1442133731832758323

2025-11-23T12:44:35.218+00:00 — Andrew Wingate (@anfroholic)

Content

This is maybe more in line with what you're thinking.
Now things are *landscape* but the numbering fits convention a little better.
Conventions are hard and not everyone will always agree on things.

Another one that has thrown me many times using CAD packages is *top*

Americans think of the screen as a window to a virtual world and top is Z+ and does not matter which way *you* are facing
Germans have *top* as Y+ as if you're imagining the virtual world extending from the tip of your nose.
It's hard to say that one is *the correct* way of doing things.

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message-1442207041593806851

2025-11-23T17:35:53.627+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Tholin FYI, for fun I put chip on top of the diagram for ceramic package that you shared. Although some Z80 wires seems to be problematically bent, maybe it is not too bad.
I don't think ceramic package is in the books for this run, but still interesting to entertain the idea.

Z80 here has a certain advantage of VDD being on the side of DIP40 (pin 11) rather than 20/40.
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message-1442207062036840579

2025-11-23T17:35:58.501+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

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message-1442646275253207152

2025-11-24T22:41:15.092+00:00 — Trevor Peyton (@trev5514)

Content

I'll give this channel a read over tonight, but I'm curious if anyone could answer this faster. Are there any considerations for wirebonding > 70 pins? My design will be roughly 128 pins. I'm swamped currently with the tapeout finalizing my design, but I would be willing to look into doing a dual 70 pin mezzanine connector OR a larger pin mezzanine connector if that might help after the tapeout.
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message-1442647318141599925

2025-11-24T22:45:23.736+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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The standard padframe is 74 pins. You are free to do whatever you like, but going against the standard will likely end up with you having to make your own solutions.
There are larger pin versions, but 70 seemed good at that fit the needs of most at the time.
There were conversations about using multiple connectors, but there were concerns over tolerances and like I said above, 70pins was adequate.
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message-1442647835547009197

2025-11-24T22:47:27.095+00:00 — Trevor Peyton (@trev5514)

Content

@Andrew Wingate Understood I'll try to find those conversations and read them over.
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message-1442648186266325063

2025-11-24T22:48:50.713+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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sure, I posted quite a few pictures around those conversations, so searching `has: images` and maybe `from: @Andrew Wingate` could help
*edit* also add `in: cob` as it's in this channel

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message-1442650678458716201

2025-11-24T22:58:44.898+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Man this is so close. My design needs bare minimum 64 parallel pin bus + a clock signal and rst... Everything else I can cut. It looks like there are exactly 64 GPIO pins free which means I'm two short for the design to work! I'll read later and see if I can change some things around my design, I'd like to use the standard wirebond option if I can make it work.

Scratch that it looks like a little less I just eyeballed it.
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message-1442651907091988642

2025-11-24T23:03:37.827+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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There are something like 10 ground pins on the standard cob, it isn't necessary to have the routing down the cob stay the same as the default.
The part (for now) that seems most important is to keep the wirebonding pads (qty74) and the 74 pads in the default padring, then also the actual PCB to keep the 14x16mm size and the 70pin mezzanine.
@xianglin_pu and the Mosbius team have created their own routing to gain some extra pins by not having so many vss/vcc etc.
https://discord.com/channels/1361349522684510449/1429068742108909638/1429520076536811622
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message-1442653649426976809

2025-11-24T23:10:33.232+00:00 — Trevor Peyton (@trev5514)

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Content

That is perfect! 68 Signal Pins would do it. I'm not framiliar with wirebond process. I'm assuming it's the mapping from the pads to the PCB, are you saying it's possible for us to design our own routing for the PCB and just use the pads as needed?
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message-1442654224176517352

2025-11-24T23:12:50.263+00:00 — Andrew Wingate (@anfroholic)

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A lot is still unknown, we're trying to keep as much standard as is practical possible, but for now, yes, you can have your own routing on the PCB.

Keep in mind that I'll likely be taking another pass and there will be some small changes, so you may want to hold off on designing something now, but overall yes, you can have your own routing on the PCB itself.
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message-1442655245200265330

2025-11-24T23:16:53.694+00:00 — Trevor Peyton (@trev5514)

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Sounds good. If the 68 signal pin version is available, I'll just bank on that for now and keep my design. After the tapeout I'll see where everyone is at and go from there, I haven't had time to look at the PCB design yet anyways. I'll give this channel a read later and hopefully be a little more informed. Thanks for the discussion.

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message-1444688802491928668

2025-11-30T13:57:31.534+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Leo Moser (mole99) FYI, Z80 in quarter size would be almost ceramic package-able, if not for 1 ground that is in the way...

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message-1444689806964556067

2025-11-30T14:01:31.019+00:00 — Leo Moser (mole99) (@mole99)

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We might redo the default pinout for the second shuttle, since we may require additional power/ground pads. Perhaps we could find a pinout that works for ceramic as well.

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message-1444820942462259262

2025-11-30T22:42:36.158+00:00 — kris (@kris____)

Content

a ceramic package would be so pretty

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message-1444875684148281364

2025-12-01T02:20:07.593+00:00 — Tim 'mithro' Ansell (@mithro_)

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And expensive!

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message-1444876574544363541

2025-12-01T02:23:39.88+00:00 — kris (@kris____)

Content

how much does it compare to the other packages?
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message-1444876840207519795

2025-12-01T02:24:43.219+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I've seen prices like O($100) USD per package
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message-1444877046512881755

2025-12-01T02:25:32.406+00:00 — kris (@kris____)

Content

ooh ouch 🥲
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message-1444877320807518348

2025-12-01T02:26:37.803+00:00 — kris (@kris____)

Content

time to buy a kiln and make some casts lol
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message-1444914911313395762

2025-12-01T04:56:00.078+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

I wonder if that is a real thing

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message-1445020866621734983

2025-12-01T11:57:01.792+00:00 — Tim 'mithro' Ansell (@mithro_)

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Kinda looks like reclaimed device?
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message-1445081880671031488

2025-12-01T15:59:28.675+00:00 — Matt Venn (@mattvenn)

Content

leadframe looks intact to me

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message-1445090353228026068

2025-12-01T16:33:08.69+00:00 — ReJ aka Renaldas Zioma (@rzioma)

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imho should be new

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message-1445094495111876800

2025-12-01T16:49:36.192+00:00 — kris (@kris____)

Content

what is that part?
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message-1445099163233550468

2025-12-01T17:08:09.159+00:00 — ReJ aka Renaldas Zioma (@rzioma)

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I dunno, but I saw them on the other photos with new ceramic packages. Perhaps something that is used to hold them while bonding.
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2025-12-01T17:11:02.08+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

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message-1445099904773914725

2025-12-01T17:11:05.956+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Maybe just part of the manufacturing process
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message-1445106685893939240

2025-12-01T17:38:02.701+00:00 — Matt Venn (@mattvenn)

Content

Yes exactly, after bonding it gets snipped off

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2025-12-01T17:56:56.079+00:00 — kris (@kris____)

Content

ohh that’s interesting, the holes in the first one make it look like it can be daisy chained with other ones
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2025-12-05T12:50:20.467+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

I think it normally is… it comes as a continuous strip. The one pictured has already been snipped off the strip.
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2025-12-05T12:50:33.429+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

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(I think)
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message-1446768639687655425

2025-12-06T07:42:03.363+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I've seen them come in large metal panels.
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message-1447784913708384307

2025-12-09T03:00:21.971+00:00 — Andrew Wingate (@anfroholic)

Content

Hey all,
Just got some PCBs back today for prototyping and verification.
*edit: also note these are HASL, while real versions will be ENIG. It didn't seem worth $75 for just pictures*

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2025-12-09T03:00:31.514+00:00 — Andrew Wingate (@anfroholic)

Content

I will try and assemble a few tomorrow *no die, just mezzanine connectors and headers*
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message-1447786037525872662

2025-12-09T03:04:49.91+00:00 — Andrew Wingate (@anfroholic)

Content

Mezzanine connectors also arrived today.

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message-1447787649095172096

2025-12-09T03:11:14.138+00:00 — Andrew Wingate (@anfroholic)

Content

Last night I also played for a few minutes with another layout for the wirebonders.
This would also fit into a dip package layout.

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2025-12-09T03:11:17.085+00:00 — Andrew Wingate (@anfroholic)

Content

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message-1447812050595090565

2025-12-09T04:48:11.909+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Reply/reference

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Delightful 🙂 I’m getting excited!

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message-1447819004302327902

2025-12-09T05:15:49.802+00:00 — urish

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Diplightful!

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message-1447864157314744512

2025-12-09T08:15:15.119+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Great news!
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message-1447866215404933162

2025-12-09T08:23:25.806+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Is there a minimum distance requirement between the chip and the binding pad on a PCB?
I am thinkng about 0.5x1 chip but rotate 90 degrees for placement.
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message-1447866489838243880

2025-12-09T08:24:31.236+00:00 — tnt (@246tnt)

Content

I think 1.5x~2x the die thickness IIRC.
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message-1447866648957554759

2025-12-09T08:25:09.173+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Yes @tnt you are correct
https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view

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message-1447866907742175332

2025-12-09T08:26:10.872+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

What is the expected thickness of the die?
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message-1447867043201155206

2025-12-09T08:26:43.168+00:00 — Andrew Wingate (@anfroholic)

Content

The ones I have are about 0.7mm
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message-1447867087543341207

2025-12-09T08:26:53.74+00:00 — tnt (@246tnt)

Content

Although the numbers here are way off. IIRC the chips won't be back grinded so it'll be more like 800 um if it's anything like the sky130/ihp ones.
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2025-12-09T08:27:20.621+00:00 — Andrew Wingate (@anfroholic)

Content

I also believe they will not be back grinded
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message-1447867376430354492

2025-12-09T08:28:02.616+00:00 — Andrew Wingate (@anfroholic)

Content

What I drew above is pushing pretty close to the limits in spots
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message-1447868156767895595

2025-12-09T08:31:08.663+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Andrew Wingate btw, those light blue outgoing lines? They don't (always) connect to the red pads. Are these the ideal wire "diretions"?
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message-1447868425774043176

2025-12-09T08:32:12.799+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

I spent maybe 10 minutes on this.
Just sharing for the sake of sharing. The lines you see are just the old lines from the old version and don't really mean anything

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message-1447868576496353321

2025-12-09T08:32:48.734+00:00 — Andrew Wingate (@anfroholic)

Content

Also @ReJ aka Renaldas Zioma
When you all are saying DIP, what width DIP are you referring to?
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2025-12-09T08:34:26.073+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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message-1447869002893230194

2025-12-09T08:34:30.395+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

This one
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message-1447869022095015950

2025-12-09T08:34:34.973+00:00 — Andrew Wingate (@anfroholic)

Content

The wide version that's .6" between centers

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message-1447869052298199121

2025-12-09T08:34:42.174+00:00 — Andrew Wingate (@anfroholic)

Content

haha ok yeah!!
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message-1447869068337090631

2025-12-09T08:34:45.998+00:00 — Andrew Wingate (@anfroholic)

Content

Thank you
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message-1447869145793167451

2025-12-09T08:35:04.465+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

inches are hard! 🙂

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message-1450280963006533776

2025-12-16T00:18:46.498+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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2025-12-16T00:19:14.603+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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2025-12-16T05:14:16.734+00:00 — Andrew Wingate (@anfroholic)

Content

Forgive the fact this is LTT, but this one is a factory tour of a fab, touches on packaging and a bunch of other steps we're working on.
I thought it was pretty cool
https://www.youtube.com/watch?v=ivLvsTnp9fI

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2025-12-16T05:19:16.512+00:00 — Tea-Rex (@the.tearex)

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I really enjoyed that video. better than the recent hisense tour, and even better than the intel video.
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2025-12-16T05:19:42.06+00:00 — Tea-Rex (@the.tearex)

Content

It probably won’t be a great performer for LMG, but that doesn’t matter—it’s still cool

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2025-12-16T05:30:42.239+00:00 — Andrew Wingate (@anfroholic)

Content

Just assembled the first test COB.
I think I pretty much like the form factor.
With 70pins they hold on there pretty good.

Some conversations with other people, they had mentioned mezzanine connectors to the a weak point, but these seem pretty solid.

I think I'm pretty happy with them overall.

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2025-12-16T08:40:46.745+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

I love the small metallic rocket in the corner!

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message-1450407457225441301

2025-12-16T08:41:25.07+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

On the real ones it will be gold colored

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message-1450521801586380922

2025-12-16T16:15:46.89+00:00 — BreakingTaps (@polyfractal)

Content

looks amazing 🤩

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message-1450788961726365796

2025-12-17T09:57:22.831+00:00 — Andrew Wingate (@anfroholic)

Content

I soldered some headers on and put it on a breadboard.
It's a little on the large size, but should work great if you need it.

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message-1450881837713850521

2025-12-17T16:06:26.192+00:00 — BreakingTaps (@polyfractal)

Content

I see the PDK has rules for bumping, is that a thing we could get from GF in the future?  https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4.html

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message-1450884034333905047

2025-12-17T16:15:09.907+00:00 — Andrew Wingate (@anfroholic)

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Content

I have also brought up WCSP before. It seems there are a few issues.

1. Just the extra cost, it would require more masks and processes.
2. It seems the people who do the bumping are not interested in the quantities we're doing.
3. Everyone would have to agree on a standard pinout. (I don't see this one as a dealbreaker, but poses some issues when we try to subdivide dies into smaller forms, or probably worse going in the other direction for a larger than standard size like you were asking for for more sram.)

It certainly is something that would be very useful if we can devise a way to make it work under all these constraints.
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message-1450885791738888399

2025-12-17T16:22:08.905+00:00 — BreakingTaps (@polyfractal)

Content

makes sense, thanks @Andrew Wingate! was contemplating chiplet'y things to get more SRAM and simple "bridge" interposers using bumps was a potential candidate 😇

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message-1450886993738207262

2025-12-17T16:26:55.484+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

It's very long
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message-1450887151733702709

2025-12-17T16:27:33.153+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

It is, but it's also all 70 pins
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message-1450887247359639663

2025-12-17T16:27:55.952+00:00 — asic destroyer (@logic_destroyer)

Content

It's not possible to use a shorter one?
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message-1450887629116801154

2025-12-17T16:29:26.97+00:00 — asic destroyer (@logic_destroyer)

Content

I’m using SDRAM in my design

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message-1450887677372272713

2025-12-17T16:29:38.475+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Of course it is.
But you'd have to know the pins you could bridge (VCC, VDD, etc.)
This thing was made just to fit whatever anyone did, and more to just make something to play with than something that may actually be useful.
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message-1450887941902700654

2025-12-17T16:30:41.544+00:00 — asic destroyer (@logic_destroyer)

Content

Sorry to ask, but why do we need an adapter board?
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message-1450888447463133375

2025-12-17T16:32:42.079+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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You don't. This was more of an example for people who get the COB version.
Ideally you'd have your own motherboard that did whatever you wanted and just had the mating 70pin mezzanine connector assembled so you could put your chip on however you wanted

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message-1450888649448231124

2025-12-17T16:33:30.236+00:00 — asic destroyer (@logic_destroyer)

Content

COB version is a naked chip?
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message-1450889190068981913

2025-12-17T16:35:39.13+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

COB (Chip On Board)
The COB is the small 14mm x 16mm pcb that is on the top.
Your die would be wirebonded to that and then you can do whatever you want after, but don't have to find a way to wirebond yourself as it's not as accessible as PCBA

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message-1450889379009663086

2025-12-17T16:36:24.177+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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How is something like that soldered onto the PCB?
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message-1450889635201810492

2025-12-17T16:37:25.258+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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That is wirebonded and covered in clear epoxy
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message-1450889718408675368

2025-12-17T16:37:45.096+00:00 — asic destroyer (@logic_destroyer)

Content

Wirebonded from GF?
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message-1450889822314041495

2025-12-17T16:38:09.869+00:00 — Andrew Wingate (@anfroholic)

Content

No they found their own people to do the wirebonding
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message-1450889930917281895

2025-12-17T16:38:35.762+00:00 — asic destroyer (@logic_destroyer)

Content

That means we get such PCB with CHIP (COB)
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message-1450889942816391220

2025-12-17T16:38:38.599+00:00 — asic destroyer (@logic_destroyer)

Content

?
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message-1450890419922538739

2025-12-17T16:40:32.35+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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You get just this part with your die wirebonded and the mezzanine connector on the back.
Everything below that (your own motherboard or breakout board) is on you.

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message-1450890830603878590

2025-12-17T16:42:10.264+00:00 — asic destroyer (@logic_destroyer)

Content

I that ok to use only this here?

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message-1450890911352619151

2025-12-17T16:42:29.516+00:00 — asic destroyer (@logic_destroyer)

Content

I need short wires for SDRAM
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message-1450891246544355390

2025-12-17T16:43:49.432+00:00 — asic destroyer (@logic_destroyer)

Content

Sorry if I’m asking basic questions. I’m not fully in the loop, and I don’t have much PCB design experience.
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message-1450892151918694451

2025-12-17T16:47:25.29+00:00 — Andrew Wingate (@anfroholic)

Content

For your own die, you can choose whatever pads you want for whatever.
These were designed respecting the pad choices chosen by Tiny Tapeout as they had the most ready designs available when we started all this.
You're also welcome to design your own COB chip as long as you respect the pad locations on the die, the wirebond pads on the COB PCB, and the location of the mezzanine connector. But going outside the standards will leave all the remaining details to you.
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message-1450892803633840210

2025-12-17T16:50:00.671+00:00 — asic destroyer (@logic_destroyer)

Content

Would it be possible to design one universal board for all designs, despite the SDRAM/SRAM differences and other incompatibilities?
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message-1450893278798024838

2025-12-17T16:51:53.959+00:00 — asic destroyer (@logic_destroyer)

Content

If it’s not possible, I’ll need to ask you more questions here. My assumption is that I’ll need to integrate your COB board via an adapter PCB, considering the Linux SoC’s requirements.
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message-1450895136459460752

2025-12-17T16:59:16.86+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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That's more or less what we have. I am unsure of the exact requirements you're asking for.
Maybe there are others here more knowledgable who can answer these questions.
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message-1450896501235646575

2025-12-17T17:04:42.248+00:00 — asic destroyer (@logic_destroyer)

Content

All good. I can handle the schematic, and probably the PCB layout too, otherwise I’ll just ask. I also want to provide three PMOD interfaces so I can connect an SD card, Ethernet, and Flash through them.
The board only needs the adapter, SDRAM, discrete components, a clock, uart, and the power supplies.

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message-1450897275357368370

2025-12-17T17:07:46.813+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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good old times 🙂

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message-1450897518685716530

2025-12-17T17:08:44.827+00:00 — asic destroyer (@logic_destroyer)

Content

maybe 4 pmods: uart, flash, sdcard, ethernet
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message-1450898689416499220

2025-12-17T17:13:23.951+00:00 — asic destroyer (@logic_destroyer)

Content

@Andrew Wingate Last question: do we get the COB with this connector already attached?

Which connector we should use for the motherboard?

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message-1450898778411237517

2025-12-17T17:13:45.169+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Yes
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message-1450898927456096266

2025-12-17T17:14:20.704+00:00 — asic destroyer (@logic_destroyer)

Content

And which Connector 236 or 262?
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message-1450899180397527110

2025-12-17T17:15:21.01+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Mating connector

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message-1450899245581467838

2025-12-17T17:15:36.551+00:00 — asic destroyer (@logic_destroyer)

Content

Thank you @Andrew Wingate

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2025-12-17T17:16:11.333+00:00 — asic destroyer (@logic_destroyer)

Content

I see, that is a pair 🙂
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message-1451214303838343290

2025-12-18T14:07:32.293+00:00 — Andrew Wingate (@anfroholic)

Content

Came across another packaging tech, an old one.
IBM mst
https://www.youtube.com/shorts/MZRlHEyirCE

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2025-12-18T16:27:10.574+00:00 — asic destroyer (@logic_destroyer)

Content

@RebelMike @psychogenic @Andrew Wingate Hi pros, I have no idea… any advice for me, please?
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message-1451596145108451348

2025-12-19T15:24:50.346+00:00 — asic destroyer (@logic_destroyer)

Content

One more thing I noticed: if an oscillator is used, it has to be an SMD type. According to the dimensions, it still fits underneath the connector. I would have preferred a DIP-4 package so the oscillator could be easily replaced, but it seems I now have to use a 30 MHz SMD oscillator and place it under the connector to keep the trace to the ASIC short. Ideally, the oscillator would have been mounted on top of the connector PCB.
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message-1451596643605680200

2025-12-19T15:26:49.197+00:00 — asic destroyer (@logic_destroyer)

Content

I think you have exactly the same problem. How are you planning to solve it?
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message-1451598024483668020

2025-12-19T15:32:18.424+00:00 — RebelMike (@rebelmike)

Content

I think the first iteration of my host board will have an RP2 on it to allow me to test things and play with the frequency. If I make a standalone version I’d probably go for the chip I mentioned before that buffers the output so trace length isn’t important - or see what other people have done and worked 🙂

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message-1451607838328623248

2025-12-19T16:11:18.227+00:00 — asic destroyer (@logic_destroyer)

Content

Regardless of the solution, the main challenge is the connector and the placement of the oscillator or crystal. Ideally, the oscillator would be mounted on top of the connector board.
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message-1452398266233782293

2025-12-21T20:32:10.925+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@asic destroyer - At some point I think we will have high quality analog IP for clock generation and we can then get rid of things like external oscillators

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message-1452402811991228459

2025-12-21T20:50:14.718+00:00 — asic destroyer (@logic_destroyer)

Content

@Tim 'mithro' Ansell , this COB adapter doesn’t make sense to me for higher frequencies or SDRAM. I talked to Goran—he sees no issue. The solution is to put both the oscillator and SDRAM on the bottom side. My schematic is done; I’ll do the layout in 2–3 months.
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message-1452403429149249548

2025-12-21T20:52:41.86+00:00 — asic destroyer (@logic_destroyer)

Content

I’ll use DIP-8 oscillators, and I want to avoid having any microcontrollers on the board.
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message-1452404003907567787

2025-12-21T20:54:58.893+00:00 — asic destroyer (@logic_destroyer)

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message-1453328098711044159

2025-12-24T10:07:00.263+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

Reply/reference

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AFAIK, you'll always need an external crystal oscillator for accurate clock frequency. I'm not aware of a circuit where oscillation frequency is not dependent on process corner and transistor variations. Alternative is that you need to trim each chip to get wanted clock frequency.
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message-1453328624701669558

2025-12-24T10:09:05.669+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Chips4Makers aka Staf Verhaegen - Depends on how much accuracy you need. With USB2.0 and a bunch of other protocols you care about the relative drift between two computers and you can get away with using a PLL on the incoming data signals.
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message-1454641632103104637

2025-12-28T01:06:31.028+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Essen / @Andrew Wingate / @carlfk - https://www.ebay.com/itm/387551726916

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message-1454673565956964569

2025-12-28T03:13:24.652+00:00 — Andrew Wingate (@anfroholic)

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Content

Awesome!
For those interested in what wafer bonding is. Asianometry has a video
https://youtu.be/2ACiuKgYUkI

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message-1454950491795493061

2025-12-28T21:33:48.917+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Attachments

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message-1454950571940384975

2025-12-28T21:34:08.025+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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nice
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message-1455184620445372651

2025-12-29T13:04:09.537+00:00 — asic destroyer (@logic_destroyer)

Content

Hello, is it true in my case that the chip will consume 13 mW?

```
hd@i9:~/hacking/wafer.space/gf180mcu-kianv-rv32ima-sv32/final $ cat metrics.csv  | grep power__tot
power__total,0.013211173005402088
```
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message-1455348666855456943

2025-12-29T23:56:01.249+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

@Leo Moser (mole99)  @Tim 'mithro' Ansell  😉
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message-1455381197248004196

2025-12-30T02:05:17.099+00:00 — Lofty (@ravenslofty)

Reply/reference

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Most likely not; opensta can use the power information from the liberty file and *guess* what the power usage would be, but for meaningful real-world numbers you would need to give opensta a VCD or something that contains a realistic trace of what you're going to run.

Even so, it will probably barely tickle an ammeter, so don't worry too much.
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message-1455382694383980625

2025-12-30T02:11:14.044+00:00 — asic destroyer (@logic_destroyer)

Content

As a rough upper bound, can we assume a worst case where all transistors toggle every clock cycle?
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message-1455387521663107126

2025-12-30T02:30:24.957+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lofty - That was my assumption too, but @Tholin seem to indicate their GF180MCU chips got pretty warm to the touch.
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message-1455388076217204799

2025-12-30T02:32:37.173+00:00 — Tholin (@tholin)

Content

At 50MHz, the AS2650v2 gets hot enough to hurt
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message-1455388200066486312

2025-12-30T02:33:06.701+00:00 — Tholin (@tholin)

Content

I wouldn’t call it "warm" anymore, but firmly in the "hot" territory.
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message-1455388462315470972

2025-12-30T02:34:09.226+00:00 — Tholin (@tholin)

Content

I hope the COB parts will be able to dissipate heat through the PCB ground plane

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message-1455390926167085188

2025-12-30T02:43:56.654+00:00 — Tholin (@tholin)

Content

That’s why I cringe a bit when I see people just have CEN permanently selected on the SRAM macros because I’m pretty sure that that is why I have such incredible heat output.

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message-1455391902512709809

2025-12-30T02:47:49.433+00:00 — asic destroyer (@logic_destroyer)

Content

That could’ve been communicated beforehand, though.
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message-1455392482752987218

2025-12-30T02:50:07.773+00:00 — Tholin (@tholin)

Content

I still hope that half of that heat output was caravel
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message-1455392786311549019

2025-12-30T02:51:20.147+00:00 — asic destroyer (@logic_destroyer)

Content

Why do you think that?
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message-1455392915063836783

2025-12-30T02:51:50.844+00:00 — Tholin (@tholin)

Content

Because its a whole RISC-V SoC with a bunch of SRAM macros that are also just leaving CEN always active.

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message-1455393453063274589

2025-12-30T02:53:59.113+00:00 — asic destroyer (@logic_destroyer)

Content

How was it at 30 MHz? Do you also have data on the heat output, like how much power your design consumed?
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message-1455393617580527767

2025-12-30T02:54:38.337+00:00 — Tholin (@tholin)

Content

At 25MHz, its....fine

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message-1455393924679209054

2025-12-30T02:55:51.555+00:00 — asic destroyer (@logic_destroyer)

Content

Do you have data on how much power your board consumed?
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message-1455394456109842442

2025-12-30T02:57:58.258+00:00 — Tholin (@tholin)

Content

No
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message-1455394656459423785

2025-12-30T02:58:46.025+00:00 — asic destroyer (@logic_destroyer)

Content

I have to sleep now. Thanks for the information.
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message-1455394900810928344

2025-12-30T02:59:44.283+00:00 — Tholin (@tholin)

Content

I have no multimeter that doesn’t max out at 100mA
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message-1455543394251047025

2025-12-30T12:49:47.878+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

Reply/reference

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Content

It's the signals that toggle; if I remember correctly a typical value used for power estimation without a VCD files is using 20% toggle rate on all the signals in a circuit. 100% is really worst case.

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message-1455650310705119308

2025-12-30T19:54:38.747+00:00 — Essen (@essen__)

Reply/reference

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Content

Started a thread.
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message-1455978455333212291

2025-12-31T17:38:34.523+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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I don’t know that much about pcb design; for now I’ve got 2-3 months to work on the layout. 😉

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message-1455979020725260299

2025-12-31T17:40:49.323+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

Pro tip,
Order early, order often.
JLCPCB and others have this global standard shipping, and it's like $5 US
I would order what you have there, just so you can hold it and look at it.
Otherwise looks pretty good so far 👍

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message-1455981461306867794

2025-12-31T17:50:31.203+00:00 — asic destroyer (@logic_destroyer)

Content

I was thinking we could do the production with Aisler. Since they support open-source projects, it might be a bit cheaper. I’m in Germany as well, so it’d be convenient. Maybe @Tim 'mithro' Ansell , @Matt Venn , or @psychogenic  has a contact there and we can do our PCB order through them.
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message-1455985199593820240

2025-12-31T18:05:22.48+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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I have six 100 nF caps on the bottom side for decoupling.
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message-1455985448164921466

2025-12-31T18:06:21.744+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1455989574877581385

2025-12-31T18:22:45.629+00:00 — urish

Reply/reference

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IMHO send the draft version to both Aisler and JLC so you can compare

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message-1455990136738414763

2025-12-31T18:24:59.587+00:00 — asic destroyer (@logic_destroyer)

Content

I’d also like to have the board assembled.
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message-1456434118895341589

2026-01-01T23:49:13.182+00:00 — asic destroyer (@logic_destroyer)

Content

Live Free Or Die
        ASIC

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2026-01-01T23:54:24.818+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1458552497936404490

2026-01-07T20:06:54.103+00:00 — Andrew Wingate (@anfroholic)

Content

Hey @xianglin_pu,
Le'ts just continue the discussion here if that's alright with you.
Over the break or sometime, I camy up with this. Influenced in no small part to the work you have done.

If you'd like to take a stab at making another version I would be happy to see it.
These are some design rules https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view
Assume the die is 0.75mm thick. I have attached some drawings I sent a dicing house to get us some sample wafers diced for testing.

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message-1458553750712090918

2026-01-07T20:11:52.788+00:00 — Andrew Wingate (@anfroholic)

Content

I think the design constraints should be brought in a touch.
Basically I would like for the cob to fit in between headers that are spaced at 0.6" like we would have for a DIP type chip.
The carrier board would be 0.1" wider than what you see in these pictures.
Let me know if you have any questions, I'll try my best to answer.

Also, don't take the above picture as gospel, I only spent a few minutes playing around and just shared is all.
Thanks and good luck!

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message-1458554052274032681

2026-01-07T20:13:04.686+00:00 — Tholin (@tholin)

Content

Did my first attempts at making a COB footprint accidentally set the standard of using certain comment layers in KiCad for marking the pad locations and bond wires?
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message-1458554108809183232

2026-01-07T20:13:18.165+00:00 — Tholin (@tholin)

Content

I see everyone doing it now, and I’m curious.
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message-1458554563282862223

2026-01-07T20:15:06.52+00:00 — Andrew Wingate (@anfroholic)

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My design was a derivative of yours ;) It does a good job of conveying lots of information.
And @xianglin_pu's design was a derivative of mine I believe.

Was well thought out. Thank you

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message-1458554827561766956

2026-01-07T20:16:09.529+00:00 — Tholin (@tholin)

Content

Yeah, KiCad’s measurement tools let you quickly check if you are exceeding angle limits.

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message-1458555162032476466

2026-01-07T20:17:29.273+00:00 — Andrew Wingate (@anfroholic)

Content

Not only that, I feel like having a real drawing of the bonding scheme will pay dividends when we actually go to get quotes and wirebonding for real.
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message-1459315041634357248

2026-01-09T22:36:58.688+00:00 — asic destroyer (@logic_destroyer)

Content

I’ve wired everything up now. @GoranMahovlic  helped me a lot, especially with the SDRAM wiring and the connector. I don’t have much experience—this is my first real board—so I’m going to check the signals again and double-check the connector pinout. Then I’ll send it to a fab/assembly shop for soldering. I really wanted to finish this so I can continue with my next Linux SoC, StealthV.

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message-1459316578498777159

2026-01-09T22:43:05.105+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Awesome! That looks great!!

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message-1459316650645131569

2026-01-09T22:43:22.306+00:00 — asic destroyer (@logic_destroyer)

Content

Thank you @Andrew Wingate
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message-1459327342634860706

2026-01-09T23:25:51.475+00:00 — asic destroyer (@logic_destroyer)

Content

Looks like a few GND vias are missing, so there’s a bit of rework to do, but it’s 95% finished
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message-1459332148170588381

2026-01-09T23:44:57.204+00:00 — asic destroyer (@logic_destroyer)

Content

I can buy from that store ,  based in Berlin, DIP-8 oscillators there.

https://www.segor.de
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message-1459332862724800806

2026-01-09T23:47:47.567+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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If your board is on github, you can stick that link into this site and get a web view of the board.

Here is an example of a friend's board. https://kicanvas.org/?github=https%3A%2F%2Fgithub.com%2FCarlFK%2Fgeebee%2Ftree%2Fmain%2Fdell7212%2Fkicad%2Fbgpogo

If you post it, I'll take a look at it if you'd like.

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message-1459333316288188540

2026-01-09T23:49:35.705+00:00 — asic destroyer (@logic_destroyer)

Content

When it’s final, I’ll put it on GitHub.

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message-1459333318872010969

2026-01-09T23:49:36.321+00:00 — Andrew Wingate (@anfroholic)

Content

Also side note: KiCanvas was helped to make real by @Tim 'mithro' Ansell
Thanks Tim, I have used it  a number of times

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message-1459333889519652894

2026-01-09T23:51:52.374+00:00 — asic destroyer (@logic_destroyer)

Content

@Tim 'mithro' Ansell  is always full of surprises.

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message-1459336508325761024

2026-01-10T00:02:16.746+00:00 — asic destroyer (@logic_destroyer)

Content

@Andrew Wingate I sent you a zip file of the pcb

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message-1459597973083128061

2026-01-10T17:21:14.802+00:00 — asic destroyer (@logic_destroyer)

Content

Attachments

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message-1459598214314459258

2026-01-10T17:22:12.316+00:00 — asic destroyer (@logic_destroyer)

Content

@Andrew Wingate  I just sent you a new ZIP.
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message-1460003611797881075

2026-01-11T20:13:06.608+00:00 — xianglin_pu (@chasees18)

Reply/reference

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Thank you @Andrew Wingate for your information, it's helpful.😃
I am bit confused with "the cob to fit in between headers that are spaced at 0.6"", do you mean the clearance space between pads ? like I drawed below in yellow.
Also I see the design rule for wire bonding, I noticed that the min bonding angle must >45 degree, I am not sure would the ones that circled in white also work ? I really appreciate your feedback,
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message-1460115688826998785

2026-01-12T03:38:27.854+00:00 — xianglin_pu (@chasees18)

Content

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message-1464279399523291307

2026-01-23T15:23:33.842+00:00 — Tholin (@tholin)

Content

What is the status of the wire bonded breakout PCB layout? At some point, I need to fork it and derive a version of it that works with my custom pad ring, but I don’t know if I can do this yet.
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message-1464507141388767466

2026-01-24T06:28:31.734+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I am not sure I will be able to make any of the changes I had hoped for in time.
@asic destroyer has also started designs with the layout as outlined currently.
Unless @xianglin_pu or someone else puts something forward or says something very soon, I think we have what will be the first version
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message-1464540069951049863

2026-01-24T08:39:22.515+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

I hope you don’t change anything about the pinout.

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message-1465473067424813264

2026-01-26T22:26:46.447+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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@Andrew Wingate ❤️

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message-1470182885670649908

2026-02-08T22:21:54.621+00:00 — asic destroyer (@logic_destroyer)

Content

crazy

https://x.com/matthewvenn/status/2020521149713600550

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message-1472778375331446816

2026-02-16T02:15:27.578+00:00 — Architeuthis Flux (@arabidsquid)

Content

Hey, so I was making a bunch of add-on boards for the upcoming next version of [Barnacle Board](https://github.com/Architeuthis-Flux/Barnacle_Board) and figured I'd make one that maps your 70 pin mezzanine connector to a breadboard.
Before I finish routing (and adding labels for the COB pads), I figured I should ask y'all some stuff:
- Do you even want this?
- How likely is it that you want `VDD_CORE`, `VDD_IO`, and `PWR_AUX` separate?
- What do you generally do with `PWR_AUX`?
- Is there anything you can think of that would make this more awesome?

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message-1472779448049991884

2026-02-16T02:19:43.334+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

Awesome!!

> Do you even want this?
Not sure, but it looks super cool!!

> How likely is it that you want VDD_CORE, VDD_IO, and PWR_AUX separate?
This was a spec pulled from Tiny Tapeout. Currently they have them all bridged on the die, but that may change in the future. Use your own judgement here.

> What do you generally do with PWR_AUX?
Again, this is likely more power pins than a *regular* design would need. We needed a standard and they had the most robust needs and had the most documentation, so that's how we ended up here.

> Is there anything you can think of that would make this more awesome?
Artwork! 😉

Looks great though. Super cool, thanks for sharing!

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message-1472780275984367709

2026-02-16T02:23:00.729+00:00 — Architeuthis Flux (@arabidsquid)

Content

What do you mean, I do have artwork on there. jk I'll definitely add some

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message-1472780472210821231

2026-02-16T02:23:47.513+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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The whole board is a piece of art. It looks great!

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message-1472780627148411073

2026-02-16T02:24:24.453+00:00 — Architeuthis Flux (@arabidsquid)

Reply/reference

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Thanks for that, so I can treat all those power pins as a single node?
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message-1472781671852933322

2026-02-16T02:28:33.53+00:00 — Andrew Wingate (@anfroholic)

Content

We're still working to harden the standard.
This will likely come sometime after the first run is complete.
I designed a couple tests.
https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2Fscratch%2Fmotherboards%2Fmotherboards

https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/scratch/motherboards/motherboards
It looks like I did **Not** bridge them.

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message-1472781883812347915

2026-02-16T02:29:24.065+00:00 — Andrew Wingate (@anfroholic)

Content

Really I have no idea what others have done.
Getting a concensus on what people actually *did* would be good
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message-1472782097025601659

2026-02-16T02:30:14.899+00:00 — Andrew Wingate (@anfroholic)

Content

And when I say I did not bridge them, I mean VDD_IO <==> VDD_CORE
The ones on the same nets are bridged

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message-1472782820178137172

2026-02-16T02:33:07.312+00:00 — Architeuthis Flux (@arabidsquid)

Reply/reference

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Legit. That's good news because it can fit on a half size breadboard that way.

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message-1472783554826993694

2026-02-16T02:36:02.466+00:00 — Architeuthis Flux (@arabidsquid)

Content

And eventually you'll be able to plug these into a [Jumperless](https://jumperless.org/) crossbar matrix for some automated testing or whatever

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message-1472783790911918090

2026-02-16T02:36:58.753+00:00 — Andrew Wingate (@anfroholic)

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Sweet! I recongnized one of those from your pic above

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message-1472967751411699864

2026-02-16T14:47:58.354+00:00 — Tholin (@tholin)

Content

Hmmmm...

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message-1472968088944250900

2026-02-16T14:49:18.828+00:00 — Andrew Wingate (@anfroholic)

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Awesome!
Are the dipswitches for project selection on your multiproject die?
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message-1472968359976108203

2026-02-16T14:50:23.447+00:00 — Tholin (@tholin)

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Yes

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message-1472987688809271446

2026-02-16T16:07:11.8+00:00 — Tholin (@tholin)

Content

And mezzanine version, which I’d actually prefer

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message-1473016039683129566

2026-02-16T17:59:51.175+00:00 — Architeuthis Flux (@arabidsquid)

Reply/reference

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Oh sick, which pads did you use for project selection? and is there any consensus on that? (I'm guessing no)
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2026-02-16T18:26:15.836+00:00 — Tholin (@tholin)

Content

No, no consensus
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message-1473439528567050411

2026-02-17T22:02:38.793+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Architeuthis Flux - So you going to give creating a custom replacement for your analog muxes a go on the next wafer.space run?
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message-1473439737686659278

2026-02-17T22:03:28.651+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Architeuthis Flux - It might be worth chatting with @peterkinget and the MOSBius team, they kind of already doing something in the same type of category.
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message-1473440632164061266

2026-02-17T22:07:01.911+00:00 — Architeuthis Flux (@arabidsquid)

Reply/reference

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Yeah, I'm definitely toying with that idea.
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2026-02-17T22:09:19.871+00:00 — Architeuthis Flux (@arabidsquid)

Reply/reference

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Yeah I watched that stream you did a few months ago, super rad. I've been meaning to hit you up @peterkinget and chat.
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message-1477049643476058294

2026-02-27T21:07:57.26+00:00 — Egor Lukyanchenko (@egorxe)

Content

@Andrew Wingate Which glue is planned to be used to glue the die to the cob, the conductive or non-conductive type? I guess it's conductive so the die bulk will be grounded, right?
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message-1477055297062178979

2026-02-27T21:30:25.18+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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This is something that's a little outside my expertise.
Part of me says there seems to be little reason why we would have anything other than conductive, so would imagine that would be what we ask for.
I also imagine we can have whatever we ask for.

Is there anyone out there who feels strongly either way?
@Tim 'mithro' Ansell
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message-1477059517425651782

2026-02-27T21:47:11.393+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@stuart - what has Tiny Tapeout been using?
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message-1477060904825917592

2026-02-27T21:52:42.175+00:00 — tnt (@246tnt)

Content

We use conductive epoxy.

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message-1478138002957013012

2026-03-02T21:12:42.381+00:00 — peterkinget

Reply/reference

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Hi, feel free to suggest some times for a zoom meeting. I am on Pacific time right now. I do not check Discord often enough ... so feel free to send me an email as well peter.kinget@columbia.edu.

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message-1479931971877601452

2026-03-07T20:01:17.902+00:00 — peterkinget

Content

@Tim 'mithro' Ansell @Andrew Wingate We have finished the COB design for the MOSbius chip on the first wafer space run. Where do we take it from here? [BTW, Tim, also sent you an email, we can continue the discussion there also.]
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message-1481591065827086429

2026-03-12T09:53:56.724+00:00 — Andrew Wingate (@anfroholic)

Content

Hey guys,
We're narrowing down on what a panel should look like

I have committed some files and we will see what the PCB house and the wirebonders have to say, but wanted to keep you all informed.

The boards are 77mm/side which should be good enough for JLCPCB to be ok, and still fit within wirebonders jig
This file can be found here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/blob/main/74pad-70pin-mezzanine/panel-74pad-70pin-mezzanine/production/panel-74pad-70pin-mezzanine.zip
Panel files here: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/74pad-70pin-mezzanine/panel-74pad-70pin-mezzanine
online viewer here: https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fwafer-space%2Fchip-on-board-wire-bonded-pcbs%2Ftree%2Fmain%2F74pad-70pin-mezzanine%2Fpanel-74pad-70pin-mezzanine

@Tholin @peterkinget @Meinhard Kissich @xianglin_pu
Afaik, you are the only ones wanting custom COB.
Let me know if you need any assistance.

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message-1481591353535103098

2026-03-12T09:55:05.319+00:00 — Tholin (@tholin)

Content

And I just need to change the routing, so there should be no complications.

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message-1481591577167265864

2026-03-12T09:55:58.637+00:00 — Tholin (@tholin)

Content

Actually, I think I already have mine pushed to github
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message-1481591588768452650

2026-03-12T09:56:01.403+00:00 — Tholin (@tholin)

Content

https://github.com/AvalonSemiconductors/gf180mcu_cob/tree/main/74pad-mp-mezzanine
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message-1481595109287006218

2026-03-12T10:10:00.76+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Replying to your comment from https://discord.com/channels/1361349522684510449/1361349523724570941/1481581473235468289

It looks like you don't have the same components or placement. I *think* this is alright, but just want you do be aware.
Default uses qty(8) 0201 components

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message-1481595457229815838

2026-03-12T10:11:23.716+00:00 — Tholin (@tholin)

Content

Oh, the capacitors?

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message-1481595505065721876

2026-03-12T10:11:35.121+00:00 — tnt (@246tnt)

Content

@Andrew Wingate BTW, you can use `Top/Bottom/Connected layers" for the settings of vias in KiCAD, that avoid rings on non-connected internal layers and reduces cuts in the internal planes and JLC processes that with no problems.
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message-1481595523994747051

2026-03-12T10:11:39.634+00:00 — Tholin (@tholin)

Content

I can fix that. Are the mezzanine and COB footprint in the right places?
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message-1481595912018067508

2026-03-12T10:13:12.146+00:00 — Andrew Wingate (@anfroholic)

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I don't want to say yes without verifying, but I believe it should be centered.
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message-1481596134848991352

2026-03-12T10:14:05.273+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Thanks. I guess I don't know what that means though?
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message-1481596491284877313

2026-03-12T10:15:30.254+00:00 — tnt (@246tnt)

Content

The annular ring settings.

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message-1481596875877519360

2026-03-12T10:17:01.948+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I'll look into that. Thank you
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message-1481877891242397736

2026-03-13T04:53:41.232+00:00 — beardothaweirdo (@wspitts2)

Content

Btw, I am open to collaborating for wafers/die (preferably wafers). I have access to some pretty nice equipment: https://docs.google.com/document/d/1n0aPQOVQ90qUniRZclDV7zVC_QPGmtOmgF9b8g0f-MM/edit?usp=sharing

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message-1482479642458984715

2026-03-14T20:44:49.902+00:00 — urish

Reply/reference

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Started a thread.
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message-1482601180361261118

2026-03-15T04:47:46.796+00:00 — Andrew Wingate (@anfroholic)

Content

Hey all, just a little backstory on the COB.

The wirebonder machine has a vacuum chuck and it's able to take a board no larger than 70mm/side.
They will be populating the boards with the mezzanine connector and the passives before the die is wire-bonded.
They also will be creating a custom chuck that can fit the mezzanine connector and have room for the passives area we defined before.

Someone can correct me if I'm wrong, but I think we're going to have them all glob-topped with clear. Speak up if this is concerning to you.

Long story short, thank you all who spoke up early about how they thought things would go, because for the most part it seems to be going about how we thought it would.

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message-1482725561871630366

2026-03-15T13:02:01.659+00:00 — Lofty (@ravenslofty)

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Content

(actually I think clear is a beautiful aesthetic)
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message-1482726000889434284

2026-03-15T13:03:46.329+00:00 — Andrew Wingate (@anfroholic)

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Of course! Me too. This is only a problem if you're worried about interference from light.
I think they're going to look quite beautiful!
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message-1482733424291610636

2026-03-15T13:33:16.206+00:00 — tnt (@246tnt)

Content

On sky130 I didn't see a ton of interference from light unless in sensitive circuits. Things like SRAM and analog stuff might be more problematic.

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message-1483438648434229249

2026-03-17T12:15:34.744+00:00 — Meinhard Kissich (@meinhard)

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Content

I'm all good with the default CoB. Thus, my previous question to get the mating connector/routing right. Thanks for keeping us all in the loop 🙂

No issue with clear glob-top. Actually, I quite like seeing the die through it. Gives it a nice touch, that you usually don't have in commercial products.

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message-1483439038437396540

2026-03-17T12:17:07.728+00:00 — Andrew Wingate (@anfroholic)

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Sounds great! I was just trying to ping everyone i remembered who said anything about custom anything. Cheers
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message-1483670321696473130

2026-03-18T03:36:09.954+00:00 — xianglin_pu (@chasees18)

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Thanks for the information, We have modified our COB PCB based on the deafult design, and I would like to comfrim that due to different pin functions, if it's possible we could custimze our routing (re-route some wires) and passive components (re-location and delete some components)
Our design is uploaded here: https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/main/V3_COB_Original/V3_COB_Original
Any feedbacks will be appreciated

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message-1483711483987755142

2026-03-18T06:19:43.809+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Just got home from a long day and am very tired.
I think it looks alright at first glance, but you probably need to refill your pours, and the passives need to be on the same side as the mezzanine connector (back)

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message-1483711578154078410

2026-03-18T06:20:06.26+00:00 — Andrew Wingate (@anfroholic)

Content

https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2Fmosbiuschip%2FWaferSpace_COB_70pins%2Ftree%2Fmain%2FV3_COB_Original%2FV3_COB_Original
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message-1483738283971317800

2026-03-18T08:06:13.423+00:00 — tnt (@246tnt)

Content

The passive also need to be in the "designated" area to not interfere with the chuck mounting right ?

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message-1483806927304786113

2026-03-18T12:38:59.269+00:00 — Andrew Wingate (@anfroholic)

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That is also correct, but given how they already were and would likely stay, i omitted that part.

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message-1483821797253185590

2026-03-18T13:38:04.541+00:00 — RebelMike (@rebelmike)

Content

Has there been any thoughts about COB package for half and quarter size chips?  I don't see anything in the repo.  From my point of view it would be cool if the pinout was somewhat consistent between them (w.r.t. the input and bidir pin numbering in the default template) - if you are planning to package all of the variants, that is!
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message-1483834303489118248

2026-03-18T14:27:46.26+00:00 — xianglin_pu (@chasees18)

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Many thanks Andrew!👍
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message-1484223372433817730

2026-03-19T16:13:47.525+00:00 — xianglin_pu (@chasees18)

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@peterkinget please see the design here for the MOSbius COB design
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message-1484477679569993749

2026-03-20T09:04:19.071+00:00 — stuart (@saladchap)

Content

Passives are OK on the top as long as they're not too tall. If on the bottom then they should be in the 'designated' area since we will be making a jig with cut outs for that area to hold the PCBs flat in the machine for the bonding

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2026-03-20T09:04:56.663+00:00 — stuart (@saladchap)

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Content

'too tall' meaning 0201s/0402s and similar are fine, headers and pins are not
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message-1484479713928937613

2026-03-20T09:12:24.1+00:00 — tnt (@246tnt)

Content

@stuart I think here the "no passive on top" is to not pay for dual sided SMT 🙂

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2026-03-20T10:42:50.454+00:00 — stuart (@saladchap)

Content

makes sense
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message-1484576117498187797

2026-03-20T15:35:28.502+00:00 — peterkinget

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Hi @Andrew Wingate and @xianglin_pu (Xianglin Pu?) — I am a bit confused why we are not using Xianglin’s design with the rotated pads. That will help with the bonding yield. E.g. take a look at the attached picture. Ignore the chip and the wires, but look at how the landing pads on the package are arranged. Notice how they are formed and slightly rotated so they are aligned with the bonding wire. Xianglin’s design was doing the same, why are we coming back from that?

@Tim 'mithro' Ansell is there opportunity to try to COB designs for this run so we can gain experience with both alternatives?

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2026-03-20T15:39:01.707+00:00 — peterkinget

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Content

@Andrew Wingate et al., Can you do a couple with clear, but the large majority with dark epoxy. The source and drain junctions of MOS transistors will act as photodiodes and are light sensitive so if I have to pick between dark and clear, I would prefer dark. (That’s also what you see when you open up toys or so that used COB bonded chips.) Clear will be nicer for pictures, but that is secondary.
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message-1484607436764610681

2026-03-20T17:39:55.597+00:00 — xianglin_pu (@chasees18)

Content

For the reference, this was the COB PCB design we used to have for rotated pads

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message-1484620059044352121

2026-03-20T18:30:04.983+00:00 — peterkinget

Content

@Andrew Wingate @Tim 'mithro' Ansell @xianglin_pu this is a picture I received from a tiny tape out COB. their landing pads are also “rotated”.

What am I missing that we are going for a rectangular arrangement?

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message-1484621468405858496

2026-03-20T18:35:41.001+00:00 — tnt (@246tnt)

Content

This is how we'll have the WS chips bonded on this run : https://github.com/htfab/breakout-ttgf0p2-cob/blob/main/images/bonding.png
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2026-03-20T18:37:24.706+00:00 — Andrew Wingate (@anfroholic)

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Oh so TT isn't using the COB?
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message-1484623403725095053

2026-03-20T18:43:22.417+00:00 — tnt (@246tnt)

Content

No, the dies get directly mounted on a board compatible with our existing demo/test board.  I think at one point there was also the possibility we'd ship some COB "module" to users so they could integrate on their own project, but given this is a test run and there is no real "customer" for theses boards , and there is only 400 dies and not 1000, it was decided to not do that here.

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message-1484624247480516629

2026-03-20T18:46:43.584+00:00 — Andrew Wingate (@anfroholic)

Content

Hey @peterkinget
I think a lot of this can fall on me more or less running out of time.

In the beginning we didn't know a lot about the requirements from the wirebonders, but are working with them now.

As stated above, we're needing specialized tooling to hold our boards along with a number of other supplementary documents stating design requirements.
Creating and submitting all these with all the uncertainties we already have seems like a high bar for this run.

> is there opportunity to try to COB designs for this run so we can gain experience with both alternatives?
I would probably punt this to the second run as we will have a lot of the process down

> Can you do a couple with clear, but the large majority with dark epoxy.
I can try, but again, we have a large number of boards. I'm sure we can do them all dark, I am less confident on partials, but I can ask.
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message-1484686288417329182

2026-03-20T22:53:15.296+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@stuart is helping us work with the wire bonders

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message-1484686324719161564

2026-03-20T22:53:23.951+00:00 — peterkinget

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Thanks, @Andrew Wingate, no worries, understandable you are very busy. Question is how do we go forward since it sounds like TT is going with a different COB already. Should we make Xianglin’s with the rotated pads the standard template for the rest of the chips?

Whatever works is fine with me, as long as we get working chips. If the packaging house has signed of on your rectangular design, then that is fine too and we can go for the other design in future rounds.

I assume @Tim 'mithro' Ansell will provide some guidance on next steps.
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message-1484686568005304541

2026-03-20T22:54:21.955+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@peterkinget - I think the rotated pad version might be a good default for everyone but need to figure out what the bond house says

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2026-03-20T22:55:51.051+00:00 — peterkinget

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OK, keep us posted and let us know how to assist. @xianglin_pu can point to the design files on GitHub. Note that others might have to change the board depending on where their grounds and VDDs are. We double bond the VDD and have VSS in the four corners, but I do not recall if that is a standard for the run or up to every design.
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message-1484687357457465456

2026-03-20T22:57:30.175+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I believe the one critical thing is the PCB size and location of the components because that effects the chuck that holds everything. I'm unsure how the pads on the PCB effect things.

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message-1484687650530005012

2026-03-20T22:58:40.049+00:00 — xianglin_pu (@chasees18)

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Please see the attatched linke for the rotated pad COB PCB
https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/main/V3_COB

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message-1484706431847501836

2026-03-21T00:13:17.864+00:00 — xianglin_pu (@chasees18)

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Indeed, the size is critical, and for our current rotated-pad PCB design, the PCB size is **17mm x 18mm** since all rotated pads need to be located without clearance issues.
I am not sure if that is possible fitting in the chunk or not. What would be the maximum size that the chunk can tolerate ?
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message-1486003912573194250

2026-03-24T14:09:01.375+00:00 — Leo Moser (mole99) (@mole99)

Content

Hi @Andrew Wingate,
@stuart mentioned that he would need wire bonding diagrams for each project to reduce the chance of bonding a chip the wrong way around, for example. Since some of the chips have distinctive features, I could provide you with a rendering of the top metal layer for each project, which you could then combine with a screenshot of the PCB and add the bond wire connections.

Would it be fine if I provide you the images with their ID as names, so that you can automate the bonding diagram creation?
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message-1486066436345696367

2026-03-24T18:17:28.204+00:00 — Andrew Wingate (@anfroholic)

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I already have the wirebonding detail added to the repo.
https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs?tab=readme-ov-file#wirebonding-detail
All chips have the QR code as pin0 marking yes?

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message-1486067172617748590

2026-03-24T18:20:23.745+00:00 — tnt (@246tnt)

Content

@Andrew Wingate Need that diagram for each die picture so the tech can recognize the orientation with what the die physically looks like.
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message-1486067984832270428

2026-03-24T18:23:37.392+00:00 — Andrew Wingate (@anfroholic)

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We have the QR code as pad 0 marker.
The reels will be coming fully marked
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message-1486421126069354527

2026-03-25T17:46:52.824+00:00 — stuart (@saladchap)

Content

Also we will need them for the non-full-size die too
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message-1486569727332450477

2026-03-26T03:37:22.126+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@stuart - I have been assuming that the non-full size die would be a "figure out when the first full size die are currently running successfully".
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message-1486618381443534858

2026-03-26T06:50:42.17+00:00 — stuart (@saladchap)

Content

Ok cool, makes sense. @Leo Moser (mole99) had offered to help with the bonding diagrams with some scripting so I thought it would make sense for him to do all of them at the same time
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message-1486711981414289435

2026-03-26T13:02:38.142+00:00 — Leo Moser (mole99) (@mole99)

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Started a thread.
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message-1486755656957690138

2026-03-26T15:56:11.203+00:00 — asic destroyer (@logic_destroyer)

Content

Hello everyone,

could you briefly explain what the issue is here? I am not that deep into the technical details and would like to understand it better.
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message-1486881480662712340

2026-03-27T00:16:09.912+00:00 — asc (@asc9742)

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@Andrew Wingate excuse my ignorance, but I noticed that in the bonding diagram, the lines are connected between the black squares and not the "actual pads". Is that just for cosmetic reasons or is there a separate step to bond the black squares to the actual pads?

Also, just to be clear based on the image, the QR code should be on the northeast corner of the COB (corner with the wafer.space logo)? We had assumed that the on-chip wafer.space logo location would correlate to the same corner wafer.space logo location on the COB.

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message-1486881938093379664

2026-03-27T00:17:58.972+00:00 — Andrew Wingate (@anfroholic)

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At the end of the day these pictures and diagrams are used to display intent to a human who programs the machine. At no point are any of these actually used directly for anything.

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message-1486882462041772032

2026-03-27T00:20:03.891+00:00 — Andrew Wingate (@anfroholic)

Content

Also way at the beginning when we were talking about defining different projects, we ended up with the qr code as the fiducial and information carrier. The logo was added after afaiu and there was some inadvertant overlap as I used the waferspace logo as a large fiducial without knowing there was another conflicting mark on the dies themselves
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message-1486883156337492168

2026-03-27T00:22:49.424+00:00 — asc (@asc9742)

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Ok no worries. Is it reasonable to have the mosbius chip bonded with the QR code on the southwest corner or would it be better to fix the COB to match with the standard bonding orientation?
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message-1486883413934997640

2026-03-27T00:23:50.84+00:00 — Andrew Wingate (@anfroholic)

Content

If they used the same pad template they are all the same.
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message-1486883639030448259

2026-03-27T00:24:44.507+00:00 — asc (@asc9742)

Content

We have the same pad template but different pads for ground and vdd
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message-1486884272597106780

2026-03-27T00:27:15.561+00:00 — asc (@asc9742)

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The same 17x20 pads but for example, our vdds are at pads 29 and 30. So im afraid that wrong orientation would tie two unique analog pads together if flipped.
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message-1486884704908087449

2026-03-27T00:28:58.632+00:00 — Andrew Wingate (@anfroholic)

Content

The pins and pads should all be correct the way that it is. If you want it in the sw corner just flip the whole thing 180deg.
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message-1486885015538368615

2026-03-27T00:30:12.692+00:00 — Andrew Wingate (@anfroholic)

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Also you guys are designing your own COB chip yes? Just make your changes there
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message-1486885474902610001

2026-03-27T00:32:02.213+00:00 — asc (@asc9742)

Content

Sorry, to be more clear, im asking if the QR code absolutely needs to be in the ne corner for bonding? In that case, we will alter our COB (like you said, just rotate 180). If we can bond the die with the QR code in the sw corner, which we had assumed when creating our COB, we don't need to alter our current COB.
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message-1486885752909463725

2026-03-27T00:33:08.495+00:00 — Andrew Wingate (@anfroholic)

Content

I see, for the sake of continuity and the fact there is a human in the loop. I would **strongly suggest** that you adhere as closely to the others as possible
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message-1486885861940396182

2026-03-27T00:33:34.49+00:00 — asc (@asc9742)

Content

Got it, no worries. We will alter our design. Thank you
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message-1486886047412391986

2026-03-27T00:34:18.71+00:00 — Andrew Wingate (@anfroholic)

Content

If you all have the mosbius logo as your pin1 marker, that's fine. Just make it upside down so it's in the corner however you like once it's put on your motherboard

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message-1488215214791852042

2026-03-30T16:35:56.908+00:00 — xianglin_pu (@chasees18)

Content

Hi @Andrew Wingate and @Tim 'mithro' Ansell, We have finished design of our own COB (the QR code on chip should now be at NE corner), and generated Gerber & Drill Files (in 'Gerber_Drill_Files' folder), everything is uploaded to GitHub Repo (https://github.com/mosbiuschip/WaferSpace_COB_70pins/tree/xp/V3_COB_Original/V3_COB_Original).
Any feedback or comments to the design are appreciated.

I would also like to double check that I can direcly submit the design in this discord channel or are there other places where I can submit/upload the files ? Thanks for the support.
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message-1488371559772061837

2026-03-31T02:57:12.456+00:00 — JohnPhillippe (@johnphillippe_72277)

Reply/reference

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[Evergreen Semiconductor Materials](https://evergreensemiconductor.com/) and [Spectrum Semi](https://www.spectrum-semi.com/) both sell ceramic package cavities.  One of the challenges is getting lids but if you don't care about hermetic sealing you can have flat lids cnc'd and then you can glue them down if it's a low volume prototype situation.

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message-1488415644226556056

2026-03-31T05:52:23.009+00:00 — Brian Swetland (@dnaltews)

Content

those PGA packages make me nostalgic but I bet they're not cheap
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message-1492424810742026341

2026-04-11T07:23:22.793+00:00 — stuart (@saladchap)

Reply/reference

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Started a thread.
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message-1493301673668509696

2026-04-13T17:27:43.206+00:00 — Tholin (@tholin)

Content

Why is there a missing connection on the COB PCB layout?

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message-1493301695755714661

2026-04-13T17:27:48.472+00:00 — Tholin (@tholin)

Content

I just cloned the repo and its like this
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message-1493415103469584405

2026-04-14T00:58:26.978+00:00 — Tholin (@tholin)

Content

The proposed mating connector (LCSC C19089262) only has 6 in stock right now. Might need an alternative part number.
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message-1493456592316661770

2026-04-14T03:43:18.69+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Wow, good catch. I have no idea how that dissapeared.
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message-1493456671161188422

2026-04-14T03:43:37.488+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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We have the connectors.
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message-1493524317529702552

2026-04-14T08:12:25.639+00:00 — Tholin (@tholin)

Content

Sorry, I mean, the board side connector that the breakouts will plug into is the one with only 6 left in stock
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message-1493524505799426069

2026-04-14T08:13:10.526+00:00 — tnt (@246tnt)

Content

The mating connector is available in multiple stacking height variants and some have thousands in stock.
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message-1493529408563183706

2026-04-14T08:32:39.436+00:00 — stuart (@saladchap)

Content

afaict you can use any height mating connector too
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message-1493530196941213757

2026-04-14T08:35:47.4+00:00 — Andrew Wingate (@anfroholic)

Content

Correct, there are a number of different heights available. I just picked one when we began.
https://www.lcsc.com/datasheet/C19089262.pdf?spm=wm.sxq.inf.ggs&lcsc_vid=TllZV1RfQVVdBlQCTlBfVFIDTlZXUFNTQFJcBAZQFFUxVlNRQVBbUlJXRFZYXjsOAxUeFF5JWAYHEwwTFU8NCAlJAAAIAhZLBBEPBAFJFAkHF0kJGUwMCAUUE0wZDhYDWgMBCQADE0weBAYV
There are also a number of other manufacturers that make compatible connectors as well.

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message-1493627442818973888

2026-04-14T15:02:12.624+00:00 — Simi (@simi150500)

Content

Hi, is it planned to get some samples of these DIP breakout boards with the order of the CoB dies? Or can we buy them somewhere, or do we have to build them on our own? Thanks. 🙂

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message-1493628119847014552

2026-04-14T15:04:54.04+00:00 — Tholin (@tholin)

Content

I’m building my own
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message-1493628756374585514

2026-04-14T15:07:25.8+00:00 — Andrew Wingate (@anfroholic)

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I don't think there are any plans to offer them.
When i get home after this run, I intend to clean this up and create some more offers, but still will just be gerbers and you can order your own.

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message-1494881473336053821

2026-04-18T02:05:16.798+00:00 — Andrew Wingate (@anfroholic)

Content

@xianglin_pu and @peterkinget
I created the panelized version of your board.
A pull request has been made if you'd like to merge back into your repo.

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message-1494881525622112400

2026-04-18T02:05:29.264+00:00 — Andrew Wingate (@anfroholic)

Content

@Tholin you had a custom version as well?
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message-1494882161059168258

2026-04-18T02:08:00.764+00:00 — xianglin_pu (@chasees18)

Content

@Andrew Wingate Looks great ! Thanks for the help.

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message-1494930176859967488

2026-04-18T05:18:48.623+00:00 — peterkinget

Content

Thanks @Andrew Wingate looks gr8 !

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message-1495009061719113888

2026-04-18T10:32:16.239+00:00 — Tholin (@tholin)

Reply/reference

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Yes.
https://github.com/AvalonSemiconductors/gf180mcu_cob/tree/main/74pad-mp-mezzanine

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message-1495009240908038184

2026-04-18T10:32:58.961+00:00 — Tholin (@tholin)

Content

Its the same as the default breakout, just the routing is different
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message-1495009796066381884

2026-04-18T10:35:11.321+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Thanks, I'll get to it later tonight.

I see the caps are also different. This should not be a problem either, I'll let you know if that changes.

Thanks

https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2FAvalonSemiconductors%2Fgf180mcu_cob%2Ftree%2Fmain%2F74pad-mp-mezzanine
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message-1495357823314563143

2026-04-19T09:38:07.483+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Thank you @Tholin
I have created a pull request if you'd like to merge

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message-1495361334307459141

2026-04-19T09:52:04.569+00:00 — Andrew Wingate (@anfroholic)

Content

Do you have a preference on COB soldermask color?
@peterkinget @xianglin_pu @Tholin @stuart
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message-1495375069495562442

2026-04-19T10:46:39.293+00:00 — Tholin (@tholin)

Content

Nope
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message-1495429081079222426

2026-04-19T14:21:16.658+00:00 — peterkinget

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We have been using blue or black. Blue would be nice for this one.

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message-1495629055767085187

2026-04-20T03:35:54.339+00:00 — namibj

Content

Is this wirebonding with the COBs chaper, was a socketed chip desired, did GF ask for things that can't (reasonably) be done like due to open PDK limitations, or how come that wafer.space is wire-bonded COB packaging instead of native flip chip WLCSP through 1 extra metal layer for some amount of redistribution plus the bumping process itself, and resulting in just bare WLCSP BGA dies?
Even the half slot at least at default IO count maths to "just" 0.4mm pitch, tho I do see that 122 IO count would be rather ambitious at probably about 0.25mm pitch.

Like there has to be a reason... is it just that such WLCSP devices would be "too much" for many customers to handle/solder?

Like e.g. epc-co with few exceptions (only one that comes to mind is one they have a drop-in different strength version of and use optically inspectable QFN pads) sells their GaN-on-Si (almost exclusively low-voltage, and most are "switch"-class but they do have some with S-parameters specified) transistors only as WLCSP BGA (well, some technically LGA due to bar-shaped pads). They claim something about cost/price for reasoning.
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message-1495666667202543646

2026-04-20T06:05:21.604+00:00 — tnt (@246tnt)

Content

It's cheaper
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message-1495681237313126600

2026-04-20T07:03:15.389+00:00 — Tim 'mithro' Ansell (@mithro_)

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As WLCSP requires more masks, it also then requires all the chips to have identical pad rings, sizes, fixed functions, etc.

Other type of packaging still uses wire bonding internally, so just drives the cost up.
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message-1495753709559218186

2026-04-20T11:51:14.119+00:00 — namibj

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Ehhhhh why would it force "all the chips" to have identical pad rings beyond the extend this currently already applies (per reticle)?
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message-1495753915696677055

2026-04-20T11:52:03.266+00:00 — namibj

Content

(isn't that cob option currently also mandating a specific pad ring layout to be selectable?)
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message-1495754003126947943

2026-04-20T11:52:24.111+00:00 — tnt (@246tnt)

Content

@namibj Only for COB option.  But if you process for WLCSP it applies to everyone ... same wafer.
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message-1495754287920185404

2026-04-20T11:53:32.011+00:00 — namibj

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I understand the words you say, but I don't comprehend why the WLCSP layers would have smaller reticles?
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message-1495754614279114794

2026-04-20T11:54:49.821+00:00 — namibj

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(and iirc the actual bumping part of it is selective so you could just skip bumping a slice's pads if that slice is supposed to get some custom wirebonding)
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message-1495754806717976747

2026-04-20T11:55:35.702+00:00 — tnt (@246tnt)

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The way I read the rules, either the whole wafer will be prepped for bumping and bumped  or will be prepped for bonding, they're exclusive options.  I think it's not just additional steps, some of the final steps diverge between options.  That's my understanding at least.
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message-1495754969159307325

2026-04-20T11:56:14.431+00:00 — namibj

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(I would easily understand the factory not letting you mix pinouts if they separate the wafers, but why would they care if the customer uses their own die sorter to pick and sort?)
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message-1495755908440129558

2026-04-20T11:59:58.373+00:00 — namibj

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https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4_5.html probe pads are at least allowed:
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message-1495757409354776576

2026-04-20T12:05:56.219+00:00 — namibj

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(notably I'm comparing the packaging budget of IIUC 1.5$/each to the total unit cost of 4$/each at the small slice size, and I don't think bumping would be that expensive relative to the FEOL+main-BEOL processing)
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message-1495757574241255484

2026-04-20T12:06:35.531+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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@namibj - WCSP adds about ~$30k NRE to every run *before* you do anything.
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message-1495757673046609951

2026-04-20T12:06:59.088+00:00 — namibj

Reply/reference

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Oh and no F[C]BGA doesn't use wire bonding internally.
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message-1495757854324556019

2026-04-20T12:07:42.308+00:00 — namibj

Reply/reference

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Ohh...
A case of "that part of the industry hasn't learned how to scale down yet"?
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message-1495758208269029427

2026-04-20T12:09:06.695+00:00 — Tim 'mithro' Ansell (@mithro_)

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FYI - No part of the industry has scaled down here. I've scaled up the number of people doing things. The costs are all the same, we just divide it by a larger number of people.
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message-1495759688057356339

2026-04-20T12:14:59.504+00:00 — namibj

Reply/reference

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Ehhhhh, not relying on Cadence NDA gated PDKs by offering self-service "don't talk to us about it" open source PDKs that suffice for creating submission-grade gds is already a major aspect.

You AFAIK are approximately the first one to offer series-production-quantities of dies through an MPW process with listed pricing instead of "call for NDA" schemes.

The other MPWs with listed prices seem to all be research quantities ("30 dies" "option for up to 200 dies").
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message-1495760832003440730

2026-04-20T12:19:32.242+00:00 — Tim 'mithro' Ansell (@mithro_)

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But that is just because the other MPW services throw lots of away stuff and loose money because they can't get enough people to order stuff.
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message-1495761165194629260

2026-04-20T12:20:51.681+00:00 — namibj

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The "30 dies" ones, or the "call for NDA before we talk pricing" ones?
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message-1495761369968934964

2026-04-20T12:21:40.503+00:00 — Tim 'mithro' Ansell (@mithro_)

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All of the above, the foundry itself generally runs things in half lot or full lot which is 12 or 25 wafers.
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message-1495761515599368373

2026-04-20T12:22:15.224+00:00 — namibj

Content

Wafer.Space is how many wafers?
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message-1495761698425016410

2026-04-20T12:22:58.813+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

1,000 dies require ~50 wafers in total
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message-1495761865949843506

2026-04-20T12:23:38.754+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

For this first run I only did 25 wafers, but it only saved about 15% of the cost
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message-1495762196519452875

2026-04-20T12:24:57.568+00:00 — namibj

Content

(also how many wafers do the full-reticle masks last? Not "effectively infinity" for say a mainstream STM32 die, but maybe close enough to the unlimited to not matter for MPW?)
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message-1495762597788651742

2026-04-20T12:26:33.238+00:00 — namibj

Reply/reference

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I'd guess it's "very many" for these larger nodes at least?
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message-1495763318210564246

2026-04-20T12:29:25+00:00 — namibj

Reply/reference

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Can you share anything about how they manage to make it that expensive? They're not fine-pitch masks, and not many masks either.
No notable automation causing lots of engineer time?
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message-1495769474983530526

2026-04-20T12:53:52.889+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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@namibj - effectively infinity but we use them once.
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message-1496019694228865024

2026-04-21T05:28:09.806+00:00 — RebelMike (@rebelmike)

Content

Just bumping this: https://discord.com/channels/1361349522684510449/1408134567491145728/1483821797253185590
Has there been any more thought as to how half slots will be bonded? It would be nice to work out the pinout so I could start designing a carrier board.
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message-1496038781382299778

2026-04-21T06:44:00.538+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike - any thoughts on if we can reuse the existing PCBs with longer bond wires?
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message-1496040568671703070

2026-04-21T06:51:06.661+00:00 — RebelMike (@rebelmike)

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That’s definitely beyond my knowledge, but I would be worried about the distribution of pins being skewed to the long sides of the half slots meaning some of the wires would be at a difficult angle.
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message-1496722240086085654

2026-04-23T03:59:49.791+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

FYI - We are getting an ~80% success rate of dies being chip on board mounted with all wire bonds working based on the Tiny Tapeout testing. So we have pulled the trigger to get the first 20 parts of the 1x1 designs bonded to get people stuff.

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message-1496972642266120303

2026-04-23T20:34:50.323+00:00 — Tholin (@tholin)

Content

Is the mezzanine connector keyed or will I have to *extremely careful* about orientation?
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message-1496975587854516345

2026-04-23T20:46:32.606+00:00 — tnt (@246tnt)

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It's not keyed AFAIK

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message-1497064527152414721

2026-04-24T02:39:57.387+00:00 — Andrew Wingate (@anfroholic)

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Correct. It is not keyed
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message-1497418906611220681

2026-04-25T02:08:08.034+00:00 — stuart (@saladchap)

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The COB factory confirmed the length isn't an issue for them, but yes the angles may be. Afaik @Tim 'mithro' Ansell  will be checking this and preparing bonding diagrams (maybe with @Leo Moser (mole99) ?) over the next few days
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message-1497517923588378684

2026-04-25T08:41:35.521+00:00 — RebelMike (@rebelmike)

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Awesome, thanks for letting me know! If new boards are required I could potentially have a go at that next week, if that would be helpful.
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2026-04-25T09:23:42.092+00:00 — Tim 'mithro' Ansell (@mithro_)

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@RebelMike - IIRC you have the quarter slot one? (Plus some half slots?)

It would probably be helpful to look at that one at least.

I think your ICs are interesting enough that I would love to see a custom board?

Being able to give out a fully open source RISC-V blinky would be pretty cool....
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message-1497542257115660329

2026-04-25T10:18:17.086+00:00 — RebelMike (@rebelmike)

Content

Yes I have one each of the two half slots and a quarter, they’re all the same design but Leo encouraged me to submit them all to help test everything.

Do you mean a custom board the chip is directly bonded to? I’d be very happy to do that if it can be made to work - I know there are max size considerations. But yes I was already planning to make a carrier board, but haven’t started on that yet as I’m not sure what the pinout will end up being.
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2026-04-25T14:44:15.866+00:00 — Tim 'mithro' Ansell (@mithro_)

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I was more thinking a custom cob board that made them all have the same pin out so could share a carrier board or something.

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2026-04-25T17:30:20.882+00:00 — RebelMike (@rebelmike)

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Yes if it’s possible to make a cob board that can match the pinout at least for the digital pins used for TinyQV (and in general as many as possible in the default template) that would definitely seem like a good move.
Haven’t looked into how feasible that is yet, today ended up busier than expected, but hopefully I’ll get some time tomorrow evening.
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2026-04-26T00:22:12.786+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike - Great! I'll probably be looking at that this week as well but there are quite a few projects and the 0.5x0.5 will likely be the lowest priority due to there only being one of that.

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2026-04-26T02:07:01.767+00:00 — BreakingTaps (@polyfractal)

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guess I should start thinking about PCB stuff now that the boards are shipping 😅   Has anyone designed just a simple breakout board for the COB connector?
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2026-04-26T02:12:33.458+00:00 — namibj

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https://discord.com/channels/1361349522684510449/1361349523724570938/1497771485966897273 look at the image with the green adapter board.

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2026-04-26T02:30:01.05+00:00 — Tim 'mithro' Ansell (@mithro_)

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https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs

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2026-04-26T02:31:03.448+00:00 — Tim 'mithro' Ansell (@mithro_)

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https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/chip-on-board

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2026-04-26T02:38:22.127+00:00 — BreakingTaps (@polyfractal)

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oh wow, totally missed that somehow. thanks @Tim 'mithro' Ansell!
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2026-04-26T05:39:37.274+00:00 — stuart (@saladchap)

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https://github.com/htfab/breakout-ttgf0p2-ws-adapter

Here's the repo for the green adaptor board in that photo. We used this so we could test the bonding process for w.s die by using the TT w.s die and the known test process we use for TT chips when making devkits.

Maybe not super useful for you but thought it might be helpful

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2026-04-26T09:12:22.044+00:00 — Andrew Wingate (@anfroholic)

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I designed a couple simple ones.
https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/74pad-70pin-mezzanine/motherboards
The large one was the only one that I made, since the castellated were a little more expensive.

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2026-04-26T09:13:58.742+00:00 — Andrew Wingate (@anfroholic)

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2026-04-26T15:34:58.202+00:00 — BreakingTaps (@polyfractal)

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ordered a small batch of these last night, thanks for making them!
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2026-04-26T15:36:19.251+00:00 — Andrew Wingate (@anfroholic)

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Of course. I am thinking now something I should have mentioned is I did not put the pinned headers all the way in as I got the shortest of the mating connector.
Sorry about that.
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message-1497984846759198863

2026-04-26T15:36:58.68+00:00 — BreakingTaps (@polyfractal)

Content

no worries, will bodge my way to making it work 🙂
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message-1497985179648659526

2026-04-26T15:38:18.047+00:00 — Andrew Wingate (@anfroholic)

Content

Perfect! Here's a more side view if that helps

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message-1497986325536833677

2026-04-26T15:42:51.248+00:00 — BreakingTaps (@polyfractal)

Content

aha I see, good to know. will keep that in mind when soldering it up 👍

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message-1497986356297732157

2026-04-26T15:42:58.582+00:00 — BreakingTaps (@polyfractal)

Content

so excited!
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2026-04-26T15:43:04.347+00:00 — BreakingTaps (@polyfractal)

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here's to hoping it's not DOA haha
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2026-04-26T15:43:27.446+00:00 — Andrew Wingate (@anfroholic)

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You got this!!
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message-1498081578994372832

2026-04-26T22:01:21.442+00:00 — RebelMike (@rebelmike)

Content

Started by trying to put a Kicad symbol together for the 1x0p5 and 0p5x1.  The 0p5x1 is rotated 90 degrees to align as best as possible:

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message-1498084207766012157

2026-04-26T22:11:48.19+00:00 — RebelMike (@rebelmike)

Content

clk on the bottom left is 1x0p5, clk on the top left is 0p5x1.  My TinyQV SoC uses clk, rst_n, in0-1 and bidir0-32.  Maybe it would be possible to produce a board that had two pads for the bond wires on the nets that are in significantly different places between the two?  I'm thinking I would ignore the analog pads completely but try to get something that would work for clk, rst_n, in0-3 and bidir0-43.
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message-1498368011856248872

2026-04-27T16:59:32.358+00:00 — Tim 'mithro' Ansell (@mithro_)

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I assume you got distracted by @tnt and the tt silicon stuff 🙂
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message-1498368484059512853

2026-04-27T17:01:24.94+00:00 — Tim 'mithro' Ansell (@mithro_)

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Well, there is no reason you can't route all the pads around the place so the connector has the pins in the same locations even if the pads/bonds are not.
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message-1498370946833055985

2026-04-27T17:11:12.111+00:00 — RebelMike (@rebelmike)

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Yes I'm afraid so.  Should get some more time for this later in the week!
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message-1498371107412115598

2026-04-27T17:11:50.396+00:00 — RebelMike (@rebelmike)

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I was hoping a single CoB might be able to work for both types of half slot, but maybe that isn't a good thing to try and do
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message-1498374724646993921

2026-04-27T17:26:12.812+00:00 — Tim 'mithro' Ansell (@mithro_)

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I think it is just easier to have 3 seperate PCBs which all end up with the same layout on the connector?

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message-1498786825609805945

2026-04-28T20:43:45.338+00:00 — RebelMike (@rebelmike)

Content

My first go at a footprint for the 1x0p5 chip:

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message-1498787265369866410

2026-04-28T20:45:30.185+00:00 — RebelMike (@rebelmike)

Content

The pads on the bottom and top are reduced to 0.2mm wide and 0.3mm spacing.  The rest are 0.25mm wide and at least 0.4mm spacing, as in the original 1x1 version
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message-1498787456936317048

2026-04-28T20:46:15.858+00:00 — RebelMike (@rebelmike)

Content

The mask box is the same as the original in https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/tree/main/scratch/footprints
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message-1498789400077664319

2026-04-28T20:53:59.139+00:00 — RebelMike (@rebelmike)

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Interested in feedback (especially from @Tim 'mithro' Ansell @Andrew Wingate @stuart @htamas).  I've pushed the footprint here: https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev/scratch/footprints
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message-1498789563609387169

2026-04-28T20:54:38.128+00:00 — RebelMike (@rebelmike)

Content

If that looks plausible I'll try and route the board matching up the pinout with the 1x1 slot as best as possible
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message-1498836952038768864

2026-04-29T00:02:56.41+00:00 — Tim 'mithro' Ansell (@mithro_)

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@RebelMike - It's important to keep the same footprint and placement of capacitors/connectors as the existing board - otherwise the CoB house has to make a new jig.
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message-1498929331349753916

2026-04-29T06:10:01.354+00:00 — RebelMike (@rebelmike)

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By the “same footprint” you mean board size?
I think we’d decided it wasn’t possible to use the same footprint for the die as the angles to the pads on the ends of the long rows get too shallow
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message-1498930280390459392

2026-04-29T06:13:47.623+00:00 — RebelMike (@rebelmike)

Content

Looking again at this it’s possible I was trying to be too clever with the 45 degree pads and actually the angles would be better with just a straight row of pads. Thoughts on that?
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message-1498931650313322566

2026-04-29T06:19:14.238+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike - I mean the PCB size

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message-1498931781460820019

2026-04-29T06:19:45.506+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

And the location of the capacitors and connectors on the PCB

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message-1498942336384892929

2026-04-29T07:01:41.996+00:00 — Andrew Wingate (@anfroholic)

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Sorry, been out for the afternoon.
Yes, basically the edge.cuts layer should stay the same, and then there was an area marked off "allocated for passives" or something like that.
Anything on the back should remain in the designated areas (ie. mezzanine/ passives)

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message-1498953282666762301

2026-04-29T07:45:11.793+00:00 — stuart (@saladchap)

Content

Yes, basically we have a jig made for the 'standard' WS BB PCBs - the most important thing is the location of the components (connectors) on the bottom side of the PCB
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message-1498953398911897621

2026-04-29T07:45:39.508+00:00 — stuart (@saladchap)

Content

for bonding the panels are split in half, 10pcs boards per panel
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message-1498953607297503334

2026-04-29T07:46:29.191+00:00 — Andrew Wingate (@anfroholic)

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@RebelMike Don't worry about panelization. I'll probably just take care of those for you as I did the others.
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message-1498953945249353758

2026-04-29T07:47:49.765+00:00 — RebelMike (@rebelmike)

Content

Great, thank you. I’ll try and get a first rev of the PCB done this evening.
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message-1498953996331647128

2026-04-29T07:48:01.944+00:00 — stuart (@saladchap)

Content

Is the plan to make these breakout (individual boardS) the same physical size of the normal ones?
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message-1498954052984115330

2026-04-29T07:48:15.451+00:00 — stuart (@saladchap)

Content

would make sense imo
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message-1498954063834910892

2026-04-29T07:48:18.038+00:00 — RebelMike (@rebelmike)

Content

Yes

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message-1498954290306486283

2026-04-29T07:49:12.033+00:00 — RebelMike (@rebelmike)

Content

Idea is to match the 1x1 version as closely as possible, including the pinout (if using the default setup from the template repo)
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message-1498954476130668616

2026-04-29T07:49:56.337+00:00 — RebelMike (@rebelmike)

Content

I’ll see how well that plan holds together once I actually see the rats nest though 😆

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message-1499064960880476402

2026-04-29T15:08:57.954+00:00 — stuart (@saladchap)

Content

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message-1499064990454386730

2026-04-29T15:09:05.005+00:00 — stuart (@saladchap)

Content

@Tholin ^^
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message-1499077753197035750

2026-04-29T15:59:47.88+00:00 — htamas (@h.tamas)

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Content

I think it's going to be ok. Here are my "strict-mode warnings" if you want to be extra careful:
- The pads in the kicad footprint are slightly off from the gds. This shouldn't matter directly as the cob house doesn't use the coordinates for alignment, but it makes the next item harder to check.
- The angles for pads 2, 23, 38 and 59 are slightly over the limit. The bond wires should have an angle of at least 45 degrees with the die edge (this is relaxed for pads 1, 24, 37 and 60 because they are the last pads on the particular die edge so there is no next pad to disturb)
- You have vias under the epoxy glob. I don't think this is a problem in practice, we had them on the "TT02" cob pcbs and the official wafer.space cob pcb also has them, and so far we didn't see any issues. But some guidelines say that the epoxy seeping through the vias can cause problems, so I moved them outside the epoxy area starting with our TT08 boards. This has the tradeoff that the ground paths are longer.
- You might want to add some marker lines to the footprint. It doesn't matter for this particular board because you have nothing else on the top side, but a silkscreen line for the area to be covered with epoxy can help the operator adding the globs, and a courtyard line a bit further out can prevent pcb designers using your footprint to accidentally add components too close to it.
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message-1499106727977685044

2026-04-29T17:54:56.006+00:00 — RebelMike (@rebelmike)

Reply/reference

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Thank you for the review!
- Yeah I just positioned the pads in roughly the right place to get an idea.  I'll leave as is
- I'll try and squeeze these up a little to avoid this.
- I assume this is working fine for the 1x1 wafer space breakout, so I'll leave as is
- I'm not actually sure what these limits are, so as this is intended just for the breakout at the moment, I will leave as is

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message-1499115028341723368

2026-04-29T18:27:54.967+00:00 — RebelMike (@rebelmike)

Content

Squeezed up a little and grounds connected
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message-1499115115998478587

2026-04-29T18:28:15.866+00:00 — namibj

Content

if the vias are tented there shouldn't be seepage
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message-1499115469448155196

2026-04-29T18:29:40.135+00:00 — RebelMike (@rebelmike)

Content

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message-1499250578159833100

2026-04-30T03:26:32.562+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@htamas - I think we have discovered that vias might be causing some of the air bubbling seen by some users.

Something we need to explore more - https://jlcpcb.com/help/article/pcb-via-covering

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message-1499324312442634271

2026-04-30T08:19:32.185+00:00 — RebelMike (@rebelmike)

Content

Realised I didn’t update before going to bed last night. Didn’t have so much time as I thought I would last night but I’ve routed the “easy” three quarters.

The rest the pin order doesn’t match the 1x1 so I need to decide how much to mess things around to make routing easy and how much to try and make work.
It would probably be good to be thinking about the 0p5x1 at the same time, but I’m going to have minimal time after tonight until 12th May so I’ll prioritise getting this one finished.
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message-1499326875657306113

2026-04-30T08:29:43.303+00:00 — Andrew Wingate (@anfroholic)

Content

> The pads in the kicad footprint are slightly off from the gds.
These files are not what we are sending the wirebonders anymore. They (and us) would like some more detail. I am attaching @BreakingTaps sample so you all can see.

> The angles for pads 2, 23, 38 and 59 are slightly over the limit. The bond wires should have an angle of at least 45 degrees with the die edge (this is relaxed for pads 1, 24, 37 and 60 because they are the last pads on the particular die edge so there is no next pad to disturb)
It seems this issue has been resolved in his update. I will look a little closer in a bit here.

> You have vias under the epoxy glob. I don't think this is a problem in practice, we had them on the "TT02" cob pcbs and the official wafer.space cob pcb also has them, and so far we didn't see any issues. But some guidelines say that the epoxy seeping through the vias can cause problems, so I moved them outside the epoxy area starting with our TT08 boards. This has the tradeoff that the ground paths are longer.
Holes in vias and whatnot do seem to be causing some problems. Not the ones under the dies themselves but the ones that are under the wire from the wirebonds. I wouldn't worry about it at the moment, but we need to explore this more deeply.

> You might want to add some marker lines to the footprint. [...] help the operator adding the globs, and a courtyard line [...] can prevent pcb designers using your footprint to accidentally add components too close to it.
None of the other boards had this. I will be heading to China in a few days and will personally get a better look at this.

Nice writeup @htamas Thank you

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message-1499330730436726805

2026-04-30T08:45:02.354+00:00 — Andrew Wingate (@anfroholic)

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Hey @RebelMike,
Just talked to Tim and got a little info on what we have going here with your COB.
As I understand it, you have one of all three 1xp5, p5x1, and p5xp5
The idea is there can be a carrier board that can accept all 3, while some may have reduced functionality.
@Tim 'mithro' Ansell  will be leaving China on may 10, so I don't know what anything means for designs after that date.

I don't have a lot of time either, but if you'd like to share some information with me I'd be happy to spend a bit of time that I do have.
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message-1499331570073473166

2026-04-30T08:48:22.539+00:00 — RebelMike (@rebelmike)

Content

I've just pushed my current state to https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev/
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message-1499332530694783007

2026-04-30T08:52:11.569+00:00 — RebelMike (@rebelmike)

Content

Yes, I have the same design on each of the three smaller sizes.  My goal is to try and make breakouts that match the template pinouts as well as possible, but with the ones TinyQV needs as a hard requirement.  I'm also trying to match the 1x1 template pinout for overall consistency.  Though I'm still not sure how possible this is given the size and sticking to 2 layers.
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message-1499332808458506412

2026-04-30T08:53:17.793+00:00 — Andrew Wingate (@anfroholic)

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I would be less concerned with matching the template as I would be with matching themselves.
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message-1499332907582488679

2026-04-30T08:53:41.426+00:00 — RebelMike (@rebelmike)

Content

But there's two copies of TinyQV in 1xp5 slots so even just having that one would allow plenty of boards to be made (and prove the design actually works).  I'm in no rush though so waiting until we have good designs for all breakouts would be fine - but I'm on holiday next week and spending all evening on Kicad would be unpopular 😆

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message-1499333021478686791

2026-04-30T08:54:08.581+00:00 — RebelMike (@rebelmike)

Content

Matching the template = matching each other - the TinyQV designs just use the default pinout from the template
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message-1499333160318664704

2026-04-30T08:54:41.683+00:00 — Andrew Wingate (@anfroholic)

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I see
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message-1499333317659459716

2026-04-30T08:55:19.196+00:00 — RebelMike (@rebelmike)

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Although it only uses the first 33 bidirs, clk, rst_n and two inputs, so the others I might mess with.
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message-1499333551584186431

2026-04-30T08:56:14.968+00:00 — Andrew Wingate (@anfroholic)

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Sounds good.
I have a little time at the moment, so let me know if there's a good place I could jump in
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message-1499334120751497359

2026-04-30T08:58:30.668+00:00 — RebelMike (@rebelmike)

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If you wanted to have a go at the footprint for p5x1 that would be great.  I'll quickly stick the symbol somewhere
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2026-04-30T09:00:28.126+00:00 — Andrew Wingate (@anfroholic)

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That sounds reasonable.
Sure!
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message-1499335112700199032

2026-04-30T09:02:27.167+00:00 — RebelMike (@rebelmike)

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Thanks!  See https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev/mezzanine-0p5x1
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message-1499335661159845918

2026-04-30T09:04:37.93+00:00 — RebelMike (@rebelmike)

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Incidentally I'm still on Kicad 9, so I started based on the last revision you had before going up to 10 - hopefully that didn't lose anything significant given I was just using the 1x1 as a template.  I should probably upgrade...
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message-1499335797206421524

2026-04-30T09:05:10.366+00:00 — Andrew Wingate (@anfroholic)

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it should, going back the other way could be a problem though after I save
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2026-04-30T09:07:00.504+00:00 — Andrew Wingate (@anfroholic)

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So this is the tall skinny one correct?
Also have I marked the correct location for pad 0 and there is an increasing number in the direction of the arrow?
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message-1499336296261357670

2026-04-30T09:07:09.35+00:00 — Andrew Wingate (@anfroholic)

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message-1499340130941665372

2026-04-30T09:22:23.609+00:00 — RebelMike (@rebelmike)

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Yes this is the tall skinny one.  Probably for consistency pad 0 would be top left (that is beginning of SOUTH in the librelane config), but the numbering matches the wide one with it rotated and pad 0 bottom left
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2026-04-30T09:25:37.656+00:00 — Andrew Wingate (@anfroholic)

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A man after my own hear lol.
Ok, I'll run with that.

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message-1499380775051591720

2026-04-30T12:03:53.92+00:00 — Andrew Wingate (@anfroholic)

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ok @RebelMike I have created a padring.
Didn't get a whole lot of time, but it's a start
https://github.com/anfroholic/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev-help
I have made a pull request if you'd like.
I may have a little more time later to look at it again.

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message-1499381296324022354

2026-04-30T12:05:58.201+00:00 — RebelMike (@rebelmike)

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That's great - thank you!  I'll take a look later

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message-1499421993882091550

2026-04-30T14:47:41.255+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

These are the three diagrams I generated for @Greg chips.

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message-1499422388213780603

2026-04-30T14:49:15.271+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

These are the three diagrams I generated for your die.

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message-1499422856356823251

2026-04-30T14:51:06.885+00:00 — RebelMike (@rebelmike)

Reply/reference

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Content

Thank you!  I'll double check they match what I've extracted from the librelane config
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message-1499422976720765122

2026-04-30T14:51:35.582+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

These are generated from the GDS file

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message-1499438115943743572

2026-04-30T15:51:45.054+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

BTW one of the theory about some of the bubbles in the CoB epoxy is this effect - https://docs.google.com/drawings/d/1_l0R9LjZSGAY5cvv7YkMGCiPKqeMAvKO5AYDg0XRl3w/edit

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message-1499438698687889630

2026-04-30T15:54:03.991+00:00 — Andrew Wingate (@anfroholic)

Content

A little more explanation is we get our boards plugged, which will just let the soldermask (this is the stuff that would make a board green; or in this case black) flow everywhere and into the holes plugging them.
This plugs them on the back side, but since there is no soldermask on this side, so no plugs.
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message-1499446953585672353

2026-04-30T16:26:52.112+00:00 — RebelMike (@rebelmike)

Content

Could you add soldermask between the inner edge of the ground ring and the inner edge of the pads?
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message-1499447101535555825

2026-04-30T16:27:27.386+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I made that suggestion as well.
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message-1499459787035906279

2026-04-30T17:17:51.845+00:00 — Brian Swetland (@dnaltews)

Content

that does seem like the most straightforward simple fix
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message-1499494687906594866

2026-04-30T19:36:32.861+00:00 — RebelMike (@rebelmike)

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I don't actually see the new padring in your branch - maybe forgot to add the file?
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message-1499495096154984618

2026-04-30T19:38:10.195+00:00 — RebelMike (@rebelmike)

Content

I seem to have successfully upgraded to Kicad 10 without destroying too much stuff though (had to switch from snap to ppa), so we should at least be making compatible files 😄
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message-1499535357203710036

2026-04-30T22:18:09.177+00:00 — RebelMike (@rebelmike)

Content

Finished routing the 1x0p5 version.  Pinout of power, clk, rst_n and bidirs matches 1x1.  I suspect matching the 0p5x1 will be rather tricky.  Quarter size should be easier as the pad frame will be smaller giving a bit more space for routing.

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message-1499536580032069785

2026-04-30T22:23:00.722+00:00 — RebelMike (@rebelmike)

Content

I had lots of fun with the ground connections to the ring/pad, so I stripped all the wires off the footprint, and changed the big ground pad to an actual pad instead of a drawing.
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message-1499536634373214318

2026-04-30T22:23:13.678+00:00 — namibj

Content

Would it help to rotate that one by 90 degrees?
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message-1499537385262944447

2026-04-30T22:26:12.704+00:00 — RebelMike (@rebelmike)

Content

Yes I think it might - good thought.  We'll be very short on space at the edges but hopefully the extra space top and bottom will make up for that.
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message-1499545677473120387

2026-04-30T22:59:09.721+00:00 — namibj

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Also, not sure how the bonding palce likes it, but if you need routing access, do consider rotating 45 degrees.
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message-1499590060738351296

2026-05-01T01:55:31.516+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Great work Mike!
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message-1499590164870205521

2026-05-01T01:55:56.343+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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From what I have seen so far, I don't think the bond house we are using will care at all.
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message-1499591097574228029

2026-05-01T01:59:38.717+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike / @Greg - It is very likely whatever we end up using on the TinyQV and/or Racquet die will become the standard CoB layout for the non-1x1 projects getting packaged.
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message-1499591445806321674

2026-05-01T02:01:01.742+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike / @Greg / @Leo Moser (mole99) - I'm also open to the alternative idea of changing the GF180MCU template I/O allocations for these sizes to make things easier.
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message-1499592673881751604

2026-05-01T02:05:54.538+00:00 — Brian Swetland (@dnaltews)

Content

a pin 1 marker on the silkscreen for the mezzanine connector might be nice just for completeness
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message-1499593034562535565

2026-05-01T02:07:20.531+00:00 — namibj

Reply/reference

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Might wrongly suggest polarization.
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message-1499596135495372820

2026-05-01T02:19:39.851+00:00 — BreakingTaps (@polyfractal)

Content

just got my motherboard breakout PCBs ... i severely underestimated how small the connector pins/pads would be 😅  probably should have bought a stencil to go with it, guess we'll see how good I am at fine soldering!

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message-1499598807279861830

2026-05-01T02:30:16.854+00:00 — Tim 'mithro' Ansell (@mithro_)

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Hot Air reflow and a good (pre-)heating plate helps a lot, surface tension is your friend.

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message-1499615540380041376

2026-05-01T03:36:46.336+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Sorry, it seems I didn't hit save before I hit commit.
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message-1499662461324759193

2026-05-01T06:43:13.161+00:00 — Greg (@greg.hashtag.9468)

Reply/reference

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Do you have the scripts which generated this? Would be nice to get an SVG if possible to put into the datasheet/spec for the chip
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message-1499663413226373190

2026-05-01T06:47:00.112+00:00 — Greg (@greg.hashtag.9468)

Reply/reference

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Was this checked in somewhere? I'm happy to take a look and poke around with the bonding for the 0p5x1
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message-1499663788964839485

2026-05-01T06:48:29.695+00:00 — RebelMike (@rebelmike)

Reply/reference

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It’s in https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev/mezzanine-0p5x1

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message-1499663953897328651

2026-05-01T06:49:09.018+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I am told these may be partially out of date, but here you go!

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message-1499664550046470316

2026-05-01T06:51:31.151+00:00 — RebelMike (@rebelmike)

Reply/reference

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Ah, no it isn't - apparently I was on Andrew's branch and committed and pushed it there.  I'll merge that
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2026-05-01T06:53:47.79+00:00 — Greg (@greg.hashtag.9468)

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Thanks 👍
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message-1499665243587084359

2026-05-01T06:54:16.504+00:00 — RebelMike (@rebelmike)

Content

I'll also make a PR against the main repo.  But possibly after I've had some coffee 🙂
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message-1499665815782293514

2026-05-01T06:56:32.926+00:00 — Greg (@greg.hashtag.9468)

Content

No worries, I'll only get to looking at this in depth in a few hours
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message-1499667249584410765

2026-05-01T07:02:14.771+00:00 — Tim 'mithro' Ansell (@mithro_)

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It is a super horrific AI written bit of code. Let me see if I can upload it somewhere.

At some point I think I'm (or really I'm going to have a better attempt at AI doing it) going to try and write/good a proper version and integrate it into either https://platform.wafer.space or maybe even LibreLane.

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message-1499667569290772520

2026-05-01T07:03:30.995+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) / @Andrew Wingate - I just had the thought that maybe it should be LibreLane that is generating Andrew's KiCAD footprints + wire bonding diagrams and my random pin out diagrams?
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message-1499667642838159491

2026-05-01T07:03:48.53+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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@Leo Moser (mole99) - Terrible or good idea? 😛
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message-1499667934451073055

2026-05-01T07:04:58.056+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I don't know how that would work? You  must specify a standard wirebonding frame first? Like from a set?
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message-1499668328648675378

2026-05-01T07:06:32.04+00:00 — RebelMike (@rebelmike)

Content

Not sure if Librelane, but a script that could generate the correct sized pad + drawing annotations in the exact pin positions could be useful. For the whole padring I guess it would be possible at least for a standard rectangular one - just push the pins out until the 45 degree rule wasn’t violated
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message-1499675040734646343

2026-05-01T07:33:12.326+00:00 — RebelMike (@rebelmike)

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Yeah I don’t know how much thought was given to the pin allocations for the different sizes - I suspect @Leo Moser (mole99) was just trying things out.
Potentially we try to route them all to match the existing template as much as possible, then change the template to make them match completely?
Though I suspect in general this doesn’t matter too much - the case of wanting them to match has only really come up because TinyQV was used in different slot sizes as a test.
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message-1499676461941133364

2026-05-01T07:38:51.168+00:00 — Tim 'mithro' Ansell (@mithro_)

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I think having a "standard" which means people can share "motherboards" PCBs is helpful rather than everyone having to design new ones.
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message-1499677454329970850

2026-05-01T07:42:47.772+00:00 — RebelMike (@rebelmike)

Content

I don’t think a standard mapping of the template pinout is required for that - it’s probably the other way around: if there was a standard SoC host motherboard (with flash, ram, etc) and the pinout for that and all the breakouts was known, you could just wire things up correctly in the silicon.
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message-1499677670764576799

2026-05-01T07:43:39.374+00:00 — RebelMike (@rebelmike)

Content

But I guess that is basically the same as saying make the template match whatever we end up with
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message-1499679472318681208

2026-05-01T07:50:48.898+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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That is a good point though to think about some things upstream instead of all downstream.
Thanks for the thought
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message-1499751781847269547

2026-05-01T12:38:08.833+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Greg - Don't say I didn't warn you 😛 - https://github.com/mithro/wafer-space-die-pad-diagrams

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message-1499768034443657387

2026-05-01T13:42:43.754+00:00 — Thorben (@thorben_61995)

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That looks much more professional than what I did 😅
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message-1499768127917916161

2026-05-01T13:43:06.04+00:00 — Thorben (@thorben_61995)

Content

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message-1499778621341040782

2026-05-01T14:24:47.867+00:00 — Tholin (@tholin)

Content

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message-1499779014867554326

2026-05-01T14:26:21.691+00:00 — Andrew Wingate (@anfroholic)

Content

@Tholin here's yours, anyone else can have theirs if they wish.

We're looking to integrate this into the verification system, so you'd just get one anyways.

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message-1499779196728377364

2026-05-01T14:27:05.05+00:00 — Andrew Wingate (@anfroholic)

Content

Yours is still very neat that is shows the sub-projects as well!
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message-1499780803373170801

2026-05-01T14:33:28.104+00:00 — Tholin (@tholin)

Content

To show the macro locations is a bit tricky. The position of each macro is specified in the librelane config, but to get its size, you need to open up its LEF.

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message-1499781132668112897

2026-05-01T14:34:46.614+00:00 — Tholin (@tholin)

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I see the analog pads are all just labeled "PAD" in this
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message-1499781353166864546

2026-05-01T14:35:39.185+00:00 — Andrew Wingate (@anfroholic)

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Yeah, we were talking earlier about pincounts and what's actually needed.
How many of the pins did you end up using for real? all of them? Most of them?
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message-1499782574141210775

2026-05-01T14:40:30.288+00:00 — Tholin (@tholin)

Content

All of them

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message-1499782848998277284

2026-05-01T14:41:35.819+00:00 — Andrew Wingate (@anfroholic)

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Like I said we were talking about some reduced pin counts.
In your opinion what's a reasonable low number?
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message-1499782882108112916

2026-05-01T14:41:43.713+00:00 — Andrew Wingate (@anfroholic)

Content

*lower
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message-1499783088459485297

2026-05-01T14:42:32.911+00:00 — Tholin (@tholin)

Content

I always need as many as possible for my processor designs for memory throughput

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message-1499783242524659844

2026-05-01T14:43:09.643+00:00 — Tholin (@tholin)

Content

I can finally build 32-bit wide data buses on wafer.space
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message-1499783308635148503

2026-05-01T14:43:25.405+00:00 — Andrew Wingate (@anfroholic)

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It's all good. There really is no answer.
Ah, ok, that's a good thought.
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message-1499783362485686342

2026-05-01T14:43:38.244+00:00 — Tholin (@tholin)

Content

My GFMPW-1 RISC-V core multiplexes both halves of the address and both halves of a word onto the same 16 pins
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message-1499783420161691718

2026-05-01T14:43:51.995+00:00 — Tholin (@tholin)

Content

4 clock cycles for a single instruction fetch, worst case
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message-1499783473689264249

2026-05-01T14:44:04.757+00:00 — Tholin (@tholin)

Content

3 clock cycles best case
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message-1499783477141307434

2026-05-01T14:44:05.58+00:00 — Andrew Wingate (@anfroholic)

Content

I see. Thanks for the insight
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message-1499783791936274453

2026-05-01T14:45:20.633+00:00 — Tholin (@tholin)

Content

wafer.space still doesn’t give enough pins for separate address and data buses on a 32-bit CPU without compromises, but its almost there

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message-1499784038565548042

2026-05-01T14:46:19.434+00:00 — Andrew Wingate (@anfroholic)

Content

Getcha, the question revolved around trying to come up with some less expensive cob or packaging alternatives.
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message-1499787500493738024

2026-05-01T15:00:04.822+00:00 — Lofty (@ravenslofty)

Content

CHES uses 4 GPIOs for JTAG and 11 for ULPI

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message-1499787688382042182

2026-05-01T15:00:49.618+00:00 — Lofty (@ravenslofty)

Content

(if that's a useful datapoint)
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message-1499787926526099517

2026-05-01T15:01:46.396+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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They are all useful. Thank you.
I think we just need to put together some numbers and see where any kind of step functions are.
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message-1499789386596745408

2026-05-01T15:07:34.504+00:00 — Lofty (@ravenslofty)

Content

(side note, I don't suppose there's a way to manually annotate the pad diagrams with actual pin functions rather than the toplevel pin name)
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message-1499789648694870246

2026-05-01T15:08:36.993+00:00 — Tholin (@tholin)

Content

Unfortunately, we are talking about integrated circuits, where IO is often the bottleneck
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message-1499789649785389087

2026-05-01T15:08:37.253+00:00 — Andrew Wingate (@anfroholic)

Content

Does this data exist somewhere? If it exists and people will use it we can incorporate it into the pipeline
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message-1499789770966958361

2026-05-01T15:09:06.145+00:00 — Lofty (@ravenslofty)

Reply/reference

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ULPI was my solution to that problem :p
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message-1499789861165469757

2026-05-01T15:09:27.65+00:00 — Lofty (@ravenslofty)

Reply/reference

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uh, I have it as source code defines; nothing more structured if that's what you're asking for
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message-1499789872645538053

2026-05-01T15:09:30.387+00:00 — Andrew Wingate (@anfroholic)

Content

Can you share what that acronym is?
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message-1499789994464907305

2026-05-01T15:09:59.431+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I see, if there's a way to get it into the GDS that's our source of truth.
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message-1499790033849286897

2026-05-01T15:10:08.821+00:00 — Lofty (@ravenslofty)

Reply/reference

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UTMI+ Low Pin Interface; uh, USB Hi Speed PHY interface

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message-1499790227273678929

2026-05-01T15:10:54.937+00:00 — Lofty (@ravenslofty)

Content

which means I can do 480Mbps serial (well, theoretically) while having my chip only have to achieve 60MHz
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message-1499790255572914197

2026-05-01T15:11:01.684+00:00 — Tholin (@tholin)

Content

I mean, particularly for memory. Ever CPU I ever taped out on gf180mcu was memory bottlenecked. Caravel was **aggressively** memory bottlenecked.
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message-1499790336644481196

2026-05-01T15:11:21.013+00:00 — Andrew Wingate (@anfroholic)

Content

I know Tim has been interested in SerDes, this can probably help with pincounts someday as well?

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message-1499790368710066196

2026-05-01T15:11:28.658+00:00 — Lofty (@ravenslofty)

Content

yes
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message-1499790432798900345

2026-05-01T15:11:43.938+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I am marginally aware how they didn't let you do a lot
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message-1499790564378284162

2026-05-01T15:12:15.309+00:00 — Lofty (@ravenslofty)

Content

(although I feel like at that point we *need* a better standard cell library >.>)

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message-1499790679386095676

2026-05-01T15:12:42.729+00:00 — Lofty (@ravenslofty)

Content

(this is not directed at Tholin, it's directed at myself to try to get back to working on my synthesisable domino logic library)

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message-1499792352078729436

2026-05-01T15:19:21.53+00:00 — Tholin (@tholin)

Content

There is a lot I need to improve about my SCL before I’m fully confident in it
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message-1499792671538155521

2026-05-01T15:20:37.695+00:00 — Lofty (@ravenslofty)

Content

It also doesn't help that I'm having to work with custom timing extraction scripts from ngspice to characterise the cells
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message-1499793314915025016

2026-05-01T15:23:11.088+00:00 — Lofty (@ravenslofty)

Content

I also think my library will probably have to rely on yours for the non-logic stuff because I have zero clue what to do there
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message-1499798631975485653

2026-05-01T15:44:18.774+00:00 — RebelMike (@rebelmike)

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Tiny Tapeout offers 26 pins (plus any analog pins) so 26-30 might be something to consider for a lower cost option on the smaller slots. Although Wafer Space is quite a different offering to TT people might prototype on TT and then bring things across.

It might also be interesting to have a higher pin count option for the full size slot.

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message-1499798868618121307

2026-05-01T15:45:15.194+00:00 — Andrew Wingate (@anfroholic)

Content

I don't think there are any plans to lower any counts, only to try to offer a lower cost version.
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message-1499799957169897492

2026-05-01T15:49:34.725+00:00 — RebelMike (@rebelmike)

Content

I guess I was thinking it might be interesting to have the current option (56 IOs) plus a smaller option (~26 IOs) for the half slots.
And the current option plus a larger option (~80 IOs?) on the full slot.
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message-1499800798912057425

2026-05-01T15:52:55.412+00:00 — RebelMike (@rebelmike)

Content

Though the larger option would obviously need a different connector (presumably 2x50) - I know there was some concern about two connectors but TT should soon find out if that causes any problems
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message-1499801217143013627

2026-05-01T15:54:35.126+00:00 — Andrew Wingate (@anfroholic)

Content

2x mezzanine was shunned pretty hard by those here, so I don't see that as an option.
Maybe if we can get back to looking at some kind of LGA or something.
https://discord.com/channels/1361349522684510449/1408134567491145728/1426376335709966446
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message-1499801806367363092

2026-05-01T15:56:55.608+00:00 — RebelMike (@rebelmike)

Content

Yeah I remember that discussion but I think it was probably over cautious. But the new TT boards should be a good indicator of whether it’s a problem in practice (they have 2x mezzanine)

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message-1499803844434071603

2026-05-01T16:05:01.521+00:00 — Trevor Peyton (@trev5514)

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I was going to use this for my daughter/motherboard cards: HC-PBB40C-90DP-0.4V-02 it's a 90 pin version, much easier than a 2x50 (in my opinion).
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message-1499803880954007724

2026-05-01T16:05:10.228+00:00 — Trevor Peyton (@trev5514)

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https://jlcpcb.com/partdetail/HCTL-HC_PBB40C_90DP_0_4V02/C19089238

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message-1499827952794472458

2026-05-01T17:40:49.402+00:00 — namibj

Reply/reference

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Content

DDR to the rescue?
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message-1499961580555731056

2026-05-02T02:31:48.743+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

FYI - The diagrams are at https://github.com/mithro/wafer-space-die-pad-diagrams/tree/main/diagrams

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message-1499961892322414704

2026-05-02T02:33:03.074+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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You have a ULPI USB interface?
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message-1499962688971870278

2026-05-02T02:36:13.01+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

At the current time packaging is a large part of the cost here and packaging is driven up by the number of IO pins. IO pads also take up quite a bit of die space. Hence figuring out options for SERDES and other ways to reduce pin count is something I'm very interested in.
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message-1500018810009292860

2026-05-02T06:19:13.308+00:00 — Lofty (@ravenslofty)

Reply/reference

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Yes
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message-1500020064487739523

2026-05-02T06:24:12.399+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lofty - Cool! I think having a bunch of proven USB connectivity solutions would be a huge gain for community.
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message-1500020151079145483

2026-05-02T06:24:33.044+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt also had some type of USB interface on the Tiny Tapeout chip.
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message-1500020583491047434

2026-05-02T06:26:16.139+00:00 — Lofty (@ravenslofty)

Reply/reference

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I knew I was going to be bandwidth hungry but also needed some kind of standard communication interface; at one point the plan was to have the chip be its own PHY and run at Full Speed, but then it was suggested that I could use ULPI and aim for Hi Speed instead.
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message-1500021496268193833

2026-05-02T06:29:53.762+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

FWIW - The original design doc for Caravel had it providing a high speed interface between your tape out and a computer and a whole bunch of "virtual" digital and analog pins that could be queried via virtual logic analyser / virtual oscilliscope so the limited number of pins that we could provide cost effectively was less of an impact, but that never quite happened.
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message-1500021615910588497

2026-05-02T06:30:22.287+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I'm still interested in reaching that type of goal.
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message-1500200044505337958

2026-05-02T18:19:22.979+00:00 — namibj

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If you have a little space (it's the smallest analog tile on ttsky26a, but you'd probably want higher current output drivers if they don't have to go through an analog mux), two analog pads, and some tt-style Mux'd digital access, and would give a functioning one to @azonenberg for characterization, I'd put considerable effort into porting my currently-in-progress ttsky26a submission to gf180mcud in time for the wafer.space Run2 GDS deadline.

(I hope to assume correctly that there is deep-nwell and the capability for placing `nmos_03v3_nvt` devices with raised bulk in said deep-nwell. And decent models of those in the region just around/above the (effective) threshold.
With those "requirements" I'd see no reason why my ttsky26a submission wouldn't be readily portable to Run2.
At least for short channels (no backplane or multi-meter Twinax!) an RX design might be possible to attempt before the Run2 deadline.)

I'll try my best to get a parasitics-extraction simulation of the VCO core done today so we'd know where things stand both with the VCO itself as well as with an SDR latch fast enough to do a DIV2 on the VCO. No inductors involved.
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message-1500207102885363914

2026-05-02T18:47:25.828+00:00 — tnt (@246tnt)

Content

So has anyone tested their COB package yet ?
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message-1500207250965532703

2026-05-02T18:48:01.133+00:00 — Tholin (@tholin)

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I will on tuesday
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message-1500207515387039754

2026-05-02T18:49:04.176+00:00 — Tholin (@tholin)

Content

Or... wednesday? The package got delayed?
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message-1500207543744467004

2026-05-02T18:49:10.937+00:00 — Tholin (@tholin)

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That’s not good, I’m not home wednesday
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message-1500207752780316743

2026-05-02T18:50:00.775+00:00 — Tholin (@tholin)

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Did the COBs get shipped in an envelope (like the dies) or package?
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2026-05-02T19:11:13.459+00:00 — Simi (@simi150500)

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envelope
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message-1500213217455247610

2026-05-02T19:11:43.655+00:00 — Tholin (@tholin)

Content

Oh, very good. Lets hope it fits in my mailbox.

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message-1500249852670382110

2026-05-02T21:37:18.171+00:00 — namibj

Reply/reference

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making you have a mailbox that will fit them (if you ask nicely enough you can probably get fairly good dimensins) could allow you to reduce the need for hope/luck. (I should get me a mailbox that can fit German Maxibrief; C4 (or B4?) at the 3?5?cm thickness, or at least letters of full size (non-folded) without substantial bending....)
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message-1500250172003713224

2026-05-02T21:38:34.306+00:00 — Tholin (@tholin)

Content

The envelope with the dies fit
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2026-05-02T21:38:53.171+00:00 — Tholin (@tholin)

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So should be fine
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2026-05-02T21:41:20.417+00:00 — namibj

Reply/reference

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(I say this because the COBs are from what I could see at breaking tap's post, slabs of PCB as they were processed at the bond house, not individualized or like the dies, taped.)
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message-1500337742633238753

2026-05-03T03:26:32.771+00:00 — Andrew Wingate (@anfroholic)

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@Tim 'mithro' Ansell do we know the formfactor the COB were send in?
Envelope or box?
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message-1500342502253920408

2026-05-03T03:45:27.553+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate - Smaller padded envelope inside a non-padded fedex envelope.

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message-1500365917790404782

2026-05-03T05:18:30.252+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate - BTW Did you share the bond diagrams you are generating here?
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message-1500371092861358121

2026-05-03T05:39:04.085+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I only shared Breaking Taps' version.
https://discord.com/channels/1361349522684510449/1408134567491145728/1499326875657306113
I can share more if you like.
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message-1500758824737443942

2026-05-04T07:19:46.568+00:00 — tnt (@246tnt)

Content

@Greg Does the arrow sticker on the picture mean you found an issue with that particular chip ?
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message-1501243612468350976

2026-05-05T15:26:08.97+00:00 — Tholin (@tholin)

Reply/reference

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I don’t know how I failed to notice that my dies are upside-down when I looked closely at this. Confirmation bias, probably.
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message-1501247113500033128

2026-05-05T15:40:03.681+00:00 — tnt (@246tnt)

Content

I'm looking at https://discord.com/channels/1361349522684510449/1408134567491145728/1495357823314563143  and the pad 0 indicator (which is the one where QR code is on the dies) is on the side of the silk `Uxx` markers.
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message-1501248570676744282

2026-05-05T15:45:51.099+00:00 — tnt (@246tnt)

Content

Ah yeah, I see. In the repo for the COB PCB the board orientation is not the same as the GDS orientation. https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/blob/main/74pad-70pin-mezzanine/wirebonding/wirebonding.png
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message-1501254946706690159

2026-05-05T16:11:11.263+00:00 — Tholin (@tholin)

Content

I simply expected the top of the GDSII layout to be aligned with the top of the PCB layout, and was never informed otherwise
Even in that wireponding.png view, you have to squint to see where the QR Code and logo are.
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message-1501620109851234455

2026-05-06T16:22:12.941+00:00 — Meinhard Kissich (@meinhard)

Content

How are Vcore, VIO, and Vaux currently/in future used? The cob module routes them separately but they seem to be low-ohmically connected.
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message-1501626241134887002

2026-05-06T16:46:34.753+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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In the (very) near future, you will be able to have separate voltage domains in your chip by using the wafer.space template. The foundry-provided pads short the core and I/O domain on purpose.

This will be possible thanks to Tim's 3.3/5V I/O cells, which have a level shifter between core and I/O domain and keep both domains properly separated in the power/ground pads.

As for Vaux, the idea is to provide another voltage domain directly to the core.

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message-1501653252511367261

2026-05-06T18:33:54.767+00:00 — Meinhard Kissich (@meinhard)

Reply/reference

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Great, thanks for the info @Leo Moser (mole99)

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2026-05-07T13:31:51.161+00:00 — Greg (@greg.hashtag.9468)

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Yes. that particular one has a lifted bondwire.
Found just with a visual inspection. Threw a QC flag so I didn't forget about it.
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2026-05-07T13:35:08.035+00:00 — tnt (@246tnt)

Content

Interesting. I couldn't really tell from the image.
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message-1502858335022485666

2026-05-10T02:22:28.827+00:00 — Tim 'mithro' Ansell (@mithro_)

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@tnt - FWIW @Lauri has been contracted to do an automated tester base around the reverse biasing the ESD diodes like you suggested.
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message-1505605939904909474

2026-05-17T16:20:28.879+00:00 — BreakingTaps (@polyfractal)

Content

@Andrew Wingate  question about the mezzanine breakout board. I'm looking at the die and COB pinout, Pad0 is top right on the die (by QR code) and bonds to top-right pad on COB (by wafer.space logo). So I'm assuming it drops down a via and goes to the right side of the mezzanine connector (while still at the die from above).

But the mezzanine breakout board lists Pad0 on the left side and the silkscreen has a dot on the top-left pin too. I _think_ Pad0 will drop down onto the right side of the breakout board but thought I'd ping first before I started releasing magic smoke 🙂

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message-1505607347471388873

2026-05-17T16:26:04.469+00:00 — tnt (@246tnt)

Content

Why not check the cob pcb directly?
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message-1505610231072297082

2026-05-17T16:37:31.973+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Hey @BreakingTaps
Yeah, sorry about how this all looks, nothing ever wanted to play nice with the way the pads were laid out and the way kicad wants things. I have been talking with @Tim 'mithro' Ansell and @Leo Moser (mole99)  about changing how we have our orientations and pin/pad orderings so things make better sense here and across the different sizes.

The first picture is how it would look if you were looking 'through' the cob at the pinout. The other one is how it would look if you had it backwards and were looking at the mezzanine connector directly from the back.

Hope that makes sense, also I just arrived home from Shenzhen in what turned into a 4 day journey home, so please reverify yourself please.
Hope this helps

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message-1505610413243633717

2026-05-17T16:38:15.406+00:00 — Andrew Wingate (@anfroholic)

Content

And yes, pad 0 is the one by the qr code
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message-1505612211853197312

2026-05-17T16:45:24.228+00:00 — BreakingTaps (@polyfractal)

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Oh yikes, four day travel home apologies for the ping! 😱  Glad you made it, I imagine things did not go quite to plan.  Cheers for the help!
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message-1505612331952898168

2026-05-17T16:45:52.862+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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I've only used kicad like twice, but this might be the sign that it's time to learn 🙂
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message-1505612663550509307

2026-05-17T16:47:11.921+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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No need for apologies!
Can't wait to see you bring it up. Don't hesitate ever to message, I could be in any timezone ;)

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message-1505617356096016674

2026-05-17T17:05:50.711+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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@psychogenic has some great YouTube videos on using KiCAD 🙂

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message-1505961873525309501

2026-05-18T15:54:50.067+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lauri seems to have made some great progress on the wire bond connectivity tester!

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message-1506058212300816516

2026-05-18T22:17:39.021+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lauri - The number of pads @ https://mithro.github.io/gf180mcu-project-template/ are now correct for the 1x1 default.

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message-1506677903277162507

2026-05-20T15:20:04.863+00:00 — Zorin (@zorin1384)

Content

Is there anyone looking for a developer?
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message-1506787415321219353

2026-05-20T22:35:14.569+00:00 — RebelMike (@rebelmike)

Content

I've been having some luck routing the tall thin one (0p5x1) by having the die at 45 degrees:

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message-1506787577905020978

2026-05-20T22:35:53.332+00:00 — Andrew Wingate (@anfroholic)

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That's interesting
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message-1506787942562267187

2026-05-20T22:37:20.273+00:00 — RebelMike (@rebelmike)

Content

Ended up breaking compatibility with some of the TinyQV pins, but none of the important ones - so bidir[27:0], in[1:0], clk and rst_n all match the 1x1
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message-1506788137345482953

2026-05-20T22:38:06.713+00:00 — Andrew Wingate (@anfroholic)

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Oh, is this one also only 2 layers?
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message-1506788178361712740

2026-05-20T22:38:16.492+00:00 — RebelMike (@rebelmike)

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Yeah
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message-1506788423648805105

2026-05-20T22:39:14.973+00:00 — Andrew Wingate (@anfroholic)

Content

Would you mind setting your min trace spacing to .103mm please.
The last boards I had to change a bit as the boardhouse complained some parts were <.1mm
I don't think you did anything wrong. I checked and DRC was clean...
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message-1506788434075844820

2026-05-20T22:39:17.459+00:00 — RebelMike (@rebelmike)

Content

I guess the one thing I haven't considered yet is whether I can connect all the grounds, but hopefully I'll work something out 😄

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2026-05-20T22:39:55.45+00:00 — Andrew Wingate (@anfroholic)

Content

haha, if it has to be 4 I don't think that's the end of the world, and if that's the case you can also disregard the previous statement.
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message-1506788680931475628

2026-05-20T22:40:16.314+00:00 — Andrew Wingate (@anfroholic)

Content

4layer spec is .09 so we're all clear there.
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message-1506788864910561401

2026-05-20T22:41:00.178+00:00 — RebelMike (@rebelmike)

Content

Will do.  Also for the last one I had hole to hole 0.25mm, but I double checked the JLC rules and they are 0.2 so I tuned that down to 0.2, does that sound ok?  Maybe should put a safety fudge on that too?
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message-1506789075875532851

2026-05-20T22:41:50.476+00:00 — Andrew Wingate (@anfroholic)

Content

Wouldn't hurt.
Again, I have no idea why they failed us. let me get the pic, 1 sec
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2026-05-20T22:43:08.391+00:00 — Andrew Wingate (@anfroholic)

Content

This was what they sent us.

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message-1506789631826591945

2026-05-20T22:44:03.025+00:00 — RebelMike (@rebelmike)

Content

Hmm, was the problem via to track?
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message-1506789779675680900

2026-05-20T22:44:38.275+00:00 — Andrew Wingate (@anfroholic)

Content

4 layer is also an easy fix.
Also I have no idea, there are arrows everywhere it seems 🤣

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message-1506789881056333965

2026-05-20T22:45:02.446+00:00 — Andrew Wingate (@anfroholic)

Content

> Hi there,
>
> Sorry to bother you, but we'd like to confirm with you an issue found when engineer making production file of your PCB order.
>
> The spacing between traces is smaller than 0.1mm which is not enough to proceed, could we help you cancel this order?
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message-1506790361480171611

2026-05-20T22:46:56.988+00:00 — RebelMike (@rebelmike)

Content

Weird, maybe some unit conversion caused some rounding issue?  Anyway, I'll go up to 0.103 - I've got a bunch of tightly packed traces but hopefully won't take too long to wiggle them apart!
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message-1506791329106104523

2026-05-20T22:50:47.688+00:00 — RebelMike (@rebelmike)

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Cool, and good to know that 4 layer isn't a major issue - if we end up trying to do custom CoBs to match important pins on all the Racquet and TinyQV designs then routing might get even more fun!
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message-1506791959208136724

2026-05-20T22:53:17.916+00:00 — RebelMike (@rebelmike)

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Anyway - I need to call it a night - I've pushed my WIP to https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/half-slot-dev if you want to take a look

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message-1506792126032117861

2026-05-20T22:53:57.69+00:00 — Andrew Wingate (@anfroholic)

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Thanks and goodnight
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message-1506794513182494771

2026-05-20T23:03:26.831+00:00 — namibj

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Are you doing JLC? If so, I'd be surprised why you weren't just going for 4L in the first place.
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2026-05-20T23:12:38.191+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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We are. That's why I was saying that as well. It's not much difference in price
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2026-05-20T23:13:04.207+00:00 — namibj

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Yeah 4L for signal integrity!
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2026-05-20T23:13:12.776+00:00 — Andrew Wingate (@anfroholic)

Content

That as well
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message-1506855164328411136

2026-05-21T03:04:27.191+00:00 — namibj

Content

In the interest of possibly understanding safety margins that were shown to not be that large by Tholin's DAC's OpAmps, do we have material datasheet information or enough detail that I could dig such up for the COBs?

Notably, thermal expansion behavior of the board; how the chip is attached to the board; what the goop is that's covering the front of the die.
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message-1507137474617413652

2026-05-21T21:46:15.209+00:00 — RebelMike (@rebelmike)

Content

So I was thinking - if the plan is to do custom CoB PCBs for TinyQV and the other run 1 half slot designs, then why are we trying to match the pinout for the default template on the generic half slot CoBs?  It would be better just to do the natural pinout and then fix the templates, rather than doing more complex than necessary routing and then locking that in for future runs.  It would also make sense to update all the CoBs to 4 layer for better signal integrity if the cost difference is negligible.
That does obviously require the generic CoBs are completed reasonably quickly so that the template can be updated in plenty of time for the run 2 designs.  But I wouldn't suggest moving any of the power pads, clock or reset, and beyond that it is likely that pinout matching only matters if people are submitting the same design at different slot sizes, or expecting a common motherboard to work between different slot sizes on the basis of using pins with the same name in the template.
Thoughts?
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message-1507137958451613898

2026-05-21T21:48:10.564+00:00 — Andrew Wingate (@anfroholic)

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I've been speaking with @Tim 'mithro' Ansell  and have been wanting to change things about the layout and the standard template and fix things at the beginning so it's harmonized across the sizes from the start.
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message-1507138895450472458

2026-05-21T21:51:53.962+00:00 — RebelMike (@rebelmike)

Content

Cool, it probably wouldn't take long to work out what the natural pad order would be and adjust the default template, even if the routing isn't actually done at that point.  I know @Leo Moser (mole99) is planning to push a significant template update soon so if that is the direction maybe getting it done before that goes out would be a good idea

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message-1507191439187251220

2026-05-22T01:20:41.365+00:00 — Tim 'mithro' Ansell (@mithro_)

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I'm sure a professional packaging house will happily provide you with all these details if you are willing to order at least 1 million units a month.

For $1.50 USD for <1000 units getting things like data sheets is pretty impossible most of the time.
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message-1507267446501933097

2026-05-22T06:22:42.921+00:00 — Leo Moser (mole99) (@mole99)

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I agree, we should probably do all of the major changes now, so people only need to migrate once.

@Andrew Wingate we should also change the pin order of the die to match the CoB, so that it doesn't need to be turned upside down. This should help reduce the confusion around the pinout, too.
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message-1507272433609084928

2026-05-22T06:42:31.94+00:00 — tnt (@246tnt)

Content

Why not just rotate the CoB PCB by 180 deg ... ?
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message-1507274253777637536

2026-05-22T06:49:45.902+00:00 — tnt (@246tnt)

Content

The pin number themselves already match, it's just on the PCB version / footprint, it was rotated so the first is on the top right instead of bottom left ...
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message-1507295311398309939

2026-05-22T08:13:26.43+00:00 — Leo Moser (mole99) (@mole99)

Content

I thought there was a reason downstream why that isn't easily possible. @Andrew Wingate what was the reason again for rotating the die?
Perhaps we should just change the PCB then. In any case, it should be consistent.
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message-1507457326225821758

2026-05-22T18:57:13.775+00:00 — Andrew Wingate (@anfroholic)

Content

@tnt @Leo Moser (mole99)
Just rotating won't fix the underlying problem.
We should strive to harmonize default across the different die sizes.
If we follow something like my diagrams here, you could design for any size die and still get a cob that matches all three (or four if the 1/4 slot follows)
I prefer the fiducial to be up top because it follows convention

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message-1507458022031626313

2026-05-22T18:59:59.668+00:00 — Tholin (@tholin)

Content

I think the thing that made it confusing is that the die has a wafer.space logo on it and the PCB has a waver.space logo on it, but they are on *opposite corners* from each other
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message-1507458100226031666

2026-05-22T19:00:18.311+00:00 — Tholin (@tholin)

Content

Instead of it being used as a alignment marker
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message-1507458432674959382

2026-05-22T19:01:37.573+00:00 — Andrew Wingate (@anfroholic)

Content

Agreed that did not help.
Not sure how it's getting announced, but if you want to have the COB 3 corners will be used by the defaults.
Qr code, ws logo, blank space. The Qr and the blank will be in opposing corners
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message-1507465742893711430

2026-05-22T19:30:40.465+00:00 — tnt (@246tnt)

Content

@Andrew Wingate The current COB footprint on the PCB has the pad 0 in the top right, not top left ... so if you rotate it 180 it's fine and aligned with the die.
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message-1507465812498448578

2026-05-22T19:30:57.06+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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That is correct
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message-1507465963446997013

2026-05-22T19:31:33.049+00:00 — tnt (@246tnt)

Content

That was the main issue in assmbly ... people expected the die to be placed in the same way it was visible in the GDS.
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message-1507466671319945460

2026-05-22T19:34:21.819+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I believe what we have here is an [x y problem](https://en.wikipedia.org/wiki/XY_problem)
To me, I think harmonizing across the die sizes is the bigger issue. If you're changing that, then also change the position of the fiducial so it cannot be confused.

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message-1507791663039250553

2026-05-23T17:05:45.883+00:00 — RebelMike (@rebelmike)

Content

I think there are just two independent issues that should be addressed at the same time:
- The CoB layout for half and quarter slots isn't finalised (and wasn't known when run 1 designs were done), so projects in different size slots can't match their pinouts.  Once the layout is known it would make sense to harmonize the default template (but most people will customize that anyway, so the important thing is knowing the mapping).
- The wafer space logos are in different places on the board and the chip, which is confusing.  The proposal seems to be to change both board and template to have the logo (and therefore pin 1) in the top left, is that correct?  Obviously everyone will need to update their run 2 projects if that change is made.
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message-1507808370663620659

2026-05-23T18:12:09.291+00:00 — Andrew Wingate (@anfroholic)

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Agreed, and thanks for the work you've done with the half slot dies.
And to be clear, a lot of the changes I'm requesting are still just my opinion.
That said, having worked with a number of the downstream effects, someday we're likely to want to make changes.
Harmonizing the template across sizes will help with whatever next version of cob we may introduce, if people want to harmonize across different dip like packages, this would be easier.
Unless I'm mistaken, I think we collectively have enough information to make some better decisions across the board. And doing so sooner than later would be better.

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message-1507810034321461369

2026-05-23T18:18:45.938+00:00 — Andrew Wingate (@anfroholic)

Content

Also of note, any of these propositions are _only_ for people who are looking to get the standard COB packaging.
Other than that, anyone's still free to do whatever they like.
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message-1507810502405914878

2026-05-23T18:20:37.538+00:00 — RebelMike (@rebelmike)

Content

On the half slot CoBs, I’ve now got distracted by a possible run 2 silicon project, but I could potentially do some more on those.
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message-1507810821290463363

2026-05-23T18:21:53.566+00:00 — Andrew Wingate (@anfroholic)

Content

The first panels of the p5x1 version should be back from the board house in the next few days if I understand correctly

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message-1507811763654230119

2026-05-23T18:25:38.243+00:00 — RebelMike (@rebelmike)

Content

CoB work items I'm aware I could look at:
- Make a simplified version of the 1x0p5 CoB, and also going up to 4 layers.  That would become the standard one going forwards
- Have another go at the 0p5x1 - this time going for the simplest routing, and hence probably just having the chip in the obvious "upright" position rather than diagonal.  Again change to 4 layers.
- Create run 1 TinyQV specific 1x0p5, 0p5x1 (and eventually 0p5x0p5) CoBs that match clk, SPI, UART to the pinout of the 1x1 GD03 Racquet project.
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message-1507812148754251848

2026-05-23T18:27:10.058+00:00 — RebelMike (@rebelmike)

Content

Then there's:
- Create a motherboard against that pinout that could be used by TinyQV or Racquet with the custom CoB
- And also make a TinyQV motherboard for the original 1x0p5 CoB, if I'm likely to receive any chips bonded to it 🙂
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message-1507812391948386416

2026-05-23T18:28:08.04+00:00 — RebelMike (@rebelmike)

Content

I would ideally like to get my hands on a TinyQV board a little before the run 2 deadline as I may be doing a revision so it would be good to know if anything didn't work
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message-1507813688890101770

2026-05-23T18:33:17.255+00:00 — Andrew Wingate (@anfroholic)

Content

> And also make a TinyQV motherboard for the original 1x0p5 CoB, if I'm likely to receive any chips bonded to it
As far as I understand, this is definitely the plan. I can't imagine it's not. I'm not in China anymore so am a bit more detached now.
I would bet something gets sent to you in about a week or two.
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message-1507814535917211780

2026-05-23T18:36:39.202+00:00 — RebelMike (@rebelmike)

Reply/reference

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Awesome!  There's two copies of TinyQV in this size slot so even if Tim would like a bunch in a custom CoB eventually there should be loads left still.  I'll put together a quick motherboard based on the pinout on the existing CoB so I have something to test with.

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message-1507824796157874328

2026-05-23T19:17:25.434+00:00 — RebelMike (@rebelmike)

Content

Just to double check, is this the correct part for the mating connector?  https://www.lcsc.com/product-detail/C19089292.html

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message-1507824907944329346

2026-05-23T19:17:52.086+00:00 — RebelMike (@rebelmike)

Content

The link from the https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/ readme is broken (maybe the part number has changed?)
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message-1507825094553108655

2026-05-23T19:18:36.577+00:00 — Andrew Wingate (@anfroholic)

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Content

That is correct.
Keep in mind there are a number of different heights if that is of concern, and there are also other compatible brands as well.

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message-1507825637006639235

2026-05-23T19:20:45.908+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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The link has been fixed. Thanks

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message-1507894215638519838

2026-05-23T23:53:16.328+00:00 — RebelMike (@rebelmike)

Content

Doh.  Just finished routing my board.  For some reason at that point I decided to double check that the pinout of the mezzanine connector was correct.  And it's not - the pins on the connector in the motherboards project which I grabbed the footprint from are flipped compared to the CoB!  That doesn't matter for those simple breakouts because they just expose all the pins.  Incidentally I think that means the pin 1 marking on those simple breakout motherboards is actually against pin 70.
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message-1508020406219571271

2026-05-24T08:14:42.507+00:00 — RebelMike (@rebelmike)

Content

Ah, this is the same thing that @BreakingTaps spotted last week!

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message-1508060919693971582

2026-05-24T10:55:41.672+00:00 — Leo Moser (mole99) (@mole99)

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Started a thread.
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message-1508164767477665922

2026-05-24T17:48:20.913+00:00 — Andrew Wingate (@anfroholic)

Content

Hey @Leo Moser (mole99) stuff seems to get lost in threads on discord.
For starters, I don't think any of this 'should' happen for run2. I think it's too late for that.

> I'm not exactly sure what your diagram is showing?
I just decided to make a rough thing to illustrate. @RebelMike you could probably imagine a ring of vias that do whatever on the bottom side, but all route cleanly on the top.

> I agree that we should harmonize what we can between the different slots sizes. What are your plans with regards to matching the pinout?
If we want to keep that many pins on all the half slots and drop 2 from the 1x1 we end up with them all being identical. I don't know what this means in reality, but if someone wanted to prototype on a half slot, then move to a larger size, the pin/padout stays identical.

> PS: Looking at the CoB PCB for the 1x1 slot, pin 1 of the mezzanine connector seems to be in the top right corner rather than the top left. Why is that the case?
KiCads generic connector library and most packages and connectors in general have pin1 in the top left. I would prefer, if someone were to take a generic mezzanine connector and use the footprint provided by the manufacturer, for pin1 to line up. There's already a lot of confusion when trying to go through all these maps to add one more translation.

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message-1508172165143334983

2026-05-24T18:17:44.654+00:00 — tnt (@246tnt)

Content

But connectors is on the bottom of the PCB, opposite of die. And then the connector on the "user side" is also swapped because it's the other side of the connection ... they can't be all top left pin 1 footprint, at some point swap needs to occur ...
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message-1508172732980789379

2026-05-24T18:20:00.037+00:00 — Andrew Wingate (@anfroholic)

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Agreed, when mentioning the connector above, I was referring to the connector a user would be sourcing (on their motherboard). The important one in my mind is the final connector and the die itself to match.
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message-1508177185683542167

2026-05-24T18:37:41.644+00:00 — tnt (@246tnt)

Content

But the "manufacturer footprint" argument doesn't hold really. If you look at the kicad library ( in the Hirose library for DF12 that's the closest I have installed ), the `DS` side connector which would be the "user side" , they standardized indeed on pin 1 top left ... with the connector horizontal. Which means top right if you put it vertically ( or bottom left ) ...
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message-1508180695720399119

2026-05-24T18:51:38.502+00:00 — Andrew Wingate (@anfroholic)

Content

Whatever, I'm not religious about this. Seems like others are. I also tend to make and throw a bunch of stuff against the wall to see what sticks.

More to the point of harmonizing. There is an error in my pictures from the last post. I am reposting more correct versions.
I have also created an example slot_size.yaml thing.
I am not sure how many people will be designing for multiple slot sizes, or how difficult that is. @RebelMike can maybe speak to that.
In the spirit of making more things, I propose a config that has a different shape. There is a single list of pads that doesn't change between slot sizes.

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message-1508180969243283636

2026-05-24T18:52:43.715+00:00 — Andrew Wingate (@anfroholic)

Content

And for the record I am aware this obscures a starting pad even further
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message-1508189330760532138

2026-05-24T19:25:57.256+00:00 — namibj

Content

IMO what needs to be clear and uniform across all 3 slabs of multilayer routing is that there's exactly one clear orienting corner, and they all line up when assembled correctly.
Die, COB, motherboard's socket area.

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message-1508189912413765682

2026-05-24T19:28:15.933+00:00 — namibj

Content

That's easy to verify when looking at a layout and picking like 3-ish nets to highlight and visually check.

The top surface of all 3 is the same "up".

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message-1508190402472317018

2026-05-24T19:30:12.772+00:00 — namibj

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(in the sense of surface-normal-vector direction)
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message-1508199491474423981

2026-05-24T20:06:19.759+00:00 — RebelMike (@rebelmike)

Content

I was assuming power pads would stay where they were and this was simply an exercise in renaming the signal pads in the default template on the half (and quarter) slots.  That basically has no implications except for helping make the CoB pinout clearer as there would be a single mapping default template -> pins, which projects could compare their renamed pins against.

But for run 3 obviously bigger changes could be considered - I'm not clear on what the implications of removing two power pads from the 1x1 pad ring would be.
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message-1508203021593743371

2026-05-24T20:20:21.405+00:00 — namibj

Content

Don't remove too many power pads, at least if we have a way to not fry chips as much as the avalon Run1 DACs are doing.
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message-1508203059166183576

2026-05-24T20:20:30.363+00:00 — namibj

Content

larger chip more consumption
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message-1508203395284992041

2026-05-24T20:21:50.5+00:00 — RebelMike (@rebelmike)

Content

My thoughts:
- The wafer space logos should be in the same position as it's the obvious marker to align in assembly (I'd weakly suggest top right as aesthetically it looks most pleasing there - Andrew and Leo both put it there independently AFAICT) - this doesn't necessarily need to mean "pin 1".
- To allow that without users having to change their run 2 designs, the CoB pinout should be changed (this would likely end up ~a 180 degree rotation on the current pinout, and maybe if it could be exactly that that would leave some compatibility between run 1 and run 2).
- The project pad -> mezzanine pin mapping should be clearly documented, with reference to the pad names in the default template and the pin names on the mezzanine footprint for the user's motherboard.
- The signal (and VDD?) pins on the default templates should be harmonized as much as possible, so the above documentation applies to all slot sizes

Ideally that should be done for run 2, because the current state is a source of confusion and mistakes.
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message-1508204149307867308

2026-05-24T20:24:50.273+00:00 — RebelMike (@rebelmike)

Content

On the pin types in the templates, I suspect it would make sense to keep some analog and input ones to highlight their existence in the template, rather than just making everything bidir.  My principle of least change was suggesting make everything match the current 1x1 but that does have quite a large number of dedicated inputs
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message-1508205051250737192

2026-05-24T20:28:25.313+00:00 — Andrew Wingate (@anfroholic)

Content

Think of all these as conceptual models rather than genuine proposals.
More power pins are perfectly acceptable.

An overarching goal expressed by @Tim 'mithro' Ansell is to look for ways to reduce cost in efforts towards accessibility.
This likely means moving away from the mezzanine all together, and taking any decoupling caps with it, since assembly is no longer an operation we're doing.
No caps means more pins can be used for whatever purpose as they all become generic wires.
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message-1508205283506130964

2026-05-24T20:29:20.687+00:00 — namibj

Content

Yeah it's a good top right corner "arrow"
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message-1508205552621195266

2026-05-24T20:30:24.849+00:00 — namibj

Content

Attachments

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message-1508205644447219794

2026-05-24T20:30:46.742+00:00 — namibj

Content

qr code lacks coarse structure contrast
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message-1508205910198063306

2026-05-24T20:31:50.102+00:00 — namibj

Content

W.S logo or alternatively (if for some reason that has to not be there) an Intel LGA style triangle should be strongly recommended.
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message-1508206014611198113

2026-05-24T20:32:14.996+00:00 — namibj

Content

(The QR would work if the other corners were blank, but they aren't.)
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message-1508207136566546463

2026-05-24T20:36:42.491+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I think all that sounds reasonable.

> The project pad -> mezzanine pin mapping should be clearly documented, with reference to the pad names in the default template and the pin names on the mezzanine footprint for the user's motherboard.
I'm finally getting settled as I get home and plan to work on cleaning the repo with the current COB and better document the motherboard.
I think that will take away most of the confusion.

> The wafer space logos should be in the same position as it's the obvious marker to align in assembly (I'd weakly suggest top right as aesthetically it looks most pleasing there - Andrew and Leo both put it there independently AFAICT) - this doesn't necessarily need to mean "pin 1".
The one request I did have, is whatever corner we are using as 'fiducial' has the opposing corner blank. This could happen this run, or not.

> To allow that without users having to change their run 2 designs, the CoB pinout should be changed (this would likely end up ~a 180 degree rotation on the current pinout, and maybe if it could be exactly that that would leave some compatibility between run 1 and run 2).
I don't understand this one fully? Basically rotate all the copper 180? That would do it? (negating changes to the schematic)

> The signal (and VDD?) pins on the default templates should be harmonized as much as possible, so the above documentation applies to all slot sizes
This is a run3 thing?
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message-1508207962148311211

2026-05-24T20:39:59.325+00:00 — Andrew Wingate (@anfroholic)

Content

> The signal (and VDD?) pins on the default templates should be harmonized as much as possible, so the above documentation applies to all slot sizes
I think I see. When making all this I did not have that info.
I've been filling in this spreadsheet as I got more info
https://docs.google.com/spreadsheets/d/1pI2BAEWEexXcXN3vah3SR85zPIV6eAXPGXc2bcvoSGU/edit?gid=0#gid=0
You're saying to use the info in the `config.yaml` column?

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message-1508208941840994354

2026-05-24T20:43:52.902+00:00 — RebelMike (@rebelmike)

Reply/reference

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> The one request I did have, is whatever corner we are using as 'fiducial' has the opposing corner blank. This could happen this run, or not.
The location is specified in the project's config, but I assume is validated by the submission system, so changing it and then advising people of the change should be possible?

> Basically rotate all the copper 180? That would do it? (negating changes to the schematic)
Yeah I think rotating everything through 180 but leaving the logo where it is would resolve it.

> You're saying to use the info in the config.yaml column?
Yes - while users will rename their pins, they will have started from this setup so it seems the most meaningful thing to me.  Maybe I'm putting too much weight on it though
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message-1508209437456994428

2026-05-24T20:45:51.066+00:00 — Andrew Wingate (@anfroholic)

Content

Can you explain the reason they may be called `bidir\\[0\\].pad` and `inputs\\[0\\].pad` instead of something more generic if it's just overwritten anyways?
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message-1508209795046441161

2026-05-24T20:47:16.322+00:00 — RebelMike (@rebelmike)

Content

This is what's specified in https://github.com/wafer-space/gf180mcu-project-template/blob/main/librelane/slots/slot_1x1.yaml
And the number of bidirs / analog / inputs match the defines in https://github.com/wafer-space/gf180mcu-project-template/blob/main/src/slot_defines.svh
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message-1508210336145215608

2026-05-24T20:49:25.33+00:00 — RebelMike (@rebelmike)

Content

Users may well change those to match their needs, but given wafer space is providing both the project template and the CoB, referring to things by those names seems like it should make sense to people

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message-1508211147642241165

2026-05-24T20:52:38.806+00:00 — RebelMike (@rebelmike)

Content

In my case, I was short on time and also didn't know what slot size you might have going spare, so I just fitted my design in to the template without changing any of the pad names.  Then you had spare slots of all half and quarter sizes so all 3 got produced!  That's what led to me wishing that the default pinout was harmonized back in run 1.  That's probably a pretty unique circumstance though so I think going forwards its more about documentation, but it would also reduce surprises if you do switch which slot you're targetting.
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message-1508212341051752652

2026-05-24T20:57:23.337+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I'm going to go out on a limb and say I don't think switching slot sizes will be all that uncommon in the future.
More or less I think things are pretty entrenched as far as run1 goes. I'll try to make the changes listed above.
I would like to keep the conversation alive about run3 though.
Thanks for the input

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message-1508216245785202795

2026-05-24T21:12:54.298+00:00 — namibj

Content

oh, hmmmmm..... @BreakingTaps any hope for the idea of using ACF and DRC-pushed FPC (JLC just about lets you do 102 um pitch on the 5$ special)?
Or is that too high resistance/would need fancy surface treatment on the die to connect to the aluminium topmetal?

I'd expect AOI to reject even up to half the FPC production to be sufficiently practical to work from that POV; but it's not easy to find out if the commodity ACF would have sufficient performance to do the task of W.S default/bargain fan-out.

It is my understanding that the traces are on top of the core and the lack of fine-pitch coverlay/soldermask would imply that these are bare metal strips on an underlying flat polyimide core; so that might be enough "bump"? It's about 12um thick there.
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message-1508258999404073021

2026-05-25T00:02:47.555+00:00 — namibj

Content

Ok I'll draw up a standard COB pinout FPC for that tomorrow.
This.... _might just work._
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message-1508259127267164303

2026-05-25T00:03:18.04+00:00 — Andrew Wingate (@anfroholic)

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What is this?
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message-1508260597412921375

2026-05-25T00:09:08.55+00:00 — namibj

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https://www.youtube.com/watch?v=0HZ35CyHVxQ
https://web.archive.org/web/20190708182030/https://fsrkj.com/upfiles/201712/22/af0aa1f1cb2886b6f.pdf
It's on aliexpress for like 7 USD a roll; seems to not be hard to get one's hands on, and it's just `190±10 C` for 10 s at 2 MPa via a hard-ish silicone sheet (200~300 um they say, shore 70+) with a thn teflon sheet (25~50 um) between that and the FPC, pressing the contact strip area down using a sufficciently solid anvil underneath to not harm the more-fragile die (or, in the original case, the LCD's glass; it works for dies too, though, "just" not well on aluminium at least with that standard metallurgy)

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message-1508262564998549544

2026-05-25T00:16:57.659+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I've seen this video before. Super neat!! Good luck!
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message-1508262942007890071

2026-05-25T00:18:27.545+00:00 — namibj

Reply/reference

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yeah same I remembered didn't even remember it was him but tbf, fits.
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message-1508525758107222136

2026-05-25T17:42:47.786+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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oh that's a fun idea! I'm not sure to be honest, might be dodgy for high frequency signals, but maybe fine for less demanding tasks? I dont actually have much experience with the stuff on real projects, just tearing down existing projects to get to the ACF for microscopy 🙂 But yeah it's used all over for displays

Could be a really clever way to get flipchip without needing the fab to bump for us!

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message-1508543310468350092

2026-05-25T18:52:32.595+00:00 — namibj

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It's actually waaaay better for high frequency it's a bit resistive but I'm sure that's easy to tune away in a transceiver as we talk like a couple Ohm at the terminus.

That 3mm bond wire at 1 GHz is already 12 ohm though...

If you have any idea how to get some test dies receptive to the nickel spheres....
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message-1508543731819741254

2026-05-25T18:54:13.053+00:00 — BreakingTaps (@polyfractal)

Content

ah interesting, why would more resistance help with higher frequency? I sorta assumed you'd want the shortest, most conductive path possible?
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message-1508544043867701359

2026-05-25T18:55:27.451+00:00 — BreakingTaps (@polyfractal)

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our topmetal is aluminum right? I just skimmed that old video of mine and they used Al on the glass connector side. So it was Al -> ACF -> Ni/P coated Cu fpc
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message-1508544195277623306

2026-05-25T18:56:03.55+00:00 — Andrew Wingate (@anfroholic)

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As far as I understand, yes, it's aluminum.

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message-1508547377978413196

2026-05-25T19:08:42.365+00:00 — Christopher (@fossify_37988)

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It's easier to control resonances with slight dampening. You lose a bit of Q but you get a more consistent response

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message-1508555137277362316

2026-05-25T19:39:32.326+00:00 — BreakingTaps (@polyfractal)

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gotcha, TIL!
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message-1508680592886202448

2026-05-26T03:58:03.274+00:00 — namibj

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It's got comparatively _zero_ inductance once you include the remaining parasitics.
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message-1508681017366544515

2026-05-26T03:59:44.478+00:00 — namibj

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Wait they they.... They did Al straight to the ACF???

I'll get you a JLC special FPC layout/pinout for your die before the weekend if you'd be interested in trying.
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message-1508682482327883858

2026-05-26T04:05:33.752+00:00 — namibj

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Well it's more that you can tune the launch impedance a bit anyways once it matters and that'll easily cover the spread in series resistance from the ACF.
Like you already need the structures in the PA (yeah it's digital but it's still a power amplifier, with tuned distortion, and sometimes integrally fused modulator if the output itself is naturally clocked instead of being a second stage after the clocked stage) and a bit more tuning range to cover increased stacking of variance is not really expensive at that point.

So therefore you might as well just enjoy the much lower inductance.
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message-1508684032949354566

2026-05-26T04:11:43.449+00:00 — namibj

Content

If you have any special wishes on that provide a schematic.
I'd plan for having the mezzanine connector off the side so you could bend it and have the entire thing barely taller/thicker than the original cob, but now with the die backside exposed to attach a heatsink.

I'd probably do it on Thursday early Berlin time; if that's too early I'd get to it approximately a week later (that's Germanys closest thing to a comiket this coming weekend I'll be running on fumes by the end).
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message-1508756539077562429

2026-05-26T08:59:50.257+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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What does ACF stand for?
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message-1508756945480192101

2026-05-26T09:01:27.151+00:00 — namibj

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https://discord.com/channels/1361349522684510449/1408134567491145728/1508260597412921375
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message-1508756949934800897

2026-05-26T09:01:28.213+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

ACF is the tape stuff that @BreakingTaps is talking in the video you shared?
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message-1508756973993070602

2026-05-26T09:01:33.949+00:00 — namibj

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Yeah
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message-1508757244005711984

2026-05-26T09:02:38.325+00:00 — namibj

Content

It's what they use to bond to notably LCDs and other TFT-on-glass type active-matrix displays like OLED.
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message-1508757492727943249

2026-05-26T09:03:37.625+00:00 — namibj

Content

It's a 180~190C for 2~10 seconds thermoset epoxy used with about 2MPa pressure.
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message-1508839172499177513

2026-05-26T14:28:11.6+00:00 — BreakingTaps (@polyfractal)

Content

"Anisotropic Conductive Film" yep
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message-1508839384630165526

2026-05-26T14:29:02.176+00:00 — BreakingTaps (@polyfractal)

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At least for the glass-FPC interface, looks that way.  Copper FPC pad on top, glass on bottom. Thin film of aluminum on glass side.  (please excuse my shitty cross-section polishing I was in a rush 😄 ) Edit: also ignore the silver, iirc I sputtered a very thin layer on to help with charging on the glass

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message-1509327108911009793

2026-05-27T22:47:04.706+00:00 — RebelMike (@rebelmike)

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I did a quick tweak to the generic breakout to make it 4 layer and label clk/rst/power/ground - don't know if this would be useful to anyone else: https://codeberg.org/rebelmike/ws-breakout

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message-1509778420144541832

2026-05-29T04:40:25.689+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

Cool!
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message-1510124743519375461

2026-05-30T03:36:35.616+00:00 — Andrew Wingate (@anfroholic)

Content

Hey all, I've added and updated some of the readmes and moved all the run-1 stuff into it's own directory so we can keep things more organized moving forward.  https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs
This likely breaks any way for you to make pull requests Mike. *side note- this has the updated 1xp5 files that have the larger clearance.*
@Tim 'mithro' Ansell @RebelMike

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message-1510124889535938632

2026-05-30T03:37:10.429+00:00 — Andrew Wingate (@anfroholic)

Content

Also updated the motherboards to have these as the symbols.

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message-1511217046409445457

2026-06-02T03:57:00.919+00:00 — Andrew Wingate (@anfroholic)

Content

@RebelMike the 1xp5 boards have arrived. Pretty sure some will be bonded shortly.
@Tim Edwards I think yours and @Greg will also be bonded in this run.

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message-1511356401094627418

2026-06-02T13:10:45.665+00:00 — xianglin_pu (@chasees18)

Content

Hi Andrew @Andrew Wingate and Tim @Tim 'mithro' Ansell , I have heard from Tim that there is a good method verifying the wire bond connections. Would you mind helping pointing me to the correct location where this verification method is discussed. This would help a lot in our chip debugging. Many thanks.
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message-1511367788491702423

2026-06-02T13:56:00.632+00:00 — RebelMike (@rebelmike)

Reply/reference

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Was the ground fill on the region between the die and the pins intentional?  I think that was blocked originally.  And there was some discussion of putting soldermask in that region so the vias were covered, is that still something that we think we should try?
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message-1511372585328443514

2026-06-02T14:15:04.287+00:00 — namibj

Content

Oh as I see this now if they're done by JLCPCB, I'd propose using their serialization service that'll give per-individual silkscreen serials in plain text (+ (QR/datamatrix)), though for proper traceability beyond the bondhouse the die sorter would probably have to place the dies directly onto the COB and electronically record what specific die got placed onto that serial number COB?
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message-1511372856024498246

2026-06-02T14:16:08.826+00:00 — namibj

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Iirc we'd need those vias covered at the top or fully open to prevent air bubbles inside from going up through the encapsulation.
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message-1511373088762368031

2026-06-02T14:17:04.315+00:00 — namibj

Reply/reference

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ESD diode of the pad can be easily checked for presence once you have a working GND and a working VDD pad.
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message-1511373323043340451

2026-06-02T14:18:00.172+00:00 — namibj

Content

Iirc you just carefully diode test with pad voltage below GND to see the diode to GND, and above VDD to see the diode to VDD.
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message-1511412648611151954

2026-06-02T16:54:16.118+00:00 — xianglin_pu (@chasees18)

Reply/reference

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Thanks for the suggestion it’s good idea to check the bonding by testing the ESD diode. I am not sure the method mentioned by Tim is same as this, or there are other method verifying it (physically or electrically)
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message-1511416484407021599

2026-06-02T17:09:30.643+00:00 — namibj

Content

AFAIK the esd diode was the suggested check of bonding, shy of any testability instrumentation in the chip itself.

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message-1511471263196123277

2026-06-02T20:47:10.924+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Ooh, I don't think it has been talked about much in this discord, most of the conversation was in person when we were in China.
It seems that @namibj has filled you in.
Let me know if you have any other questions.
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message-1511472598825963774

2026-06-02T20:52:29.363+00:00 — Andrew Wingate (@anfroholic)

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It did have a no fill region. This version was the one that I went in and relaxed some of the clearances and to do so, I needed to delete it for a moment as KiCad didn't allow me to select anything under it when it was there. After I finished I hit refill and it filled everywhere, since we had reduced this to 2 layers I thought the extra pour and ground wouldn't hurt anything so I left it.
-# For future reference, you're able to add keepout areas to the footprint itself and then you don't get the selection issues I was running into (I assume you did that last because of the same issues?)

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message-1511473026921926696

2026-06-02T20:54:11.429+00:00 — RebelMike (@rebelmike)

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Ah cool - yeah I don't think it should cause a problem, just wondered how it ended up like that

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message-1511473103132164206

2026-06-02T20:54:29.599+00:00 — Andrew Wingate (@anfroholic)

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We did have another version where they did the serial numbers properly, not sure what happened this go.
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message-1511473202847809686

2026-06-02T20:54:53.373+00:00 — namibj

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Did you select the option in the interface?
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message-1511473204282265670

2026-06-02T20:54:53.715+00:00 — RebelMike (@rebelmike)

Content

I was using locking to resolve the not being able to select things problems, I feel like that is a regression in KiCAD 10?
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message-1511473471069360158

2026-06-02T20:55:57.322+00:00 — Andrew Wingate (@anfroholic)

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Oh? Could be?
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message-1511473585041182904

2026-06-02T20:56:24.495+00:00 — namibj

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You can mask object types and layers from view and mouse interaction in kicad. Those two classifications are orthogonal.
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message-1511473993776107530

2026-06-02T20:58:01.945+00:00 — Andrew Wingate (@anfroholic)

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Everything should have been the same. Again, not sure exactly what happened. We only got a few as these are the first ones for that form factor so should be ok. We'll get it next time.
I forgot about the type selection stuff. Good call
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message-1511474391282749580

2026-06-02T20:59:36.718+00:00 — namibj

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Yeah they do caution it's supposedly a best-effort thing.
I guess if you can take the day of delay you can do advanced instructions and tell them to complain if the serials somehow don't work.
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message-1511474979898654942

2026-06-02T21:01:57.055+00:00 — xianglin_pu (@chasees18)

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I see, thanks for letting me know.

I though there is a standard criteria you are using to determine if a wire is connected (physically or electrically)
Since I am trying to verify if bonding is correct, chip is functional and hopefully proceed with more units packaged.
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message-1511476409699406006

2026-06-02T21:07:37.946+00:00 — Andrew Wingate (@anfroholic)

Content

So what we did when we were just testing with a multimeter was to apply 3.3v to VSS
Then we would go around the other pins and we saw the voltage across with the diode drop. If there was no connection, you would read nothing.
The VDD pads showed up a little differently because there was a decoupling cap on the wire as well.

But at the end of the day, you are correct, we can really only when if a wire is electrically connected.

To verify things actually work how you desire, you'll have to come up with your own testing procedures.

I think what @Tim 'mithro' Ansell is asking most specifically is: Does your silicon work as expected and good enough you want them all packaged?
-# sorry meant to have this as reply to @xianglin_pu

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message-1511477415023481024

2026-06-02T21:11:37.634+00:00 — xianglin_pu (@chasees18)

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That makes sense, thanks for clarifying. When do you need our response on bonding the remaining units ?
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message-1511478379868852326

2026-06-02T21:15:27.671+00:00 — Andrew Wingate (@anfroholic)

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Don't use my opinion to judge anything too specifically, but I would say there isn't a super huge rush? Deadline would be enough time the wirebonders get done before we want them for Run#2 😜

I'm really interested to see how these work for you all though.
Please share when you're doing your tests and have one working!

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message-1511482358128185495

2026-06-02T21:31:16.162+00:00 — tnt (@246tnt)

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@Andrew Wingate Do you know what the difference is between the "COB v1" and "COB v2+" adapter for the bond tester card ?
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message-1511486125204701335

2026-06-02T21:46:14.303+00:00 — Andrew Wingate (@anfroholic)

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Can you be a little more specific, I'm not sure I know what the bond tester card is?
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message-1511486318197342273

2026-06-02T21:47:00.316+00:00 — tnt (@246tnt)

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The automatic bond tester jig thingie
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2026-06-02T21:47:10.274+00:00 — tnt (@246tnt)

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Can't remember who made it 😅
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message-1511487243200757852

2026-06-02T21:50:40.854+00:00 — Andrew Wingate (@anfroholic)

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Oh haha, yes, that would be @Lauri
I think the biggest difference is there was a v1 that used some multiplexers that could not be sourced easily.
The second version used new ones that were more readily available.

You're referring to this thing yes?

-# I should get better about sharing pictures, isn't that right @kris ;)

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message-1511487661880246443

2026-06-02T21:52:20.675+00:00 — kris (@kris____)

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the more the merrier :p

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message-1511487776661704906

2026-06-02T21:52:48.041+00:00 — tnt (@246tnt)

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@Andrew Wingate Yes this thing.

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message-1511488019062853672

2026-06-02T21:53:45.834+00:00 — Andrew Wingate (@anfroholic)

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I can try to answer some questions
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message-1511488088193634426

2026-06-02T21:54:02.316+00:00 — tnt (@246tnt)

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I have a base board `r1` same as the picture but then I got two daugther boards, one with a `COBv1` sticker and one with a `COBv2+` sticker.
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message-1511488949330378874

2026-06-02T21:57:27.627+00:00 — Andrew Wingate (@anfroholic)

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I will have to defer to @Lauri on this one. It's currently the middle of the night there.
The only COB differences that I am aware of, is the first ones he was testing were some of the originals that had the missing trace on the AUX_VDD pin. Beyond that, I left right before these came back from the PCB fab and have not had much involvement.
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message-1511491832129916948

2026-06-02T22:08:54.94+00:00 — Andrew Wingate (@anfroholic)

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I just remembered there is a little i2c memory module on the daughter board.
I bet he was reading that to choose what program to run for a pass/fail thing without having to reflash or something?
This is a guess, but an educated one.
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message-1511492405273034793

2026-06-02T22:11:11.588+00:00 — tnt (@246tnt)

Content

Oh yeah maybe. Because PCB look identical. So different programming might make more sense.
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message-1511492442648744027

2026-06-02T22:11:20.499+00:00 — tnt (@246tnt)

Content

I'll wait for them to confirm.

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message-1511569075866697730

2026-06-03T03:15:51.282+00:00 — Lauri (@lauri4332)

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Yes, the adapter boards are the same, only the EEPROM configuration differs. The v1 COB adapter skips the missing trace pad check. I've attached a picture showing which black COB is v1 and which is v2.

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message-1511619053721227374

2026-06-03T06:34:26.931+00:00 — tnt (@246tnt)

Content

@Lauri Thanks, makes perfect sense. I had forgotten there was a track missing 😅
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message-1511758397983166494

2026-06-03T15:48:09.192+00:00 — Zorin (@zorin1384)

Content

Is there anyone looking for a full stack and ai engineer?
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message-1511940645130997941

2026-06-04T03:52:20.298+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lauri - This is pretty cool!

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message-1511946026494464201

2026-06-04T04:13:43.315+00:00 — Andrew Wingate (@anfroholic)

Content

Hey all,
For the first run, originally we thought we would only have a single die size, so only had a single size tape.
I would like to give myself as much clearance as possible to land the dies in the tape, hopefully we'll be able to do this blind saving the time of having a camera step.
Any PNP should be able to pick up the components no problem.
Does anyone have opinions on 0.5mm clearance on all sides?

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message-1511955126036992051

2026-06-04T04:49:52.815+00:00 — namibj

Content

Is the camera a throughput issue or an engineering complexity issue?
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message-1511955179476615328

2026-06-04T04:50:05.556+00:00 — Andrew Wingate (@anfroholic)

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Throughput
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message-1511955383810265108

2026-06-04T04:50:54.273+00:00 — Andrew Wingate (@anfroholic)

Content

Again, not really an issue, but at 50k dies the seconds add up.
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message-1511959053809614848

2026-06-04T05:05:29.269+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate - I just randomly found https://www.digikey.com/en/articles/how-to-improve-chiplet-and-wlcsp-assembly-yields-using-precision-tape-and-reel-carriers while searching for information about tape and reel for through hole headers

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message-1511962941992472726

2026-06-04T05:20:56.284+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

I've also looked through our conversations to see what kind of material they used, I didn't find an answer. We can ask what they offer when we talk again.
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message-1511989480423293110

2026-06-04T07:06:23.539+00:00 — namibj

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Had you considered attaching them to COBs (at least for those customers that want COB service) (but not yet bonding the pad ring) directly from the sorter?
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message-1511990213608472616

2026-06-04T07:09:18.344+00:00 — Andrew Wingate (@anfroholic)

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That would for sure have to be a future rev thing. I'm not even sure how viable that would even be though.
There is some kind of glue that attaches them to the cob and I'm sure there is some kind of pot life that would be exceeded under most circumstances.
Thanks for the thought, I've tried to think of things along these lines, just don't think it will work from what we know at the moment.
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message-1511992459763257437

2026-06-04T07:18:13.869+00:00 — Leo Moser (mole99) (@mole99)

Content

Hi all, I'm wondering if anyone sees the same thing as I do here.
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message-1512005411728003254

2026-06-04T08:09:41.858+00:00 — namibj

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Content

My first thought on the glue would be to use a simple static mixer nozzle dispensing freshly mixed epoxy of a nominal pot life somewhere around 5~30 minutes, but a thermoset might be better by disconnecting pot life from hardening speed.
I'm sure there are practical solutions from the industry for the task of "die attach".

Upon re-reading  https://discord.com/channels/1361349522684510449/1361349523724570941/1506916734181834773 I'm not sure @Max Vallone meant they'll try in-house pillars on Run2 dies (~4 months until _I_ would expect actionable results reports) or if there's consideration to _try_ and verify/confirm functionality several days ahead of the Run2 GDS deadline.

_Why does that matter?:_
Depending on the extent of "bumping" treatment that needs to be done to the die (well, especially if it doesn't), skipping the T&R packaging between the "pick from stretched film" and "optically align die pads to first routing/contact layer of fan-out" (if it's the FPC-attached-via-ACF technique I suggested for prototyping and low-cost applications, this is done by looking at the die through the FPC while aligning before gently pressing them together to lock in the alignment during the travel to the hot press) might be desirable.
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message-1512041899911807047

2026-06-04T10:34:41.319+00:00 — RebelMike (@rebelmike)

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Content

Just to double check this has been communicated correctly: this was based on the original 1x1 CoB, so the die should be bonded with the Wafer Space logo in the opposite corners.
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message-1512102638806765670

2026-06-04T14:36:02.6+00:00 — tnt (@246tnt)

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Where is that app ?
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message-1512290820995420280

2026-06-05T03:03:48.73+00:00 — Lauri (@lauri4332)

Reply/reference

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This was just a widget prototype  I was experimenting with. It will need a bit more work before I can release it for use. Shouldn't take long, i'll keep you informed.
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message-1512291609545281557

2026-06-05T03:06:56.735+00:00 — Andrew Wingate (@anfroholic)

Content

@Leo Moser (mole99) and everyone, I have updated the symbol and everything on the motherboards. They now show net labels and everything where and how you would expect them.

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message-1512346718900060261

2026-06-05T06:45:55.829+00:00 — Leo Moser (mole99) (@mole99)

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Can confirm, the pins are now mapped correctly. Thanks, Andrew!

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message-1512972278982512641

2026-06-07T00:11:40.975+00:00 — BreakingTaps (@polyfractal)

Content

interesting approach to avoid wire bonding (from https://opg.optica.org/oe/fulltext.cfm?uri=oe-34-11-20833)

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message-1513093240939741289

2026-06-07T08:12:20.553+00:00 — Lauri (@lauri4332)

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Started a thread.
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message-1513187477454848170

2026-06-07T14:26:48.289+00:00 — namibj

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Also TAB (tape automated bonding), for being relatively low-tech.
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message-1513190396711276595

2026-06-07T14:38:24.294+00:00 — namibj

Content

@BreakingTaps do you have any idea yet for selectively painting the  exposed guard ring of Run1 dies so regular plating would grow just the pads up?

I'll try to make a https://www.youtube.com/watch?v=MgQbPdiuUTw in around 1~2 months I guess, but the best plan there is for the time being a way to hold a fine hollow needle and to do computer vision alignment of flip chip die to FPC.

But I'd think a litho process for separating the guard ring would be better than a mechanical painting one.

An idea I have for the TT style would be to allow on-tile flip chip pads that could be bonded out automatically via just custom FPC.

No sense trying before we have some suitable flip chip process tested, though.

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message-1513200150024032447

2026-06-07T15:17:09.665+00:00 — BreakingTaps (@polyfractal)

Content

If/when I get to it, my plan was for photolitho. I've resurrected my direct-write litho machine (half built, ordered more components to finally finish it). Probably a thick/sturdy resist like SU8, something like that

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message-1513203093813203014

2026-06-07T15:28:51.519+00:00 — namibj

Content

yeah it'd just have to shield that from the nickel spheres or while pillars are grown on the pads.
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message-1513848907988205681

2026-06-09T10:15:05.617+00:00 — Andrew Wingate (@anfroholic)

Content

Playing with some different shapes for the tape for run 2.
The ones where we don't touch the corners on a skew are about .6mm clearance.
I tried a few different shapes and I think these are pretty close to what we would be wanting. I am still not sure what we *can actually* get manufactured, but now at least have a baseline I can make some prints from.

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message-1515658100030312499

2026-06-14T10:04:10.613+00:00 — Andrew Wingate (@anfroholic)

Content

Hey all,
A bunch more cob have been made.

Unfortunately it seems like JLC has made a bunch of bad boards before we noticed, not sure what we can/will do in the short term, but hopefully a few of you will be seeing more cob sooner than later. Some are to be shipped Mon I believe.

I believe the boards are: @Greg @Tim Edwards @RebelMike @Trevor Peyton @Simi

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message-1515658743793061919

2026-06-14T10:06:44.098+00:00 — Simi (@simi150500)

Content

Awesome, thanks! 🙌

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message-1515821239908827200

2026-06-14T20:52:26.191+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Any advice on where to buy mezzanine "receiving" connectors, if I want to avoid buying from China (for tax reasons of avoiding tax hurdles)?
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message-1515821884678082571

2026-06-14T20:54:59.916+00:00 — tnt (@246tnt)

Content

Hirose might have something compatible.  DF40 maybe.

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message-1515829006212010219

2026-06-14T21:23:17.822+00:00 — RebelMike (@rebelmike)

Reply/reference

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Content

Started a thread.
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message-1516061840008810618

2026-06-15T12:48:29.725+00:00 — Thorben (@thorben_61995)

Content

After testing some different options for packaging my samples (including the ceramic carriers I posted some weeks ago), I eventually decided for CoB, too, but homemade:
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message-1516061918576509008

2026-06-15T12:48:48.457+00:00 — Thorben (@thorben_61995)

Content

Working like a charm. PCB designs and communication software will come online in the next days. Measurements can finally begin 😁

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message-1516062512364261406

2026-06-15T12:51:10.027+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I look forward to hearing about it!

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message-1516311011437838427

2026-06-16T05:18:36.823+00:00 — Architeuthis Flux (@arabidsquid)

Reply/reference

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Hey I doubt it matters for this, but if you want, here's some [PIO code](https://github.com/Architeuthis-Flux/JumperlOS/blob/main/src/ch446.pio.h) for driving those CH446Qs. I probably hold the record for most time spent worrying about those chips and RP2350s so if you have any questions about weird edge cases and stuff, lmk.

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message-1516311277528551505

2026-06-16T05:19:40.264+00:00 — Architeuthis Flux (@arabidsquid)

Content

(idk @Tim 'mithro' Ansell came by my discord to let me know about this so I figured I'd offer my services if you need them)
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message-1516312924241793155

2026-06-16T05:26:12.871+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Awesome! Thanks!
As far as I understand @Lauri already has them programmed and being used currently.

Here's an example of a test.

For those at home:
It tests the esd diode on the io pins by putting voltage on gnd and testing the volage drop.
Also checks for shorts to neighboring pins.
A picture is taken
There is a rendered result you can see here.

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message-1516346573292834876

2026-06-16T07:39:55.43+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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That is super cool!
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message-1519247405168590871

2026-06-24T07:46:47.644+00:00 — Thorben (@thorben_61995)

Reply/reference

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Started a thread.
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message-1521590430242836692

2026-06-30T18:57:08.353+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Thanks to everyone who helped me get my SRAM chips tested!  The COB boards work great (enough of them, anyway), the breakout board works great, and I was able to confirm read and write operation of all three of the 3.3V SRAM macros (256, 512, and 1024 byte) up to 50MHz.  More extensive and exhaustive testing will be done, but getting a quick answer as to whether the 3.3V SRAMs are viable for the next tapeout was key.

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message-1521590659696558141

2026-06-30T18:58:03.059+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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That's awesome!! Thanks for all your work!
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message-1521592102985666731

2026-06-30T19:03:47.166+00:00 — BreakingTaps (@polyfractal)

Content

woo! great news, cheers for making the macros and testing them!
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message-1521678126479052881

2026-07-01T00:45:36.765+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Test of writing to the lower 4 bits of 64 words at 25MHz (also works at 50MHz but it's at the sampling limit of the USB scope).

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message-1521679812828332152

2026-07-01T00:52:18.822+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Test setup with one Digilent Analog Discovery 2.

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message-1521894637655294103

2026-07-01T15:05:57.052+00:00 — namibj

Reply/reference

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Content

Can we get some amount of reporting as to how good as a PUF that SRAM behaves?
Like, reading the power-on bit pattern of a few dies and seeing how stable and unique it is per-die?

If it's at least not-terrible, I could try next week about getting a probably-smallest-tested SRAM macro set up, if I can think of a way to read it _at all_ without an electrical pad contact to the die.
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message-1521899689899720725

2026-07-01T15:26:01.601+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@namibj :  I don't have any kind of temperature force unit, so I won't be able to determine if the power-up pattern is stable over temperature.  I would tend to expect it to be dependent on the 3.3V supply ramp, as well.
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message-1521909045550907402

2026-07-01T16:03:12.162+00:00 — namibj

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Content

temperature stability shouldn't matter tooo much; trying voltage corners of the nominal-3v3, or, if not difficult, operation at reduced voltage (e.g. the foundry `Dualgate` SCL is rated down to 1.62V) would be plenty sufficcient to get an idea of if it's looking to be usable or not.

It doesn't have to be an exact match of the pattern, it just has to be closest-match by a physically-inspired metric (notably, I'd figure accounting for the impact of mismatch in the sense amplifiers would help the statistical-model-based matching, like perhaps using a polynomial chaos expansion surrogate model to decorrelate w.r.t. supply ramps and (as needed) temperature, and focus on die-specific mismatch instead.

It'd be a next-week thing though, as this week I got the extended ttgf0p3 and have already pushed schedule from the next two days to the weekend.
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message-1521910349606158556

2026-07-01T16:08:23.073+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

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I think what you will find is that some bit will always be the same at power-on but some will likely be more random. This means you'll need to transform this power-up pattern with random bits into a reproducible one.
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message-1521946120140624013

2026-07-01T18:30:31.433+00:00 — namibj

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Well, I _mostly_ care about it as being able to record them at the die sorter while the process still knows what reticle and what wafer any particular die came from (location within a reticle is obviously trivial to encode using mask ROM techniques), to then later post-packaging being able to read it out from in the circuit during e-testing and match it against the recorded database to recognize which of the dies it (with high likelihood) was, followed by printing the information onto a label or writing them into some type/choice of PROM, be it on-die or just on-PCB.
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message-1524067534402355241

2026-07-07T15:00:16.007+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

The future CoB boards will have unqiue IDs. @Andrew Wingate is hoping to keep track of the die (where from the wafer they came from) as they are loaded into the tape.

I'm also looking to source a large number of I2C EEPROMs which end up being 1-2 cents each.

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message-1524069588059554054

2026-07-07T15:08:25.637+00:00 — Tholin (@tholin)

Content

Clearly, the perfect solution is

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message-1524077397878767768

2026-07-07T15:39:27.643+00:00 — namibj

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Oh great.
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message-1527038479735853189

2026-07-15T19:45:44.572+00:00 — RebelMike (@rebelmike)

Content

First draft of 0p5x1 CoB.  Revisions compared with previous CoBs / previous attempt at this one:
- Principle of least surprise:  Schematic has pin 1 where the project template does.  Pads (except for power) are in the same order on the mezzanine connector as on the die.
- Wafer space logo moved to bottom right, so it matches the top left position on the run 2 dies
- Solder mask added between the die and pad ring
- No Ground flood fill exclusion between die and pad ring
- Pin 1 marker is in copper

Feedback welcome

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message-1527039428411785236

2026-07-15T19:49:30.754+00:00 — RebelMike (@rebelmike)

Content

One note: It'll be natural to hold these the other way up, to match the die orientation.  I think that's good, but it does mean mezzanine connector pin 1 is at the bottom, which is potentially confusing.  (Although at least on my motherboard, and I saw on the KianV one too, the CoB is mounted upside down anyway).
And one question: The ground plated through holes between the die and the pad ring, sohuld they just be normal vias?  Then all the holes should be tented, which may avoid issues with bubbles?
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message-1527039770885230773

2026-07-15T19:50:52.406+00:00 — RebelMike (@rebelmike)

Content

Project is here: https://github.com/MichaelBell/chip-on-board-wire-bonded-pcbs/tree/0p5x1-mezzanine/run-1/0p5x1-cob

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message-1527045222888898560

2026-07-15T20:12:32.265+00:00 — namibj

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IIUC/IIRC what you don't want is non-through-holes that hold an air bubble at their bottom, which get filled with epoxy that has a hard time displacing the air, thus causing those very bubbles to get stuck in the epoxy.

I'm not sure if you're allowed through holes which would let the air escape down as the epoxy flows into the hole, as the epoxy could theoretically droop down and form drops on the bottom.
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message-1527075445198295091

2026-07-15T22:12:37.825+00:00 — RebelMike (@rebelmike)

Content

Cool, so probably nothing inherently wrong with keeping them, unless that's been a problem in the existing CoBs.
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message-1527098459730215053

2026-07-15T23:44:04.917+00:00 — namibj

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IIRC the issue before was that the bottom of those was tented, but the top was open.

The cob bond house might have issues with open holes if there's worry about epoxy dripping and leaving hardened residues in places they shouldn't be; I don't know the viscosity and surface tension enough to judge if that's an actual risk with the current chemistry and thicknesses, though.

IMO keep them open and prepare to be told to tent the tops if necessary; I won't have time to search for what judgement the earlier discussions came up with, until 2 weeks from now.
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message-1527453277720154223

2026-07-16T23:14:00.118+00:00 — RebelMike (@rebelmike)

Content

And the 0p5x0p5 version:

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message-1529851763841175652

2026-07-23T14:04:43.771+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Is there a convention for the pin numbering of the wafer.space standard template padring pads? For instance, it looks like the left end of the south side is always `clk` by default, so is this a good one to call pin 1, and the rest increment in an anti-clockwise direction from there?
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message-1529858622220406876

2026-07-23T14:31:58.936+00:00 — RebelMike (@rebelmike)

Content

Yes.  The intention is that left end of south is pin 1 in the project template, and you go anti-clockwise from there.  Unfortunately the run 1 CoBs mount the die rotated by 180 degrees, so that then ends up with pin 1 at the top right.

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message-1529910420628832346

2026-07-23T17:57:48.639+00:00 — kris (@kris____)

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the corner pads look so cool
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message-1529912397001654424

2026-07-23T18:05:39.843+00:00 — Tholin (@tholin)

Content

I did ensure my layout’s padring was compatible with the standard COB this time, but I still need to check if the COB breaks out the pins how I need them.
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message-1529922272385564835

2026-07-23T18:44:54.318+00:00 — RebelMike (@rebelmike)

Reply/reference

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As long as you have power and ground in the same place as the template it should work.

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message-1529922894077886547

2026-07-23T18:47:22.541+00:00 — Tholin (@tholin)

Content

I’m using the level-shifting pads
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message-1529922930623123527

2026-07-23T18:47:31.254+00:00 — Tholin (@tholin)

Content

And do have different core and IO voltages in mind
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message-1529939927893016698

2026-07-23T19:55:03.719+00:00 — RebelMike (@rebelmike)

Content

The power pins are all independent on the breakout, each with their own cap.  Only ground are connected together
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message-1529940881413640213

2026-07-23T19:58:51.056+00:00 — Tholin (@tholin)

Content

What about IO? I've used every single pad.
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message-1529941409816117288

2026-07-23T20:00:57.037+00:00 — Andrew Wingate (@anfroholic)

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They are all good as well.
The only pads that never make it directly to the mezzanine are the ground pads, and those are all bridged.
Like Mike said, all the power pins are isolated, but also by default, have 1uF caps
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message-1535100917899075664

2026-08-07T01:42:59.623+00:00 — Essen (@essen__)

Content

Hi, I am thinking of doing a 76 pin 0.5x0.5 slot for run 3. To my understanding is that the project template ( https://mithro.github.io/gf180mcu-project-template/ ) isn't authoritative, in the event this doesn't match the expected power placement is there a list/discussion I can refer to for the power pin placement ?
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message-1535149194480984075

2026-08-07T04:54:49.657+00:00 — Essen (@essen__)

Reply/reference

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I was re-reading the entire thread (as one does (to decided if I know enough to offer to design the 76 0.5x0.5 CoB PCB that has yet to exist)) and I am actually a little concerned about the vias in the encapsulation region.
Are we really sure this is okay ?
> Open vias should not be used in the encapsulation area of the COB design due to
> capillary wicking and leakage.
source: [PCB design guidelines for chip on board (COB) applications](https://www.pi.infn.it/wp-content/uploads/2021/03/low_cost_cob_guidelines.pdf) - part of the original doc linked at the very start of the channel
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message-1535150809204006953

2026-08-07T05:01:14.637+00:00 — Essen (@essen__)

Content

Though I really don't know enough about "why" this is a bad idea to judge if this applies to us and if namibj is correct.
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message-1535151380346703954

2026-08-07T05:03:30.808+00:00 — Essen (@essen__)

Content

Will be independently taking a look at `Chip on board technologies for multichip modules` for the reason tomorrow as it is given as the source for this statement in that document.
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message-1535192897886887977

2026-08-07T07:48:29.361+00:00 — RebelMike (@rebelmike)

Reply/reference

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Interesting! These came from @Andrew Wingate‘s original 1x1 design, which did have some issues with bubbles as I understand it. But we thought that was most likely due to the vias not being covered by soldermask on top.
I don’t know if there’s a good reason why they are plated through holes instead of vias.
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message-1535194360478568478

2026-08-07T07:54:18.07+00:00 — RebelMike (@rebelmike)

Content

I think the offer of CoB bonding is normally only available if you use the standard template, though that does make it a bit strange that the bonding is the same price for quarter slot as I thought it was ~priced per bond. Worth checking with Tim though if you want to make your own CoB.

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message-1535194954002075688

2026-08-07T07:56:39.577+00:00 — Andrew Wingate (@anfroholic)

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> I don’t know if there’s a good reason why they are plated through holes instead of vias.
Partially an inherited artifact if I remember, and also a quirk of KiCad that you can't have vias in a footprint if I remember.

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message-1535196024128278528

2026-08-07T08:00:54.715+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I don't think we've gotten any of the quarter slot yet so don't have good pricing info on it yet, and am not certain prices really have to do with number of bonds directly, it's just a helpful tool to get you in the ballpark.
I'm also not certain we will be accepting *any* custom cob this time? Keep in mind the only custom ones last time shared the wirebonding layout, just had different traces and routing on the pcb.

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message-1535217872077324339

2026-08-07T09:27:43.672+00:00 — RebelMike (@rebelmike)

Reply/reference

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If there’s no particular reason for them then maybe it would be best to switch to vias - the extra clearance on them is a bit of a pain and it sounds like it would be safer to have no holes.
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message-1535288252045594654

2026-08-07T14:07:23.564+00:00 — Andrew Wingate (@anfroholic)

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Yeah, they can be taken out.

Keep in mind part of the large clearance was the assumption the dies would be 0.7mm thick. It's still too early to assume that wouldn't be the case moving forward.
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message-1535294986311049348

2026-08-07T14:34:09.138+00:00 — Essen (@essen__)

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Yeah, if the 76 pin option is part of the "standard offering" is a bit unclear. Though frankly I am not opposed to paying the extra 2c per chip bond price increase if the maximum bonds budgeted for is 74 (1x1).
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message-1535298799109541968

2026-08-07T14:49:18.18+00:00 — RebelMike (@rebelmike)

Content

As far as I’m aware the standard offering is using the project template and standard CoB pad frame only so you only get 56 pins/48 IOs on the quarter slot. But if you need something different then I’m sure it’s worth talking to Tim

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message-1535302597190094878

2026-08-07T15:04:23.713+00:00 — Andrew Wingate (@anfroholic)

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Again, any change from the standard is likely going to be a whole lot more.

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message-1535309501496959036

2026-08-07T15:31:49.828+00:00 — Essen (@essen__)

Reply/reference

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Content

So sad ... I will ask Tim after Tawain to know what extra cost I would be looking at.
Else I guess I am doing 6 ports for the second generation switch rather than 8.
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message-1535310851320578098

2026-08-07T15:37:11.651+00:00 — Essen (@essen__)

Content

In regards to adding vias it seems that there is a real concern is with wire displacements due to rapid changes in rheology during the oven-cure process ( reducing yield ).
source: Chip on Board: Technologies for Multichip Modules. Van Nostrand Reinhold, 1994, chapter 7
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message-1535311265189335062

2026-08-07T15:38:50.325+00:00 — Essen (@essen__)

Content

In regards to this issue it seems like it would be problematic for vias under the wires rather than the ones in the corner.
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message-1535311664784613498

2026-08-07T15:40:25.596+00:00 — Andrew Wingate (@anfroholic)

Content

We've done a lot of work to improve all the processes.

The PTH didn't seem to be a problem, rather the vias that were tented on the back side (there is no soldermask on the front)
We have ordered a number of untented versions, but I have been absent from that process for some time.

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message-1535333045085667418

2026-08-07T17:05:23.057+00:00 — Essen (@essen__)

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> We've done a lot of work to improve all the processes.
Nice, what kind of testing was done?
Do by any chance have any ongoing experiments for long term corrosion behavior?
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message-1535334603144040610

2026-08-07T17:11:34.527+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

The epoxy is clear so you can see everything.
Any issues I'm referring to now are likely more cosmetic than anything.
Again, any of the bubbles I saw at the end were the amount of air trapped inside of a 0.25mm via. And the only reason you'd ever even know they were there is because it's clear. Everything is encased.
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message-1535335008946888715

2026-08-07T17:13:11.278+00:00 — Essen (@essen__)

Reply/reference

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Got it, so testing by visual inspection 👍
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message-1535335543523774514

2026-08-07T17:15:18.731+00:00 — Essen (@essen__)

Content

Please don't understand this wrong way, I am not looking to impose my views on anyone, but in all transparency, the more I read the more I am personally concerned about the presence of holes in the encapsulation region.
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message-1535335907823976559

2026-08-07T17:16:45.587+00:00 — Essen (@essen__)

Content

Currently I am concerned about 2 failure modes, short term: mechanical failure of the bond (lower yield), long term: corrosion
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message-1535336103878336553

2026-08-07T17:17:32.33+00:00 — Andrew Wingate (@anfroholic)

Content

there are no holes
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message-1535336626493071421

2026-08-07T17:19:36.931+00:00 — Andrew Wingate (@anfroholic)

Content

We have also been doing electrical testing
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message-1535336658029776987

2026-08-07T17:19:44.45+00:00 — Essen (@essen__)

Reply/reference

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Seems I am confused then ? The via center ? Can you unstupid me ?

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message-1535337766257434655

2026-08-07T17:24:08.672+00:00 — Andrew Wingate (@anfroholic)

Content

Maybe I'm misinterpreting what you're referring to as holes.
The die and the wires are all encapsulated.
Parts of the pcb are exposed because it's the pcb. There's a large mezzanine and caps on the back
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message-1535338114657292408

2026-08-07T17:25:31.737+00:00 — Essen (@essen__)

Reply/reference

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I am currently using the following definition:
hole = any opening though the substrate (pcb) in which could form a contact between the epoxy and the air
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message-1535338873310421002

2026-08-07T17:28:32.614+00:00 — Essen (@essen__)

Reply/reference

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Based on this definition, do we have holes in the encapsulation region ?
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message-1535351299149791302

2026-08-07T18:17:55.165+00:00 — RebelMike (@rebelmike)

Content

Note the versions with soldermask between the pads and the die are the newer ones I did. As far as I’m aware Andrew hasn’t looked at those yet and they haven’t been made/tested. The 1x1 and the previous rev of the 1x0p5 have no solder mask in the region between the pads and the die - that led to vias that were closed on the back side but not the top side.
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message-1535352283175460935

2026-08-07T18:21:49.775+00:00 — RebelMike (@rebelmike)

Content

On the CoBs I designed - I don’t really have any expertise here, I just wanted to help out as best I could as wafer space had offered me space on the early runs for free and Andrew was short on time. It sounds like changing those holes to vias would be wise - I’ll do that when I get chance!

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message-1535355104037838949

2026-08-07T18:33:02.321+00:00 — namibj

Reply/reference

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Content

The cost complication is with the bond house setup and test-run-overhead costs of setting up and verifying the custom/new bonding does actually work.

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message-1535355288704520203

2026-08-07T18:33:46.349+00:00 — namibj

Reply/reference

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Content

Oh, well, the epoxy to the top surface of the glob is AIUI less thickness.
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message-1535355800552349716

2026-08-07T18:35:48.383+00:00 — namibj

Content

My understanding of the experienced bubble complication was with holes being tented on only the backside (where the mezzazine is) and being open on the front (where the die is), which had the air bubbles from inside escaping up into the epoxy.

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message-1535358542343573535

2026-08-07T18:46:42.077+00:00 — Essen (@essen__)

Reply/reference

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Content

That would be great, I personally believe not having an opening is the better call.

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message-1535359443573678202

2026-08-07T18:50:16.947+00:00 — Essen (@essen__)

Content

If you want some help with that kicad layout I have a cloned version of your repo opened at the moment.
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message-1535359736382226463

2026-08-07T18:51:26.758+00:00 — RebelMike (@rebelmike)

Content

I’m away for the weekend so feel free to adjust them and make a PR!

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message-1535360342245245009

2026-08-07T18:53:51.207+00:00 — RebelMike (@rebelmike)

Content

Thank you!

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message-1535364727167783036

2026-08-07T19:11:16.654+00:00 — namibj

Reply/reference

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Content

I think I'm more worried about tented vias than fully open ones at least if they're thin enough for the epoxy to not just drip down; though it already stays in a glob up top anyways, so yeah.....

For reliability IMO we should at least ask if they have a generic CTE-vaguely-matched loaded version available given that I don' think they'd require actually different processing beyond dosing the epoxy from the other dispenser.
Might be contingent on the tracability serial being included, though; in case they fall down after globbing and are all mixed up between projects somehow.

Also while you're at it and worrying about those things, maybe see if the die bottom could have thermal management improved for allowing a higher TDP.
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message-1535370471560847441

2026-08-07T19:34:06.224+00:00 — Essen (@essen__)

Reply/reference

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Nice, what kind of electrical testing do you guys do ?
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message-1535373815830286377

2026-08-07T19:47:23.56+00:00 — Essen (@essen__)

Content

( I would be curious about running a mini testing program, more specifically a subset of the IPC-SM-789 torture test mentioned in “‘Guidelines for Chip on Board Technology implementation” on my end but I don't want to create duplicates )
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message-1535467367348314172

2026-08-08T01:59:07.98+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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https://github.com/wafer-space/ws-run1-cob

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message-1535499183774240768

2026-08-08T04:05:33.607+00:00 — Essen (@essen__)

Reply/reference

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Are these a random sample of chips or are these all the chips that have been reported as some point as having failed packaging and is this an analysis of the failure modes ?
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message-1535500223915368578

2026-08-08T04:09:41.596+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Various test runs to try and understand the current state and what needs to be fixed.
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message-1535500401221304400

2026-08-08T04:10:23.869+00:00 — Essen (@essen__)

Reply/reference

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Was this run on a random sample ?
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message-1535506676919046244

2026-08-08T04:35:20.112+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lauri and @stuart are working on it.
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message-1535680432715079792

2026-08-08T16:05:46.722+00:00 — BreakingTaps (@polyfractal)

Content

ah was just going to ask about the rest of Run1 COBs. I guess still working out kinks in the process?
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message-1535927777327583273

2026-08-09T08:28:38.273+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Yes, I have been meaning to chat with you about your parts and how you wanted to proceed.

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message-1536016039236604055

2026-08-09T14:19:21.552+00:00 — Essen (@essen__)

Content

CoB PCB (0.5x0.5 focus) 🧵
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message-1536016323061223484

2026-08-09T14:20:29.221+00:00 — Essen (@essen__)

Content

Attachments

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2026-08-09T14:30:13.459+00:00 — Essen (@essen__)

Reply/reference

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Started a thread.
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message-1536472392237588480

2026-08-10T20:32:44.586+00:00 — Essen (@essen__)

Content

Do you have some rules from the packaging house, more specifically, do we know :
- how large the fingers need to be in x and y
- how far are the fingers are from one another
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message-1536498308472897696

2026-08-10T22:15:43.498+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Here's something.
Not from our wirebonding house, but may be considered fairly representative
https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view

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message-1536501011693178963

2026-08-10T22:26:27.996+00:00 — Essen (@essen__)

Reply/reference

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