This page owns analog layout verification and parasitic extraction. It does not redefine process options or the submission sequence.
Current summary
The archive's explicit tapeout guidance is to trust KLayout DRC. Magic DRC may report false positives and was not required for tapeout. Decision, 2026-03-16, by Leo Moser. (archive message; Discord)
The later analog-flow summary says precheck uses KLayout DRC. Designers may use Magic or KLayout for layout. It names Magic plus Netgen, or KLayout, as LVS routes. Confirmed guidance, 2026-06-14. (archive message; Discord)
Do not call Magic and KLayout DRC equivalent. A clean Magic result can be useful, but the archive assigns tapeout authority to KLayout. For the full signoff meaning, see Precheck and Signoff.
PEX and resistor models
The public resistor model list did not include pwell or isosub resistors in the cited question. Leo Moser said Magic PEX can still extract their resistance. Confirmed tool behavior reported 2026-06-08. This is not a compact-model claim. (archive message; Discord)
Practical order
- Run layout checks in the chosen editor.
- Run the wafer.space KLayout precheck and treat its DRC result as the acceptance result described in the archive. (archive message; Discord)
- Run LVS with a supported route named in the archive. (archive message; Discord)
- When pwell or isosub resistance matters, the archive reports that Magic can extract it during PEX. (archive message; Discord)
Related pages
Sources
1483013259635327016— 2026-03-16T08:05:14.151Z — Leo Moser (mole99) — archive message; Discord — KLayout is the trusted tapeout DRC; Magic DRC is not required.1513436381781950605— 2026-06-08T06:55:51.705Z — Leo Moser (mole99) — archive message; Discord — Magic PEX extraction of pwell and isosub resistance.1515650076645523457— 2026-06-14T09:32:17.689Z — Leo Moser (mole99) — archive message; Discord — Layout, DRC, and LVS tool routes.