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#gf180mcu-opt

37 Discord messages from Internal/gf180mcu-opt/channel.md.

Category: Internal Channel ID: 1361350052395618434

Messages: 37

message-1361353945653448807

2025-04-14T14:54:33.377+00:00 — Matt Venn (@mattvenn)

Content

:asic_hats:
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message-1361354912423870709

2025-04-14T14:58:23.873+00:00 — tnt (@246tnt)

Content

What's the `-opt` for ?
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message-1361395668685553988

2025-04-14T17:40:20.923+00:00 — mole99

Content

Cost optimization I assume if it is about the metal layer reduction
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message-1362101660100333841

2025-04-16T16:25:42.393+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Yes
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message-1362101866736910381

2025-04-16T16:26:31.659+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://docs.google.com/document/d/1Uf6xGZHpuA_G4iyAvxDwEENMjPBAf0Q16D0c8F0lbDQ/edit?tab=t.0#heading=h.vv35m449hl9p
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message-1362125440537460896

2025-04-16T18:00:12.091+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell Don't have access. Sent request 🙂
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message-1362126641463300357

2025-04-16T18:04:58.414+00:00 — tnt (@246tnt)

Content

Which metal stackup would we get ?
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message-1362129933694140487

2025-04-16T18:18:03.343+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - TBD - I would like to get us to three metal layers but I know it will be a headache for TinyTapeout
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message-1362130070470263047

2025-04-16T18:18:35.953+00:00 — tnt (@246tnt)

Content

That's just not doable.
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message-1362130222425837649

2025-04-16T18:19:12.182+00:00 — tnt (@246tnt)

Content

The standard cell need 1 metal layer pretty much for their exclusive use. TT need a metal layer for its exclusive use.
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message-1362130780393967747

2025-04-16T18:21:25.212+00:00 — tnt (@246tnt)

Content

So the only way to do routing would basically be a channel router but (1) AFAIK that's not supported by the tooling and (2) this would make the logic density ridiculously low. gf180 was already not the greatest logic density because we only had 5v standard cell but limited to channel routing, it would easily divide it by 2 (and that's optimistic).
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message-1362974275602088099

2025-04-19T02:13:10.141+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - I'd like to eventually get some actual numbers and results - the "default option" is the exact same configuration at GFMPW-0 / GFMPW-1
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message-1363060565110554715

2025-04-19T07:56:03.163+00:00 — tnt (@246tnt)

Content

Thing is it depends what you want to do ... for just pure basic digital designs, sure you can get rid of a lot of the stuff ... but to me that's also makes the process boring and not interesting. I can create full digital designs in a FPGA just fine so meh 🤷
The interesting part is analog/mixed-signal design and that's were those weird things like native Vt, deep-nwells, or the efuse stuff because they're the "fun bits" to play with.
That's just my 2ct at least.

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message-1363065518055096380

2025-04-19T08:15:44.037+00:00 — tnt (@246tnt)

Content

For TT itself, as stated above, you couldn't just "port" whatever we have now to 3 metal, that just wouldn't work out. You could imagine something TT-like, but you'd basically be starting from scratch since you'd have to using comb power routing and that completely change the way you need to combine stuff and also limits layout option (like, you couldn't do combining of tile area vertically like we do now since that'd be cutting power rails ...).

To realistically port the current "architecture" you'd need 4 metal layers, ( 1 for local interconnect of standard cells, 2 for XY routing, 1 for top level PDN for TT ) with the top one being thick metal ( say 30KA ).

And if you stick with 3 metal, you also have a balance to find for the TopMetal. Because on one hand you ideally want it to be thin, because it's a routing layer, you need to have a relatively fine grid. But on the other, it's your sole layer for PDN so you want its sheet resistance to be low so you don't need rails that are unpractically wide ...
11KA is the thickest option that still has a realistic pitch to use as signal routing and that's 40 mOhms/sq ( ~ 30% higher than in sky130 top metal ).
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message-1363259961672597504

2025-04-19T21:08:23.008+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - Why did you run the PDN over the top of the designs rather than down channels between each tile?
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message-1363260059236306974

2025-04-19T21:08:46.269+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - Trying to get as many projects onto one shuttle as possible?
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message-1363261251232469265

2025-04-19T21:13:30.463+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - Also, does that mean TinyTapeout designs can't use Metal 5?
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message-1363261262464680146

2025-04-19T21:13:33.141+00:00 — tnt (@246tnt)

Content

Several reason :
(1) It'd be wasting space between tiles
(2) Powering only from one side isn't great for IR drop for large tiles. We actually have a minimum of 2 rails going over each tile. More for larger tiles.
(3) We allow to combine multiple tiles, if you have something running between them, you can't do that because it would cut your power rail ... shutting down power to other projects on the same row.
(4) We power gate each project. That's a lot of different "power domains" (think like 500 different power domains on a tiny chip !) so our PDN routing takes quite a bit of space and even though we pretty much fill the entire thick top metal (at least as much as density allows), we still end up with PDN impedance higher than I'd like. So imagine using the space between tiles, we'd need quite the area ...
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message-1363261451162226790

2025-04-19T21:14:18.13+00:00 — tnt (@246tnt)

Content

And yes, on sky130 tiny tapeout designs can't use `Metal5`. And on IHP they can't use `TopMetal2`
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message-1363261650626547804

2025-04-19T21:15:05.686+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

BTW Have you written this up somewhere?
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message-1363261901408043039

2025-04-19T21:16:05.477+00:00 — tnt (@246tnt)

Content

The only case were people wanted to use it is to make inductors but :
* Inductors are impractically large anyway, given the cost of a tile, for the price you'd need to pay to put your inductor you might as well have paid for a ChipIgnite-mini slot ...
* The IO speed wouldn't allow you any kind of RF frequency interface
So it wasn't all that much of an issue ...
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message-1363262308712972320

2025-04-19T21:17:42.586+00:00 — tnt (@246tnt)

Content

Written what up ?
The whole TT code is public and people can have a look if they choose to. The final GDS of each shuttle is published and people are free to lookup how things are assembled.
There was also some video from Matt about the TT organization and why some of the choices were made.
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message-1363263096176640151

2025-04-19T21:20:50.332+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - Do you mean this video series -> https://www.youtube.com/watch?v=oFz6XTZvfB4 ?

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message-1363263132331409679

2025-04-19T21:20:58.952+00:00 — tnt (@246tnt)

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Yes.
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message-1363263280478687312

2025-04-19T21:21:34.273+00:00 — tnt (@246tnt)

Content

Although I'm not sure we get much into PDN anywhere.
People tend to think power distribution is boring stuff 😅
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message-1363263376649879703

2025-04-19T21:21:57.202+00:00 — tnt (@246tnt)

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Just the stuff blocking the view of their chip art that lies underneath.

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message-1363263417649205430

2025-04-19T21:22:06.977+00:00 — Tim 'mithro' Ansell (@mithro_)

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Yeah 🙂
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message-1363263754946609208

2025-04-19T21:23:27.395+00:00 — tnt (@246tnt)

Content

I did a bunch of measurement and improvements over the various shuttles ... and TT8 would have been the final iteration with all the improvements done 😅  But I guess I'll never see the result of that ...
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message-1363264613432561694

2025-04-19T21:26:52.074+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

> we still end up with PDN impedance higher than I'd like

What is the effect of the higher PDN impedance?
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message-1363265134017122506

2025-04-19T21:28:56.191+00:00 — tnt (@246tnt)

Content

For digital it can cause voltage drops when power spikes on clock transition, that can screw up your timings.
For analog, well your supply drop more with power usage, so depending on how much current you use, that can get your design out of its correct operating point.
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message-1363265830955258119

2025-04-19T21:31:42.354+00:00 — tnt (@246tnt)

Content

For GF180 you probably have a bit more margin ... simply because dropping 0.1V of 5V isn't quite as bad as loosing 0.1V when your VDD is 1.8V (or 1.2V for IHP).
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message-1363273425409544342

2025-04-19T22:01:53.013+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Yeah
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message-1473727264809029823

2026-02-18T17:06:00.459+00:00 — Samuel Napaa (@samuelnapaa)

Content

I need information on the thickness of the chip
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message-1473842188533104991

2026-02-19T00:42:40.41+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

We don't have a real answer for that, but we will not be back grinding these or anything.
It is probably safe to assume they will be ~0.75mm
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message-1473999609998082141

2026-02-19T11:08:12.612+00:00 — Samuel Napaa (@samuelnapaa)

Content

alright thanks
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message-1475328962719907988

2026-02-23T03:10:34.999+00:00 — Alb123 (@alb123_)

Content

hi is there a question channell
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message-1475330502515757157

2026-02-23T03:16:42.115+00:00 — Alb123 (@alb123_)

Content

Is solder bumping possible post-fabrication? I wanted to try to flip two chips on top of each other and try to make a 2.5d chip
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