Category: ℹ️ - Information
Parent channel: #⁉️-questions
Thread ID: 1437404783563771935
Messages: 4
message-1437404783563771935
2025-11-10T11:33:26.091+00:00 — Tholin (@tholin)
- Message ID:
1437404783563771935 - Author ID:
220639106915368960 - Nickname: Tholin
- User name: tholin
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Content
I am overhauling the testbench for my DAC circuit in xschem. Is there a way I can set up a binary counter for the bench that isn’t....whatever this is that I came up with originally (this goes on for all 12 input bits).
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</details>message-1437439382146650179
2025-11-10T13:50:55.036+00:00 — tnt (@246tnt)
- Message ID:
1437439382146650179 - Author ID:
596068704471482370 - Nickname: tnt
- User name: 246tnt
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Content
The only alternative I know is going to a full cosimulation setup, integrating verilator or iverilog and using RTL for the control logic ... but that's quite a bit of stuff to setup ...
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</details>message-1439246074567983175
2025-11-15T13:30:04.076+00:00 — Matt Venn (@mattvenn)
- Message ID:
1439246074567983175 - Author ID:
492702620759228416 - Nickname: Matt Venn
- User name: mattvenn
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Content
https://github.com/mattvenn/tt08-analog-r2r-dac-3v3/tree/main/sim
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</details>message-1439246087117475840
2025-11-15T13:30:07.068+00:00 — Matt Venn (@mattvenn)
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1439246087117475840 - Author ID:
492702620759228416 - Nickname: Matt Venn
- User name: mattvenn
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Content
Heres a demo
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