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Thread: WLCSP ?

226 Discord messages from ℹ️ - Information/⁉️-questions/threads/wlcsp.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1526018113768919210

Messages: 226

message-1526018113768919210

2026-07-13T00:11:10.368+00:00 — Jorropo (@jorropo)

Content

Hello I own a small PnP business.

We very reliably Pick-and-Place 300µm pitch BGA family part.

Without much knowledge of the silicon making process.
Would it be possible to create a 300µm grid of 100µm gold pads on the top metal layer;
reflow some ready made balls on the top of the chip;
And reflow it directly to the PCB ?

(I guess add some epoxy at some point too)

---

I don't particularly care for WLCSP or BGA, QFN is much easier to inspect, but WLCSP looks like a packaging method which doesn't require much equipement beyond a good 0402 or 0201 class pick and place machine.
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message-1526018524156395582

2026-07-13T00:12:48.212+00:00 — Jorropo (@jorropo)

Content

(Such pick and place cost start at 1k$ to 2k$ but they come with a steep learning curve to get such good results.)
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message-1526020476751712377

2026-07-13T00:20:33.747+00:00 — Jorropo (@jorropo)

Content

Hum if my search is to believed I would need an extra masked sputtering step to deposit gold on the top side of the IC.
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message-1526020611879735388

2026-07-13T00:21:05.964+00:00 — Jorropo (@jorropo)

Content

sounds highly automatable, I guess it would be much cheaper than wire bonding ?
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message-1526020995549364368

2026-07-13T00:22:37.438+00:00 — namibj

Content

The chip itself has aluminium top metal and silicon nitride passivation.

It is possible to expose only the bond pads from the passivation (there are options already prepared in the design rule checks).

If you have an ability to bond that out through a flip-chip process, at a cost cheaper than the chips themselves, at these quantities you can see on the website (i.e., 1k chips for 4~10 $ each depending on if half or full slot and depending on whether early bird discount applies), please share.
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message-1526021299779145738

2026-07-13T00:23:49.972+00:00 — namibj

Content

Notably, per my research, there are electroless zincate base plating methods available to build up a standard ENIG stackup or other such solderable surface on the aluminium, without needing high vacuum or any further lithography.
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message-1526021348181151854

2026-07-13T00:24:01.512+00:00 — Jorropo (@jorropo)

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Content

oohh
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message-1526022393183862915

2026-07-13T00:28:10.66+00:00 — namibj

Content

I'll draw a few test pad-pairs of realistic proportions (but not the same proportions throughout) that target bonding via AnisotropicConductiveFilm to high-fidelity (mostly due to copper thickness though) COTS FPC (polyimide core, 0.33 oz copper either side, "solder mask" much less detailed than the copper features themselves, so fine pitch would have to be without solder mask bridges between pads), specifically the 2L FPC special offer at JLCPCB (for prototyping convenience, and as it's realistic).

If you happen to have some plating/bumping targeted pad-pair geometries in mind, feel free to join/contribute/share.
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message-1526022783677632584

2026-07-13T00:29:43.761+00:00 — namibj

Content

we haven't yet found an affordable performant (more than the ACF can offer, at least) option for flip-chip packaging at the quantities we're dealing with here, sadly, so therefore contributions would be well-received.
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message-1526023468116611193

2026-07-13T00:32:26.944+00:00 — Jorropo (@jorropo)

Content

Ok so I see 3 problems
1. readying the ICs for accepting the balls
2. applying balls, I don't have experience given commerce ICs come with balls
  I've seen plenty of electronics repair people doing this everyday with nearly 100% yield and artiasanal equipement (jigs and laser cut steel stencils), so we should be able to find that knowledge in the wild
3. soldering to a PCB, that I know how to do, there are lots of tricks, but basically you must have a flat PCB (ENIG), a good PCB footprint, and a well callibrated pnp, then you "just" place it correctly ~+-80µm in XY and it always work (/ I never had a failure yet)
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message-1526023704415567982

2026-07-13T00:33:23.282+00:00 — Jorropo (@jorropo)

Reply/reference

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Content

I'm not sure I understand that, is your "roadmap" different ?
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message-1526023717975490660

2026-07-13T00:33:26.515+00:00 — namibj

Content

(AFAIK, as long as this does not inhibit the wire bonding ability for those customers/slots who have planned to do that, it would be possible to do the electroless/plating build-up pre-dicing at wafer-scale, provided it's not a significant expense to treat the other dies; but aside from any thick gold options, I don't think any of the plating here would have reason to be too expensive to afford wasting it on the non-flip-chip dies just to get to plate the flip-chip-dies before the wafers get diced.)

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message-1526023864306372638

2026-07-13T00:34:01.403+00:00 — namibj

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Content

Essentially the chip itself is bare aluminium LGA
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message-1526023914742874172

2026-07-13T00:34:13.428+00:00 — Jorropo (@jorropo)

Content

I would suspect that if we can do flip-chip no one would want wire bonding ¿ 😄
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message-1526023997257547806

2026-07-13T00:34:33.101+00:00 — Jorropo (@jorropo)

Content

(take that with a huge grain of salt I'm no where an expert here)
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message-1526024268918554704

2026-07-13T00:35:37.87+00:00 — Jorropo (@jorropo)

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Content

ok sorry what is that trying to test ?
Afait you want to make a PCB that an analog for the top of the IC and try to develop a flipped die process on it ?
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message-1526024353202966548

2026-07-13T00:35:57.965+00:00 — namibj

Content

If you have connections/access to plating that can turn that into something you can "just" solder, I believe appropriate stencil thickness should suffice to form a robust-to-manufacture gap between the die and the PCB?
Because that's the main reason for the balls, right, vs. "just" using LGA?
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message-1526024649199058945

2026-07-13T00:37:08.536+00:00 — Jorropo (@jorropo)

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Content

I have zero LGA experience.
If you get balls on an IC it's really easy to reflow*

*assuming you've got high quality balls and they havn't been reflowed more than 2 times already and are full of oxides.
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message-1526024771173613629

2026-07-13T00:37:37.617+00:00 — Jorropo (@jorropo)

Content

Well I don't know the right word in english, but I and plenty of other peoples are making this happen every day like it's nothing.
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message-1526026026478473427

2026-07-13T00:42:36.905+00:00 — namibj

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ACF is the flip-chip/non-soldering bonding technology that's mainstream used to attach active-matrix displays and other such circuits on glass to more traditional printed circuits and also to directly attach driver ASIC dies to the display glass.

It's low cost and doesn't necessarily need plating, but it's high resistance compared to soldering and only liked by the display industry because it's much easier to hot-press an epoxy carrier tape (the ACF matrix loaded with nickel balls that when compressed perform the anisotropic conductive aspect) for 10 seconds at 200C than to deal with flux and solder-melting temperatures when a TFT display's traces-on-glass are involved.

I'm placing a few test pad pairs (likely one connected to GND and the other to VDD, or something; to ideally test that the adjacent pads don't short out to each other) on otherwise "spare" silicon area on the current tapeout (Run2), to hopefully qualify this flip-chip process for (limited) production use on the next run.
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message-1526026317877870753

2026-07-13T00:43:46.38+00:00 — Jorropo (@jorropo)

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how will you attach it to the IC ?
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message-1526026378275852338

2026-07-13T00:44:00.78+00:00 — namibj

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We don't know where to affordably get balls onto the currently produced chips; though their aluminium is actually more a hindrance than the shape.
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message-1526026498279079956

2026-07-13T00:44:29.391+00:00 — Jorropo (@jorropo)

Content

I have found a TI resources about their ENIG on IC process
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2026-07-13T00:44:33.287+00:00 — namibj

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https://www.youtube.com/watch?v=0HZ35CyHVxQ&pp=ygURYnJlYWtpbmcgdGFwcyBhY2Y%3D

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2026-07-13T00:44:46.744+00:00 — Jorropo (@jorropo)

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yeah after googling I've remembered
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message-1526026668571889824

2026-07-13T00:45:09.992+00:00 — Jorropo (@jorropo)

Content

I call it Z conductive tape but I guess that not the industry term 😄
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message-1526026673424957541

2026-07-13T00:45:11.149+00:00 — namibj

Content

I'll be back later my dinner is getting cold 😉

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message-1526026779704164444

2026-07-13T00:45:36.488+00:00 — Jorropo (@jorropo)

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bonne appétit
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message-1526026851611316315

2026-07-13T00:45:53.632+00:00 — namibj

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this ACF style is afaik from a family of z-conductive tape stuff
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message-1526027649150091394

2026-07-13T00:49:03.78+00:00 — namibj

Content

Also, you mentioned 300um pitch; we'd prefer to hit about 100~150 um pitch at least in an appriximately-QFN-style pad layout (i.e., single-row, all or at least multiple sides).
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message-1526027880394526790

2026-07-13T00:49:58.913+00:00 — Jorropo (@jorropo)

Content

100µm is tight
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message-1526027991388524635

2026-07-13T00:50:25.376+00:00 — Jorropo (@jorropo)

Content

on a good day (aka not heatwave) my placement deviation is like 25~50µm
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message-1526028028696596652

2026-07-13T00:50:34.271+00:00 — Jorropo (@jorropo)

Content

altho I have a cheap opensource pick and place
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message-1526028334931251362

2026-07-13T00:51:47.283+00:00 — Jorropo (@jorropo)

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if you've spent 10k$ or gave me 6 months to make and refine my own pnp we could probably make it happen
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message-1526028423875526808

2026-07-13T00:52:08.489+00:00 — namibj

Content

the chips take about that long to finish anyways
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message-1526028690956488754

2026-07-13T00:53:12.166+00:00 — Jorropo (@jorropo)

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If you just wanted to place on a carrier, you could use some kind of micro manipulator with openpnp and a high resolution camera and optics and you should be able to place with single digit µm accuracy

(the hardest thing is keeping everything square at all time, thermal dilation of 1m aluminium is so anoying)
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message-1526028750557413526

2026-07-13T00:53:26.376+00:00 — namibj

Content

what to think of _now_ is what geometry is still practical enough (both pad size and spacing between) to work; notably, accounting for whatever the plating process does

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message-1526029107316396144

2026-07-13T00:54:51.434+00:00 — Jorropo (@jorropo)

Content

If my researches are to be believied, adding gold to the top of a wafer is a standard process. Is that something the fab would be able to offer ? (altho I guess it would do the whole wafer)
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message-1526029175687872613

2026-07-13T00:55:07.735+00:00 — namibj

Content

yeah I'm planning for https://www.youtube.com/watch?v=MgQbPdiuUTw -based motion of the die and see-through optics through at least alignment holes in the copper of the 2L flex to line up with the die.

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message-1526029366134440007

2026-07-13T00:55:53.141+00:00 — Jorropo (@jorropo)

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Content

Just so you know lots of the software work is accounting for the X Y and Z axis not being at perfect 90° of each other
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message-1526029470476275724

2026-07-13T00:56:18.018+00:00 — Jorropo (@jorropo)

Content

there are so many layers of self calibration and compensations
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message-1526029842112446474

2026-07-13T00:57:46.623+00:00 — namibj

Content

I'm not aware of global foundries offering us plating options, sadly; at least not at these quantities we buy from them (for them it's literally "singular full MOQ" size; they do offer half-batches for very small quantities but the cost per chip is like +50% or even +80%, so it's not suitable for production orders).

There should be some third party facilities offering such services, though.
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message-1526030285953826937

2026-07-13T00:59:32.443+00:00 — Jorropo (@jorropo)

Content

It looks like it's "just" applying chemicals baths to the top of the wafer.
They could combine it with someone's else big order going through the process
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message-1526030290336743565

2026-07-13T00:59:33.488+00:00 — Jorropo (@jorropo)

Content

¯\_(ツ)_/¯
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message-1526030335274651678

2026-07-13T00:59:44.202+00:00 — Jorropo (@jorropo)

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(am I naive about that industry ? 😢)
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message-1526030695808630794

2026-07-13T01:01:10.16+00:00 — namibj

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I am not planning to have it work open-loop at substantial precision; also it's not that much reach compared to PCBs.
This example here is appriximately 230 nm step size in a 23mm cube; so "just" 100k steps; and that's not accuracy but step size.
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2026-07-13T01:01:51.179+00:00 — namibj

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yeah it's just,a nd there's a factory somewhere that has the chemical baths basically around and ready during regular business hours, or at least for a batch once a week.
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message-1526031033403838494

2026-07-13T01:02:30.649+00:00 — Jorropo (@jorropo)

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it comes in months anyhow, what's a couple more weeks of queue :Cry:
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message-1526031040940871760

2026-07-13T01:02:32.446+00:00 — namibj

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finding that factory and convincing them it's worth dealing with us at the small volumes we have for the time being/near-future, _that's_ the not-so-easy part.
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message-1526031656102789172

2026-07-13T01:04:59.112+00:00 — Jorropo (@jorropo)

Reply/reference

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I'm halfway tempted to try the zincate + enig process myself.
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message-1526031770959614072

2026-07-13T01:05:26.496+00:00 — Jorropo (@jorropo)

Content

you're getting test pads made on run2 right ?
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message-1526032098111127702

2026-07-13T01:06:44.495+00:00 — namibj

Content

find out what geometry you'd think you'd need, and what you'd think would certainly be practical enough to pull off, and if it's reasonable numbers I'll draw you a couple pads and you'd (if I don't mess up) be able to expect a couple dies to try with.

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message-1526032214721171548

2026-07-13T01:07:12.297+00:00 — Jorropo (@jorropo)

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Content

sure, I'll give you a couple geometries
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message-1526032271943925872

2026-07-13T01:07:25.94+00:00 — Jorropo (@jorropo)

Content

from I can most likely do this
to I'll certainly not be able to do this 😄
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message-1526032835570438215

2026-07-13T01:09:40.319+00:00 — Jorropo (@jorropo)

Content

Sputtering UBM looks easier but require a lithographic step.
I know they sell 2µm maskless lithography machines.
We need something like 20x less precise than this for my 300µm BGA I'm looking for.
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message-1526032948841943273

2026-07-13T01:10:07.325+00:00 — Jorropo (@jorropo)

Content

What is the best all the open source DMD mask less lithography machines reliably do ?
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message-1526032999261667480

2026-07-13T01:10:19.346+00:00 — namibj

Content

the latter shouldn't be necessary for this run 😄

We'll just include realistic gemetires this time, in hopes of all of them actually showing "somewhat usable" yield.
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message-1526033055846764664

2026-07-13T01:10:32.837+00:00 — Jorropo (@jorropo)

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Content

ok, a 300µm grid ?
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message-1526033104907538472

2026-07-13T01:10:44.534+00:00 — Jorropo (@jorropo)

Content

I'm looking up if I want circles or squarcles
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message-1526033114260832327

2026-07-13T01:10:46.764+00:00 — Jorropo (@jorropo)

Content

I guess circles
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message-1526033232213049354

2026-07-13T01:11:14.886+00:00 — namibj

Content

due to not having a redistribution layer, a classic grid of large pads isn't actually that desirable for the chip itself 🙁
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message-1526033279671865345

2026-07-13T01:11:26.201+00:00 — Jorropo (@jorropo)

Content

hum
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message-1526033312643154021

2026-07-13T01:11:34.062+00:00 — Jorropo (@jorropo)

Content

I'm not sure what that means 😄
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message-1526033371388575875

2026-07-13T01:11:48.068+00:00 — namibj

Content

the current wire bonding is basically 0.1mm pitch QFN if we'd flip-chip that.
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message-1526033489319956571

2026-07-13T01:12:16.185+00:00 — Jorropo (@jorropo)

Content

pretty small
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message-1526033585348546691

2026-07-13T01:12:39.08+00:00 — Jorropo (@jorropo)

Content

I get you only want pads on the edges, but why tho ?
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message-1526033614540640398

2026-07-13T01:12:46.04+00:00 — namibj

Content

we only have one properly thick metal layer on the chip, and it's the very same that forms the pads when we pull the silicon nitride passivation away in a spot
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message-1526033616281403454

2026-07-13T01:12:46.455+00:00 — Jorropo (@jorropo)

Content

what would happen if you didn't ?
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message-1526033716395376770

2026-07-13T01:13:10.324+00:00 — Jorropo (@jorropo)

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ah so at worst you couldn't have any gates bellow the pad area
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message-1526033755784085704

2026-07-13T01:13:19.715+00:00 — Jorropo (@jorropo)

Content

you would remove like 1/4 of your mm²
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message-1526033870976188585

2026-07-13T01:13:47.179+00:00 — namibj

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it'd be straight-forward to use with wire bonding available as a backup if the flip chip process doesn't show sufficcient yield after the chips design is submitted to the factory
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message-1526034059468472391

2026-07-13T01:14:32.119+00:00 — namibj

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it's more that we can't use it for power distribution as freely when there's pads in the way of the power connections across half the chip

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message-1526034209502662808

2026-07-13T01:15:07.89+00:00 — namibj

Content

also we don't have IO cells ready-to-use that can be placed in the middle of a chip; but I don't think that's too big of a blocker.
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message-1526034377694515371

2026-07-13T01:15:47.99+00:00 — Jorropo (@jorropo)

Content

it's a blocker if we want to get tests in this run 😄
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message-1526034482438738070

2026-07-13T01:16:12.963+00:00 — namibj

Content

so yeah, figure out pitch feasible, and how large the pads would actually have to be to support the plating process, at least as far as the plans go.
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message-1526035499679219814

2026-07-13T01:20:15.492+00:00 — namibj

Content

One of the users, TinyTapeout, has among other parts rows of analog tiles avilable for small users to put test designs on, and those are basically 300um squares; I'd ideally hope we could manage to fit two bumps on each of them at least in a line and contact them out; if the chip has multiple lines it'd be acceptable to use different PCBs that each only contact the bumps of a single row (and the outer normal/generic/multiplexed IO that currently uses the normal wirebonding pad frame).

That would allow economic testing of things like differential receivers/transmitters which would have issues with the analog MUX parasitics today.
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message-1526035816621670451

2026-07-13T01:21:31.057+00:00 — namibj

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We'll not do useful circuits connected to the flip chip pads this run, there's no time for that; we'll just do enough to let us test if the pad is shorted out and ideally to let us _somewhat_ quantify the contact resistance of the bond.

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message-1526035874188365824

2026-07-13T01:21:44.782+00:00 — Jorropo (@jorropo)

Content

100%
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message-1526035882887348274

2026-07-13T01:21:46.856+00:00 — namibj

Content

(for statistics/yield estimation purposes)
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message-1526036587928883300

2026-07-13T01:24:34.951+00:00 — Jorropo (@jorropo)

Content

Ok so the LLM is giving me lots of info and it's hard to verify any of it.

What I know:

About pitches (center to center) worth testing 300µm and 200µm (if room for one go 300µm, less variables).
You can add 100µm if you want but I don't believe in it, PCB fab shops don't usually go that small so it can't be easy.
If you've got lots of space add 250µm and 150µm.

Assuming my PCB rules translate to ICs, never use a square will fuck up the ball.
A square with extremely big corner radius value works, but the best is a plain circle.
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message-1526037058781712444

2026-07-13T01:26:27.211+00:00 — namibj

Content

btw, if one can grow pillars from the exposed top metal (aluminium), and those are of a sufficiently "solderable" surface, then dipping the pillars onto a sheet of silver/copper low-temperature sintering paste followed by carefully placing it onto a PCB with matching pad geometry, and then applying the sintering heat/pressure (something like 200C for 30 minutes seemd to be realistic to expect, iirc), is also something to keep in mind/consider-as-option; in theory that can also be printed as it's basically like _very_ fine solder paste with consistancy depending on what particular variety (iirc the relevant ones for ourt die sizes are all conveniently available in the more-liquid-y forms, though; it's just larger dies that need the drier stuff to not have issues with letting the fumes escape during the pressing).
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message-1526037237559595170

2026-07-13T01:27:09.835+00:00 — Jorropo (@jorropo)

Reply/reference

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the pilars thing is something I've found when searching earlier
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message-1526037237668642816

2026-07-13T01:27:09.861+00:00 — namibj

Content

we don't get circles but we do get 45 degree lines
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message-1526037257079754794

2026-07-13T01:27:14.489+00:00 — Jorropo (@jorropo)

Content

😄
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message-1526037260204773376

2026-07-13T01:27:15.234+00:00 — Jorropo (@jorropo)

Content

ok
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message-1526037287308103916

2026-07-13T01:27:21.696+00:00 — Jorropo (@jorropo)

Content

well give me an 8 sided circle
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message-1526037372221919477

2026-07-13T01:27:41.941+00:00 — namibj

Content

https://jlcpcb.com/capabilities/flex-pcb-capabilities look at flex for the 0.33oz 2L

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message-1526037405499527188

2026-07-13T01:27:49.875+00:00 — namibj

Content

(that's the only FPC on special offer)
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message-1526037913152917555

2026-07-13T01:29:50.909+00:00 — namibj

Content

100um is not sustainable on laminated PCB (it is I think on build-up organic substrates like you know from modern desktop/server CPUs) for more than like 2 rows due to issues with PCB via manufacturing and layer thickness minimums; it's otherwise not _that_ much of a problem tho.
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message-1526038139985203330

2026-07-13T01:30:44.99+00:00 — namibj

Content

Try to figure out how large the pad will need to be, I'm now realy off to eat my dinner before it's properly cold 😄
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message-1526038178044313771

2026-07-13T01:30:54.064+00:00 — Jorropo (@jorropo)

Content

Ok so for he sizes, according to the LLM you want the aluminium diameter to be bigger than the passivation hole by like 15µm
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message-1526038217671970867

2026-07-13T01:31:03.512+00:00 — Jorropo (@jorropo)

Reply/reference

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yeah go eat 😄
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message-1526038245463429180

2026-07-13T01:31:10.138+00:00 — Jorropo (@jorropo)

Content

for 300µm a good openning diameter is 150µm
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message-1526038312505180241

2026-07-13T01:31:26.122+00:00 — Jorropo (@jorropo)

Content

basically it's really close the enig pad size on the PCB
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message-1526038411276718140

2026-07-13T01:31:49.671+00:00 — namibj

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let those things be my concern; your concern is the size and shape and spacing of the exposed aluminium only.
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message-1526038499634053321

2026-07-13T01:32:10.737+00:00 — Jorropo (@jorropo)

Content

@namibj sure when your dinner is finished I'll have a wrietup 😄
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message-1526039168621215957

2026-07-13T01:34:50.236+00:00 — Jorropo (@jorropo)

Content

- pitch, opening diameter
- 500µm, 300µm (easiest, remove process error)
- **300µm, 180µm** (worth testing)
- 250µm, 150µm
- **200µm, 120µm** (might work)
- 150µm, 90µm ¿not sure?
- *100µm, 60µm* probably does not work without a HDI lithographic carrier
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message-1526039838996824144

2026-07-13T01:37:30.066+00:00 — Jorropo (@jorropo)

Content

According to the LLM you want the aluminium to be ~15µm bigger than the opening size,
it also says you want maximum vias on the aluminium to prevent delaminiation when reflow
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message-1526039960300552322

2026-07-13T01:37:58.987+00:00 — Jorropo (@jorropo)

Content

it also says the pads can't be used by a flying probe otherwise the scratches will cause issues for the zincate process
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message-1526040269865353236

2026-07-13T01:39:12.793+00:00 — Jorropo (@jorropo)

Content

I've assumed a 1µm layer of enig, it grows in all directions thus I've knocked down the opening sizes of a couple
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message-1526040353499513003

2026-07-13T01:39:32.733+00:00 — Jorropo (@jorropo)

Content

I doubt it matters
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message-1526040861635252315

2026-07-13T01:41:33.882+00:00 — Jorropo (@jorropo)

Content

~~For the opening diameter I've taken a simple 50% of the pitch~~ nvm I've changed my mind, at worst balls touch and no problem
some manufacturers prefer a bit bigger because it's easier
the bottleneck is the bulge of balls, you don't want them touching
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message-1526041438104719441

2026-07-13T01:43:51.323+00:00 — Jorropo (@jorropo)

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message-1526041439136514099

2026-07-13T01:43:51.569+00:00 — Jorropo (@jorropo)

Content

I guess here is still some unused room on he wafer.

It might be worth making a tile testing a whole range of pitches and opening %.
Altho that the kind of optimization analysis you do once you know the process work.
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message-1526043289399328799

2026-07-13T01:51:12.706+00:00 — Jorropo (@jorropo)

Content

I've listed 60% opening to part pitch to opening diameter which is what the TI chip I have in front of me uses
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message-1526044254827319357

2026-07-13T01:55:02.882+00:00 — Jorropo (@jorropo)

Content

wait nvm
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message-1526044291565228032

2026-07-13T01:55:11.641+00:00 — Jorropo (@jorropo)

Content

I got it wrong, it's a 400µm pitch part not a 300µm
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message-1526044845418745918

2026-07-13T01:57:23.69+00:00 — Jorropo (@jorropo)

Content

yeah 60% is too big.
50% would be ok
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message-1526045040693084301

2026-07-13T01:58:10.247+00:00 — Jorropo (@jorropo)

Content

if I read [this](https://www.nxp.com/docs/en/package-information/SOT2152-1.pdf) correctly nxp uses 50µm⌀ openings on their 300µm ICs

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message-1526045114265501760

2026-07-13T01:58:27.788+00:00 — Jorropo (@jorropo)

Content

seems really small
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message-1526045231995158528

2026-07-13T01:58:55.857+00:00 — namibj

Content

Assuming (afaik reasonable to do given the pricing fits what I recall as typical for these low end processes) the 2000$/wafer for buying extra undieced wafer(s) is around the marginal per-wafer cost, that'd be a reference price level to compare the plating to, if it's done wafer-at-once in a way that doesn't break the ability to wire-bond dies that expect to get wire-bonded.
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message-1526045558991618130

2026-07-13T02:00:13.819+00:00 — namibj

Content

(one of the enig siblings is suited to wire bonding on top of the solderable plating; ofc it can't make a thick bump but doing it wafer-at-once means that one doesn't need to hold onto hundreds of tiny dies during the plating process steps)
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message-1526045684644446359

2026-07-13T02:00:43.777+00:00 — Jorropo (@jorropo)

Content

Then you're back to the factory issue
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message-1526045715514785873

2026-07-13T02:00:51.137+00:00 — namibj

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that's a typical redistribution layer look
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message-1526045782287843488

2026-07-13T02:01:07.057+00:00 — Jorropo (@jorropo)

Content

Do you want to try that ?
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message-1526045785014276269

2026-07-13T02:01:07.707+00:00 — namibj

Reply/reference

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you are a factory
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message-1526045806157631489

2026-07-13T02:01:12.748+00:00 — Jorropo (@jorropo)

Content

😄
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message-1526045825724059859

2026-07-13T02:01:17.413+00:00 — Jorropo (@jorropo)

Content

I appreciate the compliment
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message-1526045828391899257

2026-07-13T02:01:18.049+00:00 — Jorropo (@jorropo)

Content

hum
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message-1526045884423471166

2026-07-13T02:01:31.408+00:00 — Jorropo (@jorropo)

Content

I'll accept it in the pick and place departement
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message-1526045923254210631

2026-07-13T02:01:40.666+00:00 — Jorropo (@jorropo)

Content

the enig process is still in developpement :kek:
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message-1526045932943183912

2026-07-13T02:01:42.976+00:00 — Jorropo (@jorropo)

Content

to say the least
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message-1526046038916599858

2026-07-13T02:02:08.242+00:00 — namibj

Content

(like, 2000$ isn't insane amounts of value to risk by messing up the plasting process and failing QA, at least after having dialed in the process)
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message-1526046117492686999

2026-07-13T02:02:26.976+00:00 — Jorropo (@jorropo)

Content

I'm gonna test the process on a single IC
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message-1526046135716806861

2026-07-13T02:02:31.321+00:00 — namibj

Content

yes sure
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message-1526046222543097967

2026-07-13T02:02:52.022+00:00 — Jorropo (@jorropo)

Content

Well here is a gap to processing one IC and a wafer
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message-1526046231519035442

2026-07-13T02:02:54.162+00:00 — Jorropo (@jorropo)

Content

size gap
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message-1526046243338453003

2026-07-13T02:02:56.98+00:00 — Jorropo (@jorropo)

Content

¯\_(ツ)_/¯
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message-1526046328185163866

2026-07-13T02:03:17.209+00:00 — namibj

Content

I mean once the testing is over and we'd think about replacing the wafer.space 1.5$/chip COB wire bonding add-on with a flip-chip option.
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message-1526046365669392426

2026-07-13T02:03:26.146+00:00 — Jorropo (@jorropo)

Content

❤️
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message-1526046430970777670

2026-07-13T02:03:41.715+00:00 — Jorropo (@jorropo)

Content

How many chips on one wafer ?
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message-1526046449903734805

2026-07-13T02:03:46.229+00:00 — Jorropo (@jorropo)

Content

doing some math
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message-1526046538541957281

2026-07-13T02:04:07.362+00:00 — Jorropo (@jorropo)

Content

I suspect sputtering would be the cheapest, we need like 20µm resolution lihographic capability
this sounds doable with an opensource DMD maskless device
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message-1526046570640969779

2026-07-13T02:04:15.015+00:00 — namibj

Content

full slot is 3.93 × 5.12 mm = 20.12 mm²
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message-1526046610994364576

2026-07-13T02:04:24.636+00:00 — namibj

Content

(that's full die area, not usable-for-transistors)
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message-1526046644280365066

2026-07-13T02:04:32.572+00:00 — namibj

Content

full wafer is 200mm
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message-1526046681630642287

2026-07-13T02:04:41.477+00:00 — namibj

Content

why'd we need litho?
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message-1526046757081845830

2026-07-13T02:04:59.466+00:00 — Jorropo (@jorropo)

Content

unlike enig sputtering coats the passivation layer
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message-1526046842532528259

2026-07-13T02:05:19.839+00:00 — namibj

Content

so don't?
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message-1526046848262082693

2026-07-13T02:05:21.205+00:00 — Jorropo (@jorropo)

Content

so you develop a posiive mask over the opening after sputtering
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message-1526046911319244871

2026-07-13T02:05:36.239+00:00 — Jorropo (@jorropo)

Content

to remove the excess metal
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message-1526047016785022977

2026-07-13T02:06:01.384+00:00 — Jorropo (@jorropo)

Content

the standard way to make that positive is with litho
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message-1526047028390662316

2026-07-13T02:06:04.151+00:00 — namibj

Content

or is it not enough to turn the exposed shiny aluminium pads into solderable surfaces and then solder like the LGA it turned into?
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message-1526047109172691014

2026-07-13T02:06:23.411+00:00 — Jorropo (@jorropo)

Content

well that the goal indeed
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message-1526047189590085732

2026-07-13T02:06:42.584+00:00 — Jorropo (@jorropo)

Content

(I don't understand the question)
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message-1526047221026521170

2026-07-13T02:06:50.079+00:00 — Jorropo (@jorropo)

Reply/reference

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Content

d or r ?
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message-1526047722212163584

2026-07-13T02:08:49.571+00:00 — namibj

Content

https://www.circuitinsight.com/pdf/board_level_reliability_comparison_smta.pdf

Reactions

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message-1526047759269101639

2026-07-13T02:08:58.406+00:00 — namibj

Reply/reference

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Content

d

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message-1526048100882448385

2026-07-13T02:10:19.853+00:00 — Jorropo (@jorropo)

Reply/reference

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Content

The conclusion from the extract is that both are fine ?
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message-1526048130682851520

2026-07-13T02:10:26.958+00:00 — Jorropo (@jorropo)

Content

Do you want to skip the balls ?
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message-1526048208378265620

2026-07-13T02:10:45.482+00:00 — Jorropo (@jorropo)

Content

it looks to me like the process for LGA and BGA is identical up until the balls
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message-1526048480517165177

2026-07-13T02:11:50.365+00:00 — namibj

Reply/reference

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https://discord.com/channels/1361349522684510449/1361349523724570941/1521779301597450271 you see the shiny squares (iirc about or even exactly 40 um squares) along the edges of the die, extending from the same-width structures that ripple through the stripe-y ring that encloses the inner content's grid?
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message-1526048558581678180

2026-07-13T02:12:08.977+00:00 — Jorropo (@jorropo)

Content

?

Attachments

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message-1526048659349966919

2026-07-13T02:12:33.002+00:00 — Jorropo (@jorropo)

Content

the yellow on the chip except the edge is the passivation layer ?
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message-1526048931904229578

2026-07-13T02:13:37.984+00:00 — Jorropo (@jorropo)

Content

wait no I get it, that the square in question

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message-1526049137726980157

2026-07-13T02:14:27.056+00:00 — namibj

Reply/reference

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message-1526049175349887006

2026-07-13T02:14:36.026+00:00 — namibj

Content

this one also very clearly btw.
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message-1526049225090011236

2026-07-13T02:14:47.885+00:00 — Jorropo (@jorropo)

Content

You are talking about the squares right
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message-1526049251745075300

2026-07-13T02:14:54.24+00:00 — Jorropo (@jorropo)

Content

not the rectangles between the squares ?
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message-1526049652820938772

2026-07-13T02:16:29.864+00:00 — Jorropo (@jorropo)

Content

@namibj btw how was dinner ?
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message-1526049690242650284

2026-07-13T02:16:38.786+00:00 — namibj

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I'm talking about the silvery vey very mirror shiny squares around the very outside edge of the die (technically there's like about half or third of square size gap to the edge, and there's for these dies from Run1 at least an omnipresent narrow (about iirc 1/5th the width of the squares) shiny ring around the entire die on the outside)
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message-1526049748434554881

2026-07-13T02:16:52.66+00:00 — namibj

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tasty
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message-1526049763869458644

2026-07-13T02:16:56.34+00:00 — Jorropo (@jorropo)

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nice
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message-1526049800514965564

2026-07-13T02:17:05.077+00:00 — namibj

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yeah
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message-1526049802822094979

2026-07-13T02:17:05.627+00:00 — Jorropo (@jorropo)

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ok I see it indeed
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message-1526050062470348820

2026-07-13T02:18:07.532+00:00 — Jorropo (@jorropo)

Content

TIL you can buy 5µm 50k DPI masks for reasonable amount of money, so the sputtering option looks very interesting
I only need cleaning + a single chemical bath
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message-1526050147749073047

2026-07-13T02:18:27.864+00:00 — namibj

Content

the edge is the sealring which for dies marked as "wire bonding" has a mandatory exposed strip of metal, which in thse dies is very very close to the squares, which the wire bonding machine doesn't care about but any simple ACF bonding would very much care about.
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message-1526050159421689867

2026-07-13T02:18:30.647+00:00 — Jorropo (@jorropo)

Content

well I also need to get a vastly outdated stepper
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message-1526050248269500556

2026-07-13T02:18:51.83+00:00 — Jorropo (@jorropo)

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hum
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message-1526050342197006518

2026-07-13T02:19:14.224+00:00 — namibj

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well, we don't need litho to build up solderable plating on the aluminium base.....
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message-1526050436799271012

2026-07-13T02:19:36.779+00:00 — Jorropo (@jorropo)

Content

with sputter you get a single pad
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message-1526050491438600272

2026-07-13T02:19:49.806+00:00 — Jorropo (@jorropo)

Content

IC sized pad
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message-1526050593641074708

2026-07-13T02:20:14.173+00:00 — Jorropo (@jorropo)

Content

if feaures aren't too big I guess you could align a stencil to block the sputtering beam
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message-1526053096239661107

2026-07-13T02:30:10.839+00:00 — Jorropo (@jorropo)

Content

@namibj I don't know what is your involvement with the project seems high
given NXP seems to get by with 50µm openings for balls on the IC
do you know where I could some existing open source design ICs ? (that havn't been wire bonded)
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message-1526053184274038935

2026-07-13T02:30:31.828+00:00 — Jorropo (@jorropo)

Content

would be enough to try to replicate NXP's setup
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message-1526053216624709632

2026-07-13T02:30:39.541+00:00 — Jorropo (@jorropo)

Content

given it already has 40µm squares
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message-1526053318621663272

2026-07-13T02:31:03.859+00:00 — Jorropo (@jorropo)

Content

(well the surface from 40µm to 50µm is a big jump but worth trying)
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message-1526055053008572418

2026-07-13T02:37:57.369+00:00 — namibj

Content

> Dense arrays of 60 microns pitch die, with 30 microns pads and 30 microns spacing, were used.
uhhhhhh https://www.techblick.com/post/fine-pitch-direct-die-attach-without-thermal-compression-sunray-scientific

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message-1526055629066735668

2026-07-13T02:40:14.712+00:00 — namibj

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if you can deal with the surrounding edge that's like iirc 7 um or so spaced from the square, you could use "any" of the Run 1 dies; I'm not sure who'd most conveniently be able to send you some, but we can see about that in a few days after the tapeout for Run2 closes.

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message-1526055763016155166

2026-07-13T02:40:46.648+00:00 — Jorropo (@jorropo)

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what is the edge made off ?
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message-1526055931631243386

2026-07-13T02:41:26.849+00:00 — namibj

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should only have a notable but brute-force-able yield impact; we don't care if the prototypes have say 1% failure per joint
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message-1526056125634449539

2026-07-13T02:42:13.103+00:00 — Jorropo (@jorropo)

Content

¯\_(ツ)_/¯
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message-1526056151937056850

2026-07-13T02:42:19.374+00:00 — namibj

Content

even for 100 pads that's still over 30% yield
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message-1526056189035675759

2026-07-13T02:42:28.219+00:00 — namibj

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the same
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message-1526056246933717173

2026-07-13T02:42:42.023+00:00 — Jorropo (@jorropo)

Content

wrong question mb
is it passivated ?
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message-1526056305276616798

2026-07-13T02:42:55.933+00:00 — Jorropo (@jorropo)

Content

enig will coat all the Al
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message-1526056362348515338

2026-07-13T02:43:09.54+00:00 — namibj

Content

as far as the top layher litho is concerned the edge is just a very narrow pad that encloses the entire circuit on the die
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message-1526056403796492420

2026-07-13T02:43:19.422+00:00 — namibj

Reply/reference

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Content

I _know_
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message-1526056637897379861

2026-07-13T02:44:15.236+00:00 — namibj

Content

mask the line under a microscope with a micro manipulator of sorts, and paint it with passivation or such, is what I'd try with Run1 silicon.
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message-1526056906378969349

2026-07-13T02:45:19.247+00:00 — Jorropo (@jorropo)

Reply/reference

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My current plan is
0. chemical cleaning
1. sputtering
2. spin coating a mask
3. contact mask negative
4. UV
5. chemical bath (remove unwanted sputtered)
6. party

just because that is way less chemical bath compared to enig
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message-1526057008132788300

2026-07-13T02:45:43.507+00:00 — namibj

Content

hmmmm
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message-1526057036251664496

2026-07-13T02:45:50.211+00:00 — namibj

Content

I guess ok for testing at least
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message-1526057082418364516

2026-07-13T02:46:01.218+00:00 — namibj

Content

sputtering isn't easy tho, relatively speaking
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message-1526057089288634530

2026-07-13T02:46:02.856+00:00 — Jorropo (@jorropo)

Content

I'm vastly underequiped tho
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message-1526057116375187456

2026-07-13T02:46:09.314+00:00 — Jorropo (@jorropo)

Reply/reference

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sure but I hate chemistry
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message-1526057136155660379

2026-07-13T02:46:14.03+00:00 — Jorropo (@jorropo)

Content

hate is a strong word
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message-1526057146939211967

2026-07-13T02:46:16.601+00:00 — Jorropo (@jorropo)

Content

maybe not hate
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message-1526057174692790313

2026-07-13T02:46:23.218+00:00 — namibj

Content

(not that electroless plating baths are particularly stable)

Reactions

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message-1526057212685062214

2026-07-13T02:46:32.276+00:00 — Jorropo (@jorropo)

Content

terrible
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message-1526057216187306024

2026-07-13T02:46:33.111+00:00 — Jorropo (@jorropo)

Content

I know
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message-1526057319618842681

2026-07-13T02:46:57.771+00:00 — namibj

Content

I don't think you can get by with a single material layer though, to go from the aluminium to something decent for soldering.
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message-1526057368545136720

2026-07-13T02:47:09.436+00:00 — Jorropo (@jorropo)

Content

Ti → Ni → Au
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message-1526057379136012471

2026-07-13T02:47:11.961+00:00 — Jorropo (@jorropo)

Content

is the classical afait
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message-1526057462396883004

2026-07-13T02:47:31.812+00:00 — Jorropo (@jorropo)

Content

the Au is flashed and gets disolved into the tin
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message-1526057478381637742

2026-07-13T02:47:35.623+00:00 — Jorropo (@jorropo)

Content

from my understanding
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message-1526058080163332126

2026-07-13T02:49:59.099+00:00 — Jorropo (@jorropo)

Content

@namibj btw did I do the math right is there ~1561 ICs on a single wafer ?
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message-1526058284585324544

2026-07-13T02:50:47.837+00:00 — namibj

Content

yeah
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message-1526058383952576613

2026-07-13T02:51:11.528+00:00 — namibj

Content

though some are chopped into two for smaller projects/customers
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message-1526058389258633280

2026-07-13T02:51:12.793+00:00 — Jorropo (@jorropo)

Content

Is wafer.space combining 1k different projects on a single MPW run ?
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message-1526058454895169648

2026-07-13T02:51:28.442+00:00 — Jorropo (@jorropo)

Content

or is the same customer design repeated many times to reach 1k ICs per customer with less wafers ?
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message-1526058492472070204

2026-07-13T02:51:37.401+00:00 — namibj

Content

no, there's a reticle that gets filled and the facvtory stamps that across the die
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message-1526058584641638521

2026-07-13T02:51:59.376+00:00 — Jorropo (@jorropo)

Content

ah hum
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message-1526058724962074765

2026-07-13T02:52:32.831+00:00 — namibj

Content

https://discord.com/channels/1361349522684510449/1499473530394378403/1499476068174790868
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message-1526058795573313537

2026-07-13T02:52:49.666+00:00 — Jorropo (@jorropo)

Reply/reference

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wow
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message-1526059057864114399

2026-07-13T02:53:52.201+00:00 — Jorropo (@jorropo)

Content

afait that reticle is repeated like 40 times on a single wafer ?
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message-1526059062125662209

2026-07-13T02:53:53.217+00:00 — namibj

Content

afaik Run2 has one more row and one more column of half-sized slots so only 18 full-sized slots on the reticle.
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message-1526059114776756276

2026-07-13T02:54:05.77+00:00 — Jorropo (@jorropo)

Content

(I didn't counted the edges weirdness)
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message-1526059236209983519

2026-07-13T02:54:34.722+00:00 — namibj

Reply/reference

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Content

sounds about right; as you could see at the edge it's not quite fully reticle-strict-oriented.
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message-1526059245584519269

2026-07-13T02:54:36.957+00:00 — Jorropo (@jorropo)

Reply/reference

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Content

that seems correct, that makes 25 wafers per MPW
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message-1526059345324937357

2026-07-13T02:55:00.737+00:00 — namibj

Reply/reference

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message-1526059451948335167

2026-07-13T02:55:26.158+00:00 — Jorropo (@jorropo)

Reply/reference

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I thought they always printed half designs because it improved reliability of complete designs
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message-1526059706475614228

2026-07-13T02:56:26.842+00:00 — Jorropo (@jorropo)

Content

Attachments

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message-1526059892790661172

2026-07-13T02:57:11.263+00:00 — namibj

Reply/reference

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Content

it's not worth the litho at the very very edges because there's too much edge close by anyways so the chips aren't too usable anyways; maybe they expose some filler pattern to help the chemical-mechanical-polishing stay more well behaved though, not sure
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message-1526060027000131635

2026-07-13T02:57:43.261+00:00 — Jorropo (@jorropo)

Content

@namibj after some more searching I don't know how NXP is using 50µm opening or if I'm reading that diagram correctly.
For 300µm pitch an octogon between 180µm and 100µm diameter should be workable
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message-1526060195028013196

2026-07-13T02:58:23.322+00:00 — Jorropo (@jorropo)

Content

I would use 150µm
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message-1526060258152284210

2026-07-13T02:58:38.372+00:00 — namibj

Content

https://discord.com/channels/1361349522684510449/1419841819138854993/1454341922326843432

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