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Thread: Tons of DRC issues

130 Discord messages from ℹ️ - Information/⁉️-questions/threads/tons-of-drc-issues.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1498100763388284938

Messages: 130

message-1498100763388284938

2026-04-26T23:17:35.358+00:00 — The Computer Guy (@thecomputerguy)

Content

While working on https://github.com/MidstallSoftware/aegis/pull/21, I've seen all of these DRC issues and I am stuck:

```
26-Apr-2026 21:54:06 | ERROR   | Violated rules are : {'M1.2b', 'V2.2a', 'M2.1', 'M4.2a', 'M1.2a', 'V1.1', 'M1.1', 'M3.2a', 'V2.1', 'M2.2a', 'M3.1', 'V1.3c', 'V1.2a'}
```

I'm not sure what I am doing wrong but it would be nice to have some help. I've been running my DRC via `nix build .#checks.aarch64-linux.luna-1-gds-verify` and producing the GDS via `nix build .#luna-1-tapeout`.
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message-1498132580933963959

2026-04-27T01:24:01.252+00:00 — namibj

Content

Try opening the gds in KLayout; `KLAYOUT_PATH=$PDK_ROOT/$PDK/libs.tech/klayout klayout`, then just open the file via the menu; you can then trigger the DRC by clicking run full drc in

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message-1498132820806336522

2026-04-27T01:24:58.442+00:00 — namibj

Content

you might have to hit the rightmost one of these that says sky130a for me here (the drop-down button on the right edge of it) and select the option that isn't just "default".

Attachments

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message-1498133010359390369

2026-04-27T01:25:43.635+00:00 — namibj

Content

then maybe press that full Torx-shaped button with the T in the shape once after seelcting, before the DRC option in the main menu bar becomes available.
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message-1498133275640856626

2026-04-27T01:26:46.883+00:00 — namibj

Content

You can then press on any individual line of the report and the offending segments show up in the layout view window as black lines; you can adjust colors and such on the right side of the report window.
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message-1498153948282884097

2026-04-27T02:48:55.625+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Content

Huh? What would that do?
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message-1498154049357353061

2026-04-27T02:49:19.723+00:00 — The Computer Guy (@thecomputerguy)

Content

Shouldn't I have this information in the log I got from KLayout running through the GDS?
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message-1498156541860384909

2026-04-27T02:59:13.982+00:00 — namibj

Reply/reference

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Content

Oh yeah if you have the log file you should be able to open it and view, like this:

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message-1498156904327942285

2026-04-27T03:00:40.401+00:00 — The Computer Guy (@thecomputerguy)

Content

Huh?
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message-1498156910854275083

2026-04-27T03:00:41.957+00:00 — namibj

Content

run DRC (custom), unselect all (make sure you're not gonna overwrite your nice log), top right file -> open, select the log, enjoy.
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message-1498157170967973898

2026-04-27T03:01:43.973+00:00 — namibj

Content

I'm assuming you don't want to search for the offending coordinates/shapes in the text files by hand, to try and make sense of what exactly the DRC log entries are blaming/complaining about.
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message-1498157189561581618

2026-04-27T03:01:48.406+00:00 — The Computer Guy (@thecomputerguy)

Content

Do I have to use the GUI for this?
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message-1498157599772639275

2026-04-27T03:03:26.208+00:00 — namibj

Content

The DRC complaints only narrow down to which cell, and I'm not sure if they blame specific instances of a cell or only "all".
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message-1498158783422140486

2026-04-27T03:08:08.412+00:00 — namibj

Content

The engine itself only really operates on (polygonal, for efficciency, but it might as well be literal as the outcome wouldn't change, just the runtime/memory usage) rasterized/bitmap-view of the GDS layers at the native coordinate quantization "pixel size", as the rules rely heavily on performing boolean operations between/across layers to determine things.

It unfortunately doesn't know what source shape caused the problem, only what edge/edge-pair (as in, location) caused the problem. If there are edges at that location from more than one layer you have to guess based on the rule's description which of the options it was.
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message-1498158940691632290

2026-04-27T03:08:45.908+00:00 — namibj

Reply/reference

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Content

Technically you can reason about the files without the GUI.
Have you found the file yet?
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message-1498159520197902347

2026-04-27T03:11:04.073+00:00 — The Computer Guy (@thecomputerguy)

Content

I think so
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message-1498159713446002869

2026-04-27T03:11:50.147+00:00 — The Computer Guy (@thecomputerguy)

Content

```
result-4/netlist.spice
result-4/v2spice.log
result-4/raw_netlist.spice
result-4/drc_output/contact.drc
result-4/drc_output/metal1.drc
result-4/drc_output/luna_1_metal4.lyrdb
result-4/drc_output/luna_1_via4.lyrdb
result-4/drc_output/metaltop.drc
result-4/drc_output/via1.drc
result-4/drc_output/layers_def.drc
result-4/drc_output/drc_run_2026_04_26_21_21_23.log
result-4/drc_output/luna_1_geom.lyrdb
result-4/drc_output/luna_1_metal5.lyrdb
result-4/drc_output/luna_1_via2.lyrdb
result-4/drc_output/luna_1_metal2.lyrdb
result-4/drc_output/metal5.drc
result-4/drc_output/metal2.drc
result-4/drc_output/luna_1_metal3.lyrdb
result-4/drc_output/luna_1_via3.lyrdb
result-4/drc_output/via2.drc
result-4/drc_output/luna_1_contact.lyrdb
result-4/drc_output/geom.drc
result-4/drc_output/via4.drc
result-4/drc_output/luna_1_via1.lyrdb
result-4/drc_output/luna_1_metal1.lyrdb
result-4/drc_output/via3.drc
result-4/drc_output/luna_1_metaltop.lyrdb
result-4/drc_output/metal3.drc
result-4/drc_output/metal4.drc
result-4/drc.log
result-4/gds_check.log
```
I think it might be one of the `.drc` files?
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message-1498159802705252524

2026-04-27T03:12:11.428+00:00 — namibj

Content

given it's named "output", I'd presume so.
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message-1498159998109352036

2026-04-27T03:12:58.016+00:00 — namibj

Content

can you show the first few hundred bytes or so of one of them, I'd start with the `rc_run_2026_04_26_21_21_23.log`?
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message-1498160212169982122

2026-04-27T03:13:49.052+00:00 — The Computer Guy (@thecomputerguy)

Content

That file is quite small
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message-1498160222575792228

2026-04-27T03:13:51.533+00:00 — The Computer Guy (@thecomputerguy)

Content

Attachments

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message-1498160266171388074

2026-04-27T03:14:01.927+00:00 — namibj

Content

This is one of the drc result formats that I've encountered; I'm not sure if this is the one you'd have.

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message-1498160441099292842

2026-04-27T03:14:43.633+00:00 — The Computer Guy (@thecomputerguy)

Content

Oh, that's the `.lyrdb` files I have
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message-1498160464335470612

2026-04-27T03:14:49.173+00:00 — namibj

Content

yeah I know it's not the same PDK
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message-1498160529242591403

2026-04-27T03:15:04.648+00:00 — The Computer Guy (@thecomputerguy)

Content

Yeah
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message-1498160575287660584

2026-04-27T03:15:15.626+00:00 — The Computer Guy (@thecomputerguy)

Content

Though I plan on using Sky130 in the future heh
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message-1498160853340651672

2026-04-27T03:16:21.919+00:00 — The Computer Guy (@thecomputerguy)

Content

There's a lot of V1.1 violations for Via1
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message-1498160941240422400

2026-04-27T03:16:42.876+00:00 — The Computer Guy (@thecomputerguy)

Content

> V1.1 : Min/max Via1 size . : 0.26µm
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message-1498161025814626466

2026-04-27T03:17:03.04+00:00 — namibj

Reply/reference

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Content

this XML refers to the generator. This XML itself is a clean DRC result.
You should see content in the XML if you have that format.
I'd try grepping for a fragment of the XML that you'd expect to show up, like maybe the lydrc file as a string.
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message-1498161254781681694

2026-04-27T03:17:57.63+00:00 — The Computer Guy (@thecomputerguy)

Content

Huh the `.drc` files I have are python
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message-1498161526844952678

2026-04-27T03:19:02.495+00:00 — namibj

Reply/reference

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Content

if you violate that you're somehow creating vias that are not the size they should be, like, there's no room for options there, vias have exactly that size, and thus it's either some generator script thinking it knows better (unlikely unless you wrote something like that for this AegisFPGA), or somewhere a misconfig about coordinate system scaling.
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message-1498161812766589050

2026-04-27T03:20:10.664+00:00 — The Computer Guy (@thecomputerguy)

Content

Shouldn't OpenROAD have done that automatically in the way the PDK wanted?
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message-1498161823508201492

2026-04-27T03:20:13.225+00:00 — namibj

Reply/reference

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Content

See if you find `</report-database>` at the end of any of those files
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message-1498161929007534121

2026-04-27T03:20:38.378+00:00 — namibj

Reply/reference

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Content

sure, should, but vias don't tend to just malform themselves.
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message-1498162021336743936

2026-04-27T03:21:00.391+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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```
$ grep -r "</report-database>" result-4/drc_output
result-4/drc_output/luna_1_metal4.lyrdb:</report-database>
result-4/drc_output/luna_1_via4.lyrdb:</report-database>
result-4/drc_output/luna_1_geom.lyrdb:</report-database>
result-4/drc_output/luna_1_metal5.lyrdb:</report-database>
result-4/drc_output/luna_1_via2.lyrdb:</report-database>
result-4/drc_output/luna_1_metal2.lyrdb:</report-database>
result-4/drc_output/luna_1_metal3.lyrdb:</report-database>
result-4/drc_output/luna_1_via3.lyrdb:</report-database>
result-4/drc_output/luna_1_contact.lyrdb:</report-database>
result-4/drc_output/luna_1_via1.lyrdb:</report-database>
result-4/drc_output/luna_1_metal1.lyrdb:</report-database>
result-4/drc_output/luna_1_metaltop.lyrdb:</report-database>
```
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message-1498162088202473522

2026-04-27T03:21:16.333+00:00 — namibj

Content

great, so that's probably the files of interest.
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message-1498162111216488501

2026-04-27T03:21:21.82+00:00 — namibj

Content

`result-4/drc_output/luna_1_via1.lyrdb`?
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message-1498162142732353678

2026-04-27T03:21:29.334+00:00 — namibj

Content

If it's not secret ofc
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message-1498162369195540511

2026-04-27T03:22:23.327+00:00 — The Computer Guy (@thecomputerguy)

Content

Oh, that's 56kb
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message-1498162619826307113

2026-04-27T03:23:23.082+00:00 — namibj

Content

yeah a bunch of your errors
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message-1498162669948244121

2026-04-27T03:23:35.032+00:00 — The Computer Guy (@thecomputerguy)

Content

```
  <category>
   <name>V1.1</name>
   <description>V1.1 : Min/max Via1 size . : 0.26µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.2a</name>
   <description>V1.2a : min. via1 spacing : 0.26µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.2b</name>
   <description>V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.3a</name>
   <description>V1.3a : metal1 overlap of via1 &gt;= 0.0</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.3c</name>
   <description>V1.3c : metal1 (&lt; 0.34um) end-of-line overlap. (Applies to all &lt; 0.34µm wide Metal lines,
                    excluding Metal branches shorter than 0.28µm.) : 0.06µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.3d</name>
   <description>V1.3d : If metal1 overlap via1 by &lt; 0.04um on one side, adjacent metal1 edges overlap. : 0.06µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.4a</name>
   <description>V1.4a : metal2 overlap of via1 &gt;= 0.01 um</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.4b</name>
   <description>V1.4p : metal2 (&lt; 0.34um) end-of-line overlap. (Applies to all &lt; 0.34µm wide Metal lines,
                    excluding Metal branches shorter than 0.28µm.) : 0.06µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>V1.4c</name>
   <description>V1.4c : If metal2 overlap via1 by &lt; 0.04um on one side, adjacent metal2 edges overlap. : 0.06µm</description>
   <categories>
   </categories>
  </category>
```
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message-1498162687727767664

2026-04-27T03:23:39.271+00:00 — namibj

Content

if you open the GDS you can just load it or you can look at it's contents more programmatically
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message-1498162755189080164

2026-04-27T03:23:55.355+00:00 — namibj

Content

yeah that's just the header/legend 😄
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message-1498162761543188532

2026-04-27T03:23:56.87+00:00 — The Computer Guy (@thecomputerguy)

Content

I have the GDS open on my laptop in KLayout
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message-1498162798952452176

2026-04-27T03:24:05.789+00:00 — namibj

Content

you can feed this file in then
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message-1498162800433037343

2026-04-27T03:24:06.142+00:00 — The Computer Guy (@thecomputerguy)

Content

How do I open the lyrdb file?
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message-1498162918691442698

2026-04-27T03:24:34.337+00:00 — namibj

Content

can you show me the menu bar? Or rather, what's teh right most main menu bar name?
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message-1498163096328470661

2026-04-27T03:25:16.689+00:00 — The Computer Guy (@thecomputerguy)

Content

Attachments

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message-1498163177693777921

2026-04-27T03:25:36.088+00:00 — namibj

Content

actually, try "Tools -> Marker Browser"
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message-1498163257574293647

2026-04-27T03:25:55.133+00:00 — The Computer Guy (@thecomputerguy)

Content

Ah cool, that looks promising
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message-1498163364810063914

2026-04-27T03:26:20.7+00:00 — namibj

Content

you might want to point klayout at the PDK path though
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message-1498163442132062258

2026-04-27T03:26:39.135+00:00 — namibj

Content

e.g. `KLAYOUT_PATH=$PDK_ROOT/$PDK/libs.tech/klayout klayout -e`
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message-1498163490077147247

2026-04-27T03:26:50.566+00:00 — namibj

Content

(if using ciel)
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message-1498163494275514442

2026-04-27T03:26:51.567+00:00 — The Computer Guy (@thecomputerguy)

Content

Attachments

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message-1498163714925400196

2026-04-27T03:27:44.174+00:00 — namibj

Content

yeah you select a row possibly after expanding a folded one, and while a row is selected/highlighted, you'll see them highlighted as lines in the layout view window
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message-1498163834630705342

2026-04-27T03:28:12.714+00:00 — namibj

Content

(SerDes? Noice....)
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message-1498163944370470982

2026-04-27T03:28:38.878+00:00 — The Computer Guy (@thecomputerguy)

Content

Cool, I see it

Attachments

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message-1498164061609791579

2026-04-27T03:29:06.83+00:00 — The Computer Guy (@thecomputerguy)

Content

https://github.com/Midstall/aegis/pull/21/changes#diff-297415984077469f4bd6bc71cb8e9dc8615316b804cca6335ca1b89eecaaccf1 I'll have to change something here I think to fix it

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message-1498164471762260028

2026-04-27T03:30:44.618+00:00 — The Computer Guy (@thecomputerguy)

Content

I'm not exactly sure what I need to do to fix this
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message-1498166510063976601

2026-04-27T03:38:50.587+00:00 — The Computer Guy (@thecomputerguy)

Content

Ah, OpenROAD stopped short on iterating. I wonder if increasing the routing iterations would fix a lot of problems.
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message-1498168008424554507

2026-04-27T03:44:47.824+00:00 — namibj

Reply/reference

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auto routing "gave up" before finishing into a state where it passed LVS to the point where it at least thinks it has finished routing the entire netlist it was tasked with?
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message-1498168286720950352

2026-04-27T03:45:54.175+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Idk, I've tried doing LVS but I skipped LVS because it caused the DRC + LVS job to run for like 30 hours
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message-1498168429583138906

2026-04-27T03:46:28.236+00:00 — namibj

Content

LVS comes after DRC (personally; this is not inherently strict but some DRC fails will result in bogus LVS)
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message-1498168702435065968

2026-04-27T03:47:33.289+00:00 — namibj

Content

note you probably want to exempt "casual" LVS from operating at granularity below the standard cell "abstract block with ports and nominal behavior/named-behavior", at least in usual design loop.
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message-1498168836833411194

2026-04-27T03:48:05.332+00:00 — The Computer Guy (@thecomputerguy)

Content

Oh
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message-1498169308776366231

2026-04-27T03:49:57.852+00:00 — namibj

Content

no sadly don't know how
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message-1498169433040883804

2026-04-27T03:50:27.479+00:00 — The Computer Guy (@thecomputerguy)

Content

This is my first design so idk how either lol
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message-1498169491975311370

2026-04-27T03:50:41.53+00:00 — namibj

Content

I'd suggest you tell openroad to not give up so soon; it might have been tuned for tiles that are substantially less packed vs. your FPGA.
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message-1498169537282048010

2026-04-27T03:50:52.332+00:00 — The Computer Guy (@thecomputerguy)

Content

Yeah
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message-1498169652881129502

2026-04-27T03:51:19.893+00:00 — namibj

Reply/reference

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Like I read mention of that yesterday but don't even remember for which tool let alone in what docs.
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message-1498169769935896679

2026-04-27T03:51:47.801+00:00 — namibj

Content

(And I don't need to for my tiny 1x2 analog tile on ttsky26a.)
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message-1498170125138788422

2026-04-27T03:53:12.488+00:00 — namibj

Content

(....can you link the actual analog PLL that is mentioned by the code in your repo? I'd like to look at it this evening a little bit for some dose of inspiration.)
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message-1498170898388095136

2026-04-27T03:56:16.845+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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https://github.com/Midstall/aegis/blob/f375157ff1c4b5b1cfcac49411b3b2164238857a/ip/lib/src/components/analog/pll.dart

Embeds

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message-1498173500140290231

2026-04-27T04:06:37.151+00:00 — namibj

Reply/reference

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No I found that.
But that's not doing PLL.
It's _wrapping,_ sure, but it's not _doing_ PLL.
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message-1498173726364139540

2026-04-27T04:07:31.087+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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:SubaThink:
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message-1498174406768201768

2026-04-27T04:10:13.308+00:00 — namibj

Content

PLL is some sort of oscillating thingy that can be somehow controlled, and is somehow phase-compared to some kind of reference, and what makes it PLL is that these two things (the "controllable oscillator" and the "oscillator [output] phase comparing to reference") are wired into a control _loop._
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message-1498174661538873404

2026-04-27T04:11:14.05+00:00 — namibj

Content

If correctly designed/configured, it then has to actually manage to _lock_ to deserve the title of "Phase-**Locked** Loop".
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message-1498174804552056913

2026-04-27T04:11:48.147+00:00 — namibj

Content

(I don't want to keep you from finishing the FPGA into a functional state in time for the WS Run2 deadline.)
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message-1498176316074364998

2026-04-27T04:17:48.522+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Yeah, I'm just wrapping the one from the PDK for simplicity
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message-1498178400580403261

2026-04-27T04:26:05.507+00:00 — namibj

Content

....there is one in the PDK? (I tried and failed to find one, but maybe I searched wrong)
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message-1498178959760953364

2026-04-27T04:28:18.826+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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`gf180mcu_fd_pr__pll.sym` lol
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message-1498179225218191541

2026-04-27T04:29:22.116+00:00 — namibj

Content

....that's a symbol, not an actual thing. It's just an abstract placeholder for a schematic.
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message-1498179657374367876

2026-04-27T04:31:05.15+00:00 — The Computer Guy (@thecomputerguy)

Content

Oh
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message-1498188906972184626

2026-04-27T05:07:50.426+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) - Dunno if you have any ideas about this?
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message-1498208034319761570

2026-04-27T06:23:50.741+00:00 — Leo Moser (mole99) (@mole99)

Content

The vias are indeed of a fixed size, so the only issues I can think of are that the manufacuring grid is not set correctly (everything is scaled by a factor of 5), or there is some other setup issue.

I suggest checking the wafers.space [gf180mcu-project-template](https://github.com/wafer-space/gf180mcu-project-template) against your custom set up.
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message-1498372713121579118

2026-04-27T17:18:13.227+00:00 — The Computer Guy (@thecomputerguy)

Content

I've been checking what I have vs the template. I might've forgotten about PDN lol
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message-1499070581201440869

2026-04-29T15:31:17.943+00:00 — The Computer Guy (@thecomputerguy)

Content

Hmm, 0 violations in OpenROAD's DRC but KLayout says like 3.5k
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message-1499072923909099723

2026-04-29T15:40:36.488+00:00 — The Computer Guy (@thecomputerguy)

Content

@Tim 'mithro' Ansell which DRC is more believable?
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message-1499074212659466300

2026-04-29T15:45:43.75+00:00 — Leo Moser (mole99) (@mole99)

Content

You need to pass KLayout DRC in order to tape out. OpenROAD only has an abstract view of the cells and routing.
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message-1499074556583874571

2026-04-29T15:47:05.748+00:00 — The Computer Guy (@thecomputerguy)

Content

Oh. Most of my KLayout DRC violations are on metal1, 2.2k.
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message-1499078869523763331

2026-04-29T16:04:14.033+00:00 — The Computer Guy (@thecomputerguy)

Content

I don't think I'll be able to get the early bird deadline. Everything I try to do does not fix the DRC violations. I'm not sure what I am doing wrong and idk how to fix the violations.
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message-1499119206417957025

2026-04-29T18:44:31.098+00:00 — Leo Moser (mole99) (@mole99)

Content

You should be able to buy a slot even if you don't have the design ready yet.
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message-1499119265528287292

2026-04-29T18:44:45.191+00:00 — Leo Moser (mole99) (@mole99)

Content

As for the DRC violations, if you could share your current layout, I can take a quick look to see what's going on.
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message-1499127150933053500

2026-04-29T19:16:05.218+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Like the GDS file?
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message-1499127338074509322

2026-04-29T19:16:49.836+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Cool, hopefully I can do that soon.
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message-1499131175229460530

2026-04-29T19:32:04.685+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Yes
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message-1499134726781272219

2026-04-29T19:46:11.441+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Content

Cool, here you go

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message-1499169625039175820

2026-04-29T22:04:51.834+00:00 — bailey (@bailey8889)

Content

It looks to me like all the metal layers have been removed from the standard cells and merged at the top level. This appears to be result in power shorts and very thin metal1 maybe due to resizing. See screenshot.

I don't think that this will be easy to extract with open source tools.

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message-1499172534367813742

2026-04-29T22:16:25.472+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Content

Fun, lemme try something
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message-1499172766044131498

2026-04-29T22:17:20.708+00:00 — The Computer Guy (@thecomputerguy)

Content

Gonna drop the `pkgs/aegis-tapeout/scripts/drc_repair.py` script
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message-1499242952768225320

2026-04-30T02:56:14.527+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Content

I have this now btw

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message-1499261902562525296

2026-04-30T04:11:32.51+00:00 — bailey (@bailey8889)

Reply/reference

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Content

Looks like the standard cell rows are missing filler cells. Can you confirm?
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message-1499262268196524043

2026-04-30T04:12:59.684+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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I think I see standard cells, what exactly are standard cell rows?
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message-1499262720787218503

2026-04-30T04:14:47.59+00:00 — The Computer Guy (@thecomputerguy)

Content

Ah, sounds like I need to run `filler_placement`?

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message-1499266134938222654

2026-04-30T04:28:21.587+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Content

Cool, I've added that in

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message-1499266295374544906

2026-04-30T04:28:59.838+00:00 — The Computer Guy (@thecomputerguy)

Content

KLayout is getting a little slow
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message-1499267401441742951

2026-04-30T04:33:23.545+00:00 — bailey (@bailey8889)

Content

Better, but still not seeing power grid connections to all the macros or cell rows.
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message-1499267615250579498

2026-04-30T04:34:14.521+00:00 — The Computer Guy (@thecomputerguy)

Content

Weird, I did do the PDN stuff
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message-1499267748579250197

2026-04-30T04:34:46.309+00:00 — bailey (@bailey8889)

Content

Are you using librelane or OpenROAD directly?
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message-1499267818406023178

2026-04-30T04:35:02.957+00:00 — The Computer Guy (@thecomputerguy)

Content

OpenROAD directly and orchestrated through Nix.
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message-1499267881194622986

2026-04-30T04:35:17.927+00:00 — The Computer Guy (@thecomputerguy)

Content

The OpenROAD scripts are generated from Dart.
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message-1499268039579799582

2026-04-30T04:35:55.689+00:00 — The Computer Guy (@thecomputerguy)

Content

Do I need to do `define_pdn_grid`?
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message-1499272276917616772

2026-04-30T04:52:45.949+00:00 — The Computer Guy (@thecomputerguy)

Content

```
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_325
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_326
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_327
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_328
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_329
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_33
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_330
aegis-top-pnr-luna_> [INFO PDN-0001] Inserting grid: macro_grid - io_fabric/lut_fabric/tile_331
```
This seems promising
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message-1499273853401170030

2026-04-30T04:59:01.812+00:00 — bailey (@bailey8889)

Content

TBH, what you're are attempting is beyond my level of experience.

What I've seen in the past, is that hard macros have their own power grid with the top metal layer one lower than the max. (metal4 in this case). Since metal 4 is a vertical layer, you should be able to have the power grid for the macros, connect directly to metal1 through a metal1-via-metal2-via2-metal3-via3-metal4 stack at the metal1 power rail for each cell row. How many metal4 power rails you use depends on the width of the macro. Since you need metal4 routing over the macros, you'll want to be careful where you place the power rails.

Some of the macros currently have metal5, and while that may be doable, I suggest the top metal routing layer be limited to metal4.

Next you need to design your top level power gird so that both power and ground horizontal metal5 power lines intersect with all the hard macros. The top power grid will be vertical metal4 and horizontal metal5. In this case, metal4 power rails are not generally routed over macros that already have metal4 power rails.

Another consideration is the power connections for the standard cell rows placed between the macros. Normally, the metal1 power rails in these standard cells is connected to metal4 power rails at the top level, but in your case, these rows are narrow and may not intersect with the power grid. You may want to consider setting these regions as no cell placement.

Also noticed that you are using fill cells and not fillcap cells. fillcap cells add capacitance between the power and ground lines for better stability.
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message-1499274045911334992

2026-04-30T04:59:47.71+00:00 — The Computer Guy (@thecomputerguy)

Content

Alright. Thank you for the help though.

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message-1499307985976037497

2026-04-30T07:14:39.652+00:00 — Leo Moser (mole99) (@mole99)

Content

I can only repeat what bailey said. The power connections are missing, and decap cells would be better than fillcaps.
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message-1499308004586295327

2026-04-30T07:14:44.089+00:00 — Leo Moser (mole99) (@mole99)

Content

Independent of that, your layout is missing a padring and a sealring. This is your interface to the outside world.
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message-1499308036181852180

2026-04-30T07:14:51.622+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1499308055945543824

2026-04-30T07:14:56.334+00:00 — Leo Moser (mole99) (@mole99)

Content

Here is your layout alongside the gf180mcu project template.
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message-1499308094658838608

2026-04-30T07:15:05.564+00:00 — Leo Moser (mole99) (@mole99)

Content

I would recommend implementing the gf180mcu project template and comparing the output with your setup.
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message-1499484127995625615

2026-04-30T18:54:35.182+00:00 — The Computer Guy (@thecomputerguy)

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Content

Cool, will see what that can do for me. Thanks. I'm not really familiar with LibreLane or any of this stuff so this has been quite new for me. Hopefully I can integrate some of this trial and error into my asix and harbor repos which help out for ASIC/FPGA design/dev.

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message-1501433182111928441

2026-05-06T03:59:25.895+00:00 — The Computer Guy (@thecomputerguy)

Content

Switched to trying LibreLane, it's been running for 12 hours and it's at PP.5a for klayout lol
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message-1501605887188664331

2026-05-06T15:25:41.994+00:00 — The Computer Guy (@thecomputerguy)

Content

Total time is 14 hours and 21 minutes. I had to reduce the tile count to fit correctly. I'm going to try to scale it back up to cram as much as I can.
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message-1501611294447374467

2026-05-06T15:47:11.185+00:00 — Leo Moser (mole99) (@mole99)

Content

That runtime will hopefully be reduced considerably with the KLayout DRC update that should soon be merged.
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message-1501611558122422404

2026-05-06T15:48:14.05+00:00 — The Computer Guy (@thecomputerguy)

Content

Great, yeah it was 8 hours of KLayout lol
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message-1501733854019326062

2026-05-06T23:54:11.664+00:00 — Tim 'mithro' Ansell (@mithro_)

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That is always the way.
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message-1501734114854961183

2026-05-06T23:55:13.852+00:00 — The Computer Guy (@thecomputerguy)

Reply/reference

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Yeah, I found that out the hard way lol.
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message-1501734186992664608

2026-05-06T23:55:31.051+00:00 — The Computer Guy (@thecomputerguy)

Content

The good thing is I think soon I should be ready to submit to wafer.space
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message-1505716776795901983

2026-05-17T23:40:54.453+00:00 — The Computer Guy (@thecomputerguy)

Content

LibreLane gave me a good DRC and everything
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message-1505716883691802675

2026-05-17T23:41:19.939+00:00 — The Computer Guy (@thecomputerguy)

Content

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