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Thread: F_t - F_max

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Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1493774686801100860

Messages: 5

message-1493774686801100860

2026-04-15T00:47:18.325+00:00 — namibj

Content

Does anyone have numbers? I know they're inherently theoretical but it's still some sense of scale...
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message-1493863853728075887

2026-04-15T06:41:37.377+00:00 — Lofty (@ravenslofty)

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Content

my chess move generator is heavily combinational, but I had to use a multicycle path to get it to pass typical and fast corners at 60MHz, *with* the 9T standard cell library
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message-1493969987369566258

2026-04-15T13:43:21.609+00:00 — Max Vallone (@mavmaster)

Content

My team simulated an F_t of ~65GHz if I recall correctly. We are only doing RF work up to 600MHz on this node atm though.

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message-1494019716363190282

2026-04-15T17:00:57.925+00:00 — namibj

Content

Asking because I'm looking about porting the MCML digital PLL core (sans the digital scaffold around said core for now at least, kinda a bit rushed) I'm expecting to get into TTSKY26a over to the wafer.space Run 2 after the TT deadline.
If anyone happens to be interested in letting such a small bit live at an edge of a mostly-other-things chip of wafer.space Run2, and could be willing to offfer a bit of scan chain state and like about 2~4 IO pads, it _could_ maybe even do a multi-gigabit TX test, but we're talking like 10% of a half-tile of Run2 even with the transmitter's NRZ PA.

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message-1494021180259172454

2026-04-15T17:06:46.945+00:00 — Max Vallone (@mavmaster)

Content

Dm me but I fear I cant promise the space until our project is complete (will also be rushed)
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