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Thread: Running LVS for padframe

16 Discord messages from ℹ️ - Information/⁉️-questions/threads/running-lvs-for-padframe.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1444423485182050415

Messages: 16

message-1444423485182050415

2025-11-29T20:23:14.958+00:00 — LuighiV (@luighiv)

Content

Hi everyone,

We are trying to run LVS checks for the PADs in  gf180mcu using netgen. Not sure if others are using the same for it or maybe can suggest another tool to do it. However, while we achieved passing successfully for other circuits, for the pads (provided by GF) seems that it is no passing. We are trying with a simple test case of 4 pads, vdd, vss, asig5v and fills. What we found is that in all the pads there is an extra net which is not present (not matched) in schematic.

Digging into the issue we identified that the extracted spice netlist from layout is creating diodes with just one pin exposed while the another is connected to substrate. Not sure if netgen understands VSUBS as a global net, but the anode (substrate) is being considered as floating net during the comparison. The layout also seems to have just one pin exposed, so the extraction might be OK but might require something in netgen configuration to make it work.

Have anyone faced this issue?, or can provide a guidance to configure the LVS tool properly?

Thank you!
cc: @peterkinget

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message-1444447752103661629

2025-11-29T21:59:40.643+00:00 — bailey (@bailey8889)

Content

@LuighiV I think you may have run into the issue that magic does not handle devices that are formed by layers on different hierarchies.

I have LVS pass on the gf I/O cells by flattening before extracting via `gds flatglob`ing the following.
```
*Bondpad*
*CLAMP_COR*
*FILL*
*METAL_RAIL*
*NMOS_*
*POWER_RAIL_COR*
*_BASE*
*comp018green*
*diode_nd2ps_06v0_*[A-Z]*
*diode_pd2nw_06v0_*[A-Z]*
*mim_*_*[A-Z]*
*moscap_*
*nmos_*_*[A-Z]*
*nmos_4T_metal_stack*
*nmos_clamp_*
*pmos_6p0_esd_*
*power_via*
*ppolyf_u_*[A-Z]*
*top_route*
*_CDNS_*
```
(edited to include `*_CDNS_*`)

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message-1444448730903347392

2025-11-29T22:03:34.007+00:00 — LuighiV (@luighiv)

Content

Hi @bailey  that's great you have already managed to make it work, let me try the same here, thanks for the advice

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message-1444479930304823418

2025-11-30T00:07:32.524+00:00 — LuighiV (@luighiv)

Content

Hi @bailey I have used the configuration you have shared, and now the difference is in the 3rd terminal of poly resistors. In layout is connected to VSS  while in the netlist is connected to VDD. Do you know how to fix this? I'm using the spice model shared in the Chipathon repository

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message-1444607472374517832

2025-11-30T08:34:20.923+00:00 — bailey (@bailey8889)

Content

@LuighiV The actual layout looks like it's over nwell, so `DVDD` should be the proper connection.

Can you share the extracted netlist?
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message-1444696337508470814

2025-11-30T14:27:28.022+00:00 — LuighiV (@luighiv)

Content

sure, the extrated one is attached here

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message-1444697426312040569

2025-11-30T14:31:47.613+00:00 — bailey (@bailey8889)

Content

@LuighiV magic extracts devices at the level the occur in the hierarchy. It has problems, for example, if you add a nwell at a parent hierarchy. For the I/O cells to extract correctly, I had to `gds flatglob` all the subcells. The final extracted netlist should only include subckts for the top level io cells.
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message-1444699327535775837

2025-11-30T14:39:20.9+00:00 — LuighiV (@luighiv)

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Content

Hi @bailey  thanks for the heads up, I was using the set of instruction you shared before, I guessed that way will flatten he internal hierarchies, do you why it keeps extracting the subhierarchies?

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message-1444700957580722247

2025-11-30T14:45:49.533+00:00 — bailey (@bailey8889)

Content

@LuighiV Looks like I missed one.
Try adding
```
gds flatglob *_CDNS_*
```
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message-1444705541732569139

2025-11-30T15:04:02.48+00:00 — LuighiV (@luighiv)

Content

oh, got it, let me try again, thanks 👍

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message-1444720425719431291

2025-11-30T16:03:11.099+00:00 — LuighiV (@luighiv)

Content

Hi @bailey  I re run again but seems it has the same issue, and it keeps extracting the internal hierarchies

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message-1444730684710191264

2025-11-30T16:43:57.033+00:00 — bailey (@bailey8889)

Content

@LuighiV I can't understand why. Are you sure that `sample_pads_layout.spice` is the most recent file? Can you check the time stamp?
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message-1444738126206468287

2025-11-30T17:13:31.224+00:00 — LuighiV (@luighiv)

Content

@bailey yes, indeed I deleted first just to be sure it is created again and not using and old one

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message-1444793152576688319

2025-11-30T20:52:10.533+00:00 — bailey (@bailey8889)

Content

@LuighiV
```
gfs flatglob *_CDNS_*
```
`gfs` 😆
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message-1444796605952688148

2025-11-30T21:05:53.882+00:00 — LuighiV (@luighiv)

Content

oh... sorry, my mistake going to try again, thanks for noticing

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message-1444800415777558669

2025-11-30T21:21:02.215+00:00 — LuighiV (@luighiv)

Content

It worked now! 🙂, thank you so much @bailey  for your help!

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