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Thread: Metal Fill

31 Discord messages from ℹ️ - Information/⁉️-questions/threads/metal-fill.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1444531273728262376

Messages: 31

message-1444531273728262376

2025-11-30T03:31:33.75+00:00 — Buck (@buck_042)

Content

When I use LibreLane to generate a small digital module, everything looks normal but there is no metal fill, whereas I noticed that the top design in the template does have metal fill. What is causing this difference?

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message-1444535127051862158

2025-11-30T03:46:52.454+00:00 — Marcus (@bigturtle8)

Content

First thought would be different hardening strategies in the config.json, but could be wrong (https://librelane.readthedocs.io/en/latest/usage/caravel/index.html)
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message-1444536417509183488

2025-11-30T03:52:00.123+00:00 — Buck (@buck_042)

Content

I don't know, I don't see any configuration related to metal fill in template's config.yaml. And the fillers are successfully inserted, but no metal fill.
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message-1444552932862329045

2025-11-30T04:57:37.69+00:00 — Buck (@buck_042)

Content

I see, the template uses the chip flow, which calls some KLayout scripts to insert metal fill. In my case, I didn’t explicitly set any flow, so I assume it’s using the default classic flow, which doesn’t seem to run the KLayout density/metal-fill steps.

If I want to add metal fill for a small standalone digital block, what is the recommended approach?

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message-1444592695732473906

2025-11-30T07:35:37.897+00:00 — Leo Moser (mole99) (@mole99)

Content

Normally, you wouldn't run metal fill for a standalone block.

One way to do that, however, is to add the `KLayout.Filler` step after one the StreamOut steps in the Classic flow. You can do this directly in the config.
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message-1444596035371532418

2025-11-30T07:48:54.129+00:00 — Buck (@buck_042)

Content

Thanks! May I ask how to do that directly in the config?
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message-1444623255473230096

2025-11-30T09:37:03.907+00:00 — Leo Moser (mole99) (@mole99)

Content

You can find the relevant docs here: https://librelane.readthedocs.io/en/latest/usage/writing_custom_flows.html
By using `substituting_steps` and placing a "+" before the step ID. You're welcome!
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message-1444741493037203487

2025-11-30T17:26:53.939+00:00 — Buck (@buck_042)

Content

Thank you!
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message-1444923623063162992

2025-12-01T05:30:37.121+00:00 — Buck (@buck_042)

Content

@Leo Moser (mole99) Hi mole99, may I ask a further question?  Can I ask why only this much metal is filled here? It seems the density requirement is still not met. Is this normal? Thank you very much!

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message-1444932627403640873

2025-12-01T06:06:23.923+00:00 — Leo Moser (mole99) (@mole99)

Content

The filler generation script was made to fill an entire chip, so it adheres to rules such as leaving a 26um spacing from the edges to meet the 10um distance to the sealring etc.
I assume this is what leads to what we see here.
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message-1444938557826531413

2025-12-01T06:29:57.846+00:00 — Buck (@buck_042)

Content

I see, thanks! I think this works. We do this because we will integrate this module to our analog module.

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message-1444943456861556796

2025-12-01T06:49:25.867+00:00 — Buck (@buck_042)

Content

Oh I see, actually we don't need fill the digital module at this stage, like we can fill all during the top level?
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message-1444954697034371073

2025-12-01T07:34:05.733+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Yes, that is the usual approach. The fill for the entire chip is added at the end.

If you do an analog top-level integration you can add the fill manually:

```
klayout -b -zz -r ${PDK_ROOT}/${PDK}/libs.tech/klayout/tech/drc/filler_generation/fill_all.rb -rd input=chip_top.gds -rd output=chip_top_filled.gds
```
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message-1445070331613282518

2025-12-01T15:13:35.165+00:00 — Buck (@buck_042)

Reply/reference

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Content

Hi Leo, thank you! If we want to do top-level integration, may I ask how to obtain a clean pad ring without any logic cells? My current idea is to follow the template, remove everything in the Verilog except VDD/VSS and the pad instances, and remove the metal fill step in the flow, and then rerun the synthesis and PnR flow. Is this the correct approach?
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message-1445071219425546413

2025-12-01T15:17:06.836+00:00 — Leo Moser (mole99) (@mole99)

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Content

There is an easier approach :)
You customize the flow to only generate the padring + sealring and then streamout the GDS. I already did this for the MOSbius group: https://github.com/wafer-space/gf180mcu-project-template/pull/29
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message-1445073706736029870

2025-12-01T15:26:59.857+00:00 — Buck (@buck_042)

Reply/reference

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Content

Thank you, this is very helpful! So with this, can we still configure our IO plan? Like, by changing the pad instances in Verilog and the IO placement inside the config.yaml.
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message-1445074364893495347

2025-12-01T15:29:36.774+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, it still uses the LibreLane configuration. It simply rearranges the flow slightly.
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message-1445074513514725437

2025-12-01T15:30:12.208+00:00 — Leo Moser (mole99) (@mole99)

Content

There were XOR errors between magic and KLayout (?) but I haven't had the time to look into it. Maybe you could see what the difference between the two layouts is.
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message-1445075481916473525

2025-12-01T15:34:03.093+00:00 — Buck (@buck_042)

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Content

Thank you, this is helpful!

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message-1445076061003059221

2025-12-01T15:36:21.158+00:00 — Buck (@buck_042)

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Content

I will try to do that. But to be honest, we are trying to catch up with the DDL now. 😂  See what we can help. Really thank you, Leo!
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message-1445076397491224620

2025-12-01T15:37:41.383+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, just make sure to use the correct layout then if there is a difference between magic and KLayout 😁
No worries! Looking forward to your design.
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message-1445177037902970930

2025-12-01T22:17:35.927+00:00 — Evansika (@xintingjiang_36756)

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Content

I also encountered this when generating the empty pad frame today. Now I am looking into the differences between the two layouts
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message-1445183613833576509

2025-12-01T22:43:43.751+00:00 — Evansika (@xintingjiang_36756)

Content

In my case, klayout gds is correct because I found that the only mismatch is that the magic gds has these extract tieh and tiel cells at the origin and I don't know why

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message-1445317188952260709

2025-12-02T07:34:30.541+00:00 — Leo Moser (mole99) (@mole99)

Content

Right, that's the difference! It seems that magic exports the instances even if they were not placed. There are some constants that are used in `chip_top`, but we stream out the padring before any of those stdcells can be placed and routed.
So the KLayout version is the correct one to use.
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message-1445798440511733761

2025-12-03T15:26:49.854+00:00 — Buck (@buck_042)

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Hi Leo, may I ask a question? We are doing analog top-level integration now, so after we connect our design to the pad ring, is this the last step before DRC and LVS? Or any other step we should run? Thank you!
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message-1445799020521066628

2025-12-03T15:29:08.139+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Hi Buck, sure thing. You should also generate the fill before doing DRC and LVS, but other than that, that should be it.

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message-1445799414202503268

2025-12-03T15:30:42+00:00 — Buck (@buck_042)

Reply/reference

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Thanks!
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message-1447774602863448105

2025-12-09T02:19:23.674+00:00 — Buck (@buck_042)

Content

@Leo Moser (mole99) Hi Leo, sorry to bother you again, after we do the top level analog style integration and do the fill step, is there any script or command that we can use to tun the drc check in librelane environment? Before we used chipathon environment. Thanks!

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message-1447835974397591605

2025-12-09T06:23:15.788+00:00 — tnt (@246tnt)

Content

If you run the pre-check, it will run DRC.
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message-1447851345557061686

2025-12-09T07:24:20.558+00:00 — Leo Moser (mole99) (@mole99)

Content

As Sylvain said, you can run the precheck.
This can be done either through the online platform (https://platform.wafer.space/) or locally (https://github.com/wafer-space/gf180mcu-precheck).
Alternatively, you can run the DRC deck directly: https://github.com/wafer-space/gf180mcu/blob/main/gf180mcuD/libs.tech/klayout/tech/drc/gf180mcu.drc
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message-1448027290272530514

2025-12-09T19:03:29.047+00:00 — Buck (@buck_042)

Content

Thanks!
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