Thread: iverilog sim

2 Discord messages from ℹ️ - Information/⁉️-questions/threads/iverilog-sim.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1438935324691660852

Messages: 2

message-1438935324691660852

2025-11-14T16:55:15.532+00:00 — tnt (@246tnt)

Message ID: 1438935324691660852
Author ID: 596068704471482370
Nickname: tnt
User name: 246tnt
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Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/iverilog-sim/2025-11/2025-11.json
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Content

Is there some special trick define to use the verilog models ?

```
sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9975: error: Net MGM_P0 is not defined in this context.
sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9977: error: Net MGM_D0 is not defined in this context.
sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9979: error: Net IQ1 is not defined in this context.
sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9979: error: Output port expression is not valid.
sim/gf180mcuD/gf180mcu_fd_sc_mcu7t5v0.v:9979:      : Output port of gf180mcu_fd_sc_mcu7t5v0__udp_n_iq_ff is Q.
```

This is what I'm getting when just including `gf180mcu_fd_sc_mcu7t5v0.v` and `primitives.v` and using `-DUSE_POWER_PINS=1 -DFUNCTIONAL=1 -DUNIT_DELAY=#1` like for sky130

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message-1438936462988021841

2025-11-14T16:59:46.923+00:00 — tnt (@246tnt)

Message ID: 1438936462988021841
Author ID: 596068704471482370
Nickname: tnt
User name: 246tnt
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Archive source: https://discord.wafer.space/wafer-space/Information/questions/iverilog-sim/2025-11/2025-11.json

Content

Nevermind ... the models use implicit wire definition everywhere so gotta use `default_nettype wire` ... 🤢

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