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Thread: Do we need OCD IO pads for digital 3v3 design

10 Discord messages from ℹ️ - Information/⁉️-questions/threads/do-we-need-ocd-io-pads-for-digital-3v3-design.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1513432126190522469

Messages: 10

message-1513432126190522469

2026-06-08T06:38:57.093+00:00 — Jason Yang (@.pogeg)

Content

For our design, we're planning on using a pure 3v3 digital design (no analog, 3v3 SCL and SRAM). In that case, is switching from foundry provided IO pads to OCD pads necessary?
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message-1513434109140140182

2026-06-08T06:46:49.865+00:00 — Leo Moser (mole99) (@mole99)

Content

No, it is not necessary. In this case, you can keep using the foundry pad cells.

The OCD cells add levelshifters between IO and core, which allows you to have IO voltage > core voltage. For example, you could have a 3.3V core voltage and a 5V IO voltage.

If you run everything at 3.3V, then you can simply use the FD cells.

Currently, there are no IO cells with 3.3V transistors (normal gate oxide). Both the FD and OCD cells use 5V transistors (thick gate oxide).
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message-1513434177914146906

2026-06-08T06:47:06.262+00:00 — Leo Moser (mole99) (@mole99)

Content

As you probably know, the 3.3V SCL and SRAM are yet to be silicon verified.
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message-1513444673346342982

2026-06-08T07:28:48.568+00:00 — tnt (@246tnt)

Content

Also to note the foundry cells although designed for 5V provide more than acceptable performance running at 3.3V. ( > 100 MHz without issues ).

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message-1522993158810636470

2026-07-04T15:51:04.905+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Sounds like there might be some interest in a pure 3.3V I/O library to try to hit higher performance?  It's a bit trickier than my hack method of downsizing the 5V SRAMs to 3.3V (although that worked surprisingly well) because a lot of the I/O pad device sizing is based on ESD targets.  And it cannot just be "silicon verified" by doing a functional test---it needs to be zap-tested.  The dual voltage I/O library does not need zap testing because nothing touching the pad itself has been modified, only internal core-facing circuits.  Its ESD characteristics should be exactly like the original 5V I/O library.
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message-1523001736501919884

2026-07-04T16:25:09.986+00:00 — tnt (@246tnt)

Content

I mean inputs of the dual one reached 188 MHz (and probably limit is tt infra and not pad) and outputs would be fine above 100 M given measured rise/fall time.
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message-1523005910845362286

2026-07-04T16:41:45.227+00:00 — Leo Moser (mole99) (@mole99)

Content

But outside of TT, people might still be interested. (I definitely am 😁)

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message-1523006175275122689

2026-07-04T16:42:48.272+00:00 — BreakingTaps (@polyfractal)

Content

is there a disadvantage to using the OCD cells if everything is 3v3? Worse timing or power or something? I didn't realize you could use the FDs
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message-1523014445142511873

2026-07-04T17:15:39.962+00:00 — RebelMike (@rebelmike)

Content

Hmm, I could see it either way - splitting the power domains maybe reduces noise, joining them maybe increases stability through more pins?  Not sure which is preferable.
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message-1523032263225380965

2026-07-04T18:26:28.124+00:00 — tnt (@246tnt)

Reply/reference

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Content

I meant that more than likely the IO themselves already go way above what we measured in TT and getting non trivial logic in gf180 meeting 200 MHz is quite the challenge, so it's not like the IO are a giant limiting factor ATM.
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