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Thread: CUP Rules allowed?

28 Discord messages from ℹ️ - Information/⁉️-questions/threads/cup-rules-allowed.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1501987023433502851

Messages: 28

message-1501987023433502851

2026-05-07T16:40:11.956+00:00 — BreakingTaps (@polyfractal)

Content

Section 9.3. details Circuit-Under-Pad rules (https://mithro-gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_3.html), are these allowed to be used in designs? From prior discussions I know that WLCSP is not allowed because bumping applies to the whole wafer, but can we CUP rules on non-bumped wafers?

Context: I want to open up a bunch of vias in the passivation layer at a size/pitch that is smaller than the PAD rules (https://mithro-gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_2.html), and allow active elements underneath or nearby. This is for @Tim 'mithro' Ansell's gate array / structured ASIC idea 🙂
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message-1501996139719819494

2026-05-07T17:16:25.448+00:00 — Leo Moser (mole99) (@mole99)

Content

There was a previous discussion about pad openings. I can't find it right now, but from what I can remember, we decided to set the minimum pad opening to 40um, as that is what is stated in the guidelines. @Tim 'mithro' Ansell?

As for CUP, we actually wanted to disable the CUP rules during submission (if possible), as this would simplify things slightly because a number of rules would not be applied. However, I don't yet know if we can simply disable/waive the CUP rules, or if they are automatically activated if you have devices under/near your pads.
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message-1502003900859940904

2026-05-07T17:47:15.848+00:00 — BreakingTaps (@polyfractal)

Content

hm I'm reading the DRC closer and now I've confused myself 😅

So it looks like the PAD rules have a min 40um size and the whole opening in the passivation has to be top metal (with some top metal overlapping the passivation). But the CUP rules seem to allow wires passing through the opening.

Do you know if you can do something similar with PAD? I'd be fine with giant PAD openings as long as I dont need the top metal to fill the whole area. Was hoping for like 5um pitch between M5 lands that I connect myself

Edit: Hmm I see that the DRC says 40 for wedge/ball, but 4um for gold bump. Are the PAD rules entirely defined by the user project or something? I dont fully understand how to apply the DRC here since it differs based on end use?
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message-1502010396561903618

2026-05-07T18:13:04.544+00:00 — BreakingTaps (@polyfractal)

Content

I think I found the prior discussion about pad sizes etc: https://discord.com/channels/1361349522684510449/1486057912555012167/1486057912555012167
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message-1502018565182853191

2026-05-07T18:45:32.095+00:00 — Leo Moser (mole99) (@mole99)

Content

I feel the same way every time I read the docs 😄
The gf180mcu PDK is better quality than, say, the sky130 PDK, but the documentation leaves a lot to be desired...

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message-1502018591728341142

2026-05-07T18:45:38.424+00:00 — Leo Moser (mole99) (@mole99)

Content

It's possible that 40um is the minimum pad opening, but it could also be that a smaller opening is allowed. We only have the guideline and this note:

> These are just default numbers for DRC purpose only, however, these are VARIABLE and the customer is advised to use the appropriate value acceptable to their assembly house.

However, then you have rules for Gold bump with 4um, so physically smaller openings are possible.

Afaik, topmetal needs to cover the whole opening, at least that's the only actual rule: https://mithro-gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_1.html
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message-1502018814118854897

2026-05-07T18:46:31.446+00:00 — namibj

Content

CUP is basically just about wedge bonding messing with FEOL structures I think due to strain-induced bandgap effecs, and bonding mechanics being a little different if you have certain structures under the pad which would necessitate tuning the bonding process parameter to account for that difference.
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message-1502019075541307412

2026-05-07T18:47:33.774+00:00 — namibj

Content

the DRC _rules_ are the ones in the codified DRC list about enclosures and critical dimensions and spacings and density
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message-1502019095762047027

2026-05-07T18:47:38.595+00:00 — BreakingTaps (@polyfractal)

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it really does feel like reading tea leaves sometimes 😂

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message-1502019153131864175

2026-05-07T18:47:52.273+00:00 — namibj

Content

the bond pads are mostly suggestions to be compatible with generic bond houses
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message-1502019546511311018

2026-05-07T18:49:26.062+00:00 — Leo Moser (mole99) (@mole99)

Content

Basically, our reticle is handled as a single project during submission, so we need to decide which wire bonding option to choose for the DRC. The more red lights go on during the submission process, the longer it will take to get it done. That's why Tim would like to make the DRC rules more restrictive, if doing so makes the submission process easier.

I'm not sure if "Gold bump" is a separate switch in the proprietary DRC deck and can be used alongside wedge type, for example. Maybe @Tim 'mithro' Ansell could find this out?

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message-1502019808462508052

2026-05-07T18:50:28.516+00:00 — namibj

Content

c.f. e.g. Propeller 2 on iirc on semi 130 had to have the factory test voltages on GPIOs reduced as the original ones caused latch up damage; note this was testing with voltages way outside the absolute maximum ratings, like +30% or so
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message-1502020383258312775

2026-05-07T18:52:45.558+00:00 — BreakingTaps (@polyfractal)

Content

suppose there's also always an option to post-fab etch back the SiN and oxide myself 🫠
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message-1502020667422544063

2026-05-07T18:53:53.308+00:00 — Leo Moser (mole99) (@mole99)

Content

That would make a great video 😄
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message-1502116235561795665

2026-05-08T01:13:38.528+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

That would be super cool!
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message-1502116439354773625

2026-05-08T01:14:27.116+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - I do have limited access to the proprietary DRC decks and can run tests.
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message-1502119483274301604

2026-05-08T01:26:32.843+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But have been distracted with the wire bonding.
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message-1502121811780042942

2026-05-08T01:35:48.002+00:00 — BreakingTaps (@polyfractal)

Content

Sounds good! And yeah no worries, run1 stuff takes precedence 🙂

I'm going to try and build out a thing with the assumption that we can find a non-40um pad opening solution and see how it goes. Would prefer not to etch myself, the wet options aren't particularly pleasant or repeatible (hot phosphoric for the SiN, HF for the oxide but both are angry towards aluminum). Also don't really have the facilities for etching stuff anymore, just a dingy shed 🙁
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message-1502122539273420891

2026-05-08T01:38:41.45+00:00 — namibj

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Content

Why'd you have issues with minimum litho dimensional openings in the SiN that have minimum top metal expansion underneath?
Essentially bond pads so tiny no relevant wire bond house will want them, but large though for the litho to not cause problems?
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message-1502122955646439506

2026-05-08T01:40:20.721+00:00 — BreakingTaps (@polyfractal)

Content

hm? not sure I understand the question.

My reading of the DRC so far is that the only way to make SiN openings is with the pad rules, and those have to be 40um at the moment which is far too large for "structured asic" / "gate array" sort of customization after fab. But I've only started looking into it so may be incorrect with that assumption!
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message-1502124394095579137

2026-05-08T01:46:03.674+00:00 — namibj

Content

> Not recommended to use 6k top metal for cu wire bonding.

I just read this; does it mean we could use a wire bonder (or possibly less hyper-specialized thermosonic micro welding robot/head) to form/attach copper pillars to the otherwise "normal" pads which would then be suited for reasonably normal soldering metallurgy? Because the normal aluminum is not really solderable and (electro/-less) chemical plating seems difficult after dicing.
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message-1502125359422902354

2026-05-08T01:49:53.826+00:00 — namibj

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Content

Oh hmmm ok yeah...
>>> Drawn

Pad (1)

Bond pad opening

37

0
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message-1502128099754643587

2026-05-08T02:00:47.172+00:00 — namibj

Content

So, for one, if you convince them you're doing gold bumping, they should let you do 4μm SiN openings.
> PAD.1 [Gold bump] 4
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message-1502129208925880492

2026-05-08T02:05:11.619+00:00 — BreakingTaps (@polyfractal)

Content

yep, if you read up that's one of the pending questions. It's unclear if some parts of the wafer can be designated "gold bump bonding" while others are "wire bonding" or if the entire wafer needs to be the same
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message-1502130866242191360

2026-05-08T02:11:46.754+00:00 — namibj

Reply/reference

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Personally I don't see why glofo should care about it beyond Tim telling them he takes the risk of some bond pads being too small for many/most bond processes.

Because like, this seems like it's an easy DRC for Tim to enforce selectively for different customers of his (different die designs of the MPW reticle)? And note that the existing numbers are already just guidelines for generic bond houses.
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message-1502131466065412167

2026-05-08T02:14:09.763+00:00 — BreakingTaps (@polyfractal)

Content

agreed, it seems like it _should_ be doable! But also elsewhere Tim has expressed interest in No Waivers for DRC (and GF doesn't want to do waivers either) so if they have something hardcoded like a wafer must be all one type it's sunk.

But maybe not an issue! Will have to wait until Tim has some time to investigate I think 🙂
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message-1502249742757789827

2026-05-08T10:04:09.124+00:00 — namibj

Content

yeah, I only have the hope because it should be a bondhouse-provided DRC, not a GF-BEOL-processing DRC, and they do seem to mention that for a bonding option (gold studs) they do very much suggest rather small openings as the DRC limit.
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message-1502857213130309762

2026-05-10T02:18:01.347+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Basically, I'm a small fish for GF and have very little bandwidth with them. Any bandwidth spent on dealing with DRC errors is bandwidth that can't be used on other topics. I would generally say that I can get *one* thing fixed / changed / improved per run on GF's side at most.

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