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Thread: Connecting analog pin in librelane flow

26 Discord messages from ℹ️ - Information/⁉️-questions/threads/connecting-analog-pin-in-librelane-flow.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1514919594467393626

Messages: 26

message-1514919594467393626

2026-06-12T09:09:37.166+00:00 — RebelMike (@rebelmike)

Content

Last night, I thought I'd try taking @Matt Venn's R2R DAC he just submitted on TT 0p3 and add it to TinyQV.  I've got the macro in and the digital inputs + ground are connected OK (could probably do with buffers on the input, but one thing at a time).
However, librelane won't route the output from the DAC to the analog pin - possibly quite sensibly as in general it probably shouldn't touch analog things.  How should I deal with making that connection?  I guess I could add it manually to the gds after the librelane flow has finished, but that seems not ideal.  Can I add a step to the flow to describe the connection?  Or can I just tell the router to connect it somehow?
My repo is here, see the `dac` branch: https://github.com/MichaelBell/ws02-tinyQV/tree/dac

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message-1514920434838278186

2026-06-12T09:12:57.526+00:00 — Matt Venn (@mattvenn)

Content

Interested to see how you solve it!
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message-1514920931372568767

2026-06-12T09:14:55.909+00:00 — Tholin (@tholin)

Content

This is an issue I encountered last run as well, give me a minute to remember the fix
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message-1514921351830569092

2026-06-12T09:16:36.154+00:00 — Tholin (@tholin)

Content

Librelane does not like that the pad’s layout does not have a port named "PAD". That’s it.
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message-1514921441546600500

2026-06-12T09:16:57.544+00:00 — Tholin (@tholin)

Content

That’s all I did. Copy the files for the analog pad and define a port named "PAD" in magic
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message-1514921493803569152

2026-06-12T09:17:10.003+00:00 — Tholin (@tholin)

Content

https://github.com/AvalonSemiconductors/ws-submission-2025/tree/main/macros/Analog/AnalogPad

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message-1514921765514514543

2026-06-12T09:18:14.784+00:00 — Tholin (@tholin)

Content

Its not even different electrically. The analog pad just provides a straight connection to the outside, the ports "ASIG5V" and "PAD" are electrically shorted, but LibreLane needs "PAD" to exist.
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message-1514921884645593150

2026-06-12T09:18:43.187+00:00 — Tholin (@tholin)

Content

Otherwise it goes "whoa, this is useless!" and optimizes it out, since all it sees is a cell with only an input and no output (I *believe*)
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message-1514922646452699259

2026-06-12T09:21:44.816+00:00 — Leo Moser (mole99) (@mole99)

Content

The issue is that OpenROAD's detailed router does not route any pins with the `SPECIAL` attribute. This makes sense for power supplies, as they are handled by a dedicated pdngen call.
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message-1514922755739357195

2026-06-12T09:22:10.872+00:00 — Leo Moser (mole99) (@mole99)

Content

Here you can see that ASIG5V has SPECIAL set to True.

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message-1514922797451972631

2026-06-12T09:22:20.817+00:00 — Leo Moser (mole99) (@mole99)

Content

Looking at the LEF for `gf180mcu_fd_io__asig_5p0.lef`, I don't see the `SPECIAL` attribute set for ASIG5V. However, OpenROAD probably sets it when making the bondpad a BTerm (top-level pin) with [`place_io_terminals`](https://openroad.readthedocs.io/en/latest/main/src/pad/README.html#place-io-terminals).
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message-1514923478665400372

2026-06-12T09:25:03.231+00:00 — Leo Moser (mole99) (@mole99)

Content

I had a similar issue with [HeiChips](https://github.com/FPGA-Research/heichips25-tapeout): in IHP, the bondpads are separate from the I/O cells and [place_bondpad](https://openroad.readthedocs.io/en/latest/main/src/pad/README.html#place-wirebond-pads) also makes the pin SPECIAL. My solution (workaround) was to edit the LEF to add a second port for the core-facing pin of the I/O cell.
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message-1514923683280322560

2026-06-12T09:25:52.015+00:00 — Leo Moser (mole99) (@mole99)

Content

afaik sky130 doesn't have this issue since the I/O cells have separate ports for bondpad and core side.
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message-1514923920610955364

2026-06-12T09:26:48.599+00:00 — RebelMike (@rebelmike)

Content

I noticed that SPECIAL appeared in the def on the OpenROAD.PadRing step, and suspected that might be the reason the router ignored it

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message-1514924100047470736

2026-06-12T09:27:31.38+00:00 — RebelMike (@rebelmike)

Content

But couldn't work out where that was coming from (or even if it was sensible to try and avoid it!)
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message-1514924542030512128

2026-06-12T09:29:16.757+00:00 — Leo Moser (mole99) (@mole99)

Content

iirc @tnt recently found a workaround that doesn't require to edit the LEF file? It involves placing a macro with two ports, which is essentially just a short, next to the core-facing pin of the I/O cell.
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message-1514924914602283099

2026-06-12T09:30:45.585+00:00 — Leo Moser (mole99) (@mole99)

Content

However, Tholin's solution is also fine.
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message-1514926199514730648

2026-06-12T09:35:51.932+00:00 — tnt (@246tnt)

Content

Yesh, I putting a small macro doing the split connection which works better for me than editing the pads in the PDK :
* No need for modifying PDK
* Because the short is in a separate block with just that in it, it actually doesn't mess with full LVS/GDS check, both the "schematic" and "layout" side of that block will have a single 0R resistor in them, no ambiguity.
* That also allowed me to connect all the split `Metal2` traces on the core side, join them together for better connection and bring them to `Metal3` where I needed them, avoiding me to have to deal with via at all when routing them 😅
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message-1514926845458387087

2026-06-12T09:38:25.937+00:00 — tnt (@246tnt)

Content

Ends up looking like this :

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message-1514927236032237628

2026-06-12T09:39:59.057+00:00 — RebelMike (@rebelmike)

Content

Cool, that sounds like a good solution.  I assume I can find that in the TT gf0p3 project?
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message-1514927259918798940

2026-06-12T09:40:04.752+00:00 — tnt (@246tnt)

Content

But the routing is still done manually though ODB scripts, I don't leave it up to the auto-router.
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message-1514927413988032533

2026-06-12T09:40:41.485+00:00 — tnt (@246tnt)

Content

You can't find it anywhere, that's WIP which is not pushed publically anywhere yet.
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message-1514927824119533608

2026-06-12T09:42:19.268+00:00 — tnt (@246tnt)

Content

But the macro is 2 squares of metal with via between them 😅  just positioned right where it needs to be.

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message-1514928573998174288

2026-06-12T09:45:18.053+00:00 — Leo Moser (mole99) (@mole99)

Content

And *if* you want to leave it up to the auto-router, you can now add NDRs directly via the LibreLane config 😉

https://github.com/FPGA-Research/heichips25-tapeout/blob/d555bbc58aad6cc54e0bc9ce81b75936db2df0d8/librelane/config.yaml#L253

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message-1515106828151820589

2026-06-12T21:33:37.155+00:00 — RebelMike (@rebelmike)

Content

Thanks all, I’ve got tnt’s solution working and it’s building with no errors 🙂

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message-1517258713147379743

2026-06-18T20:04:26.518+00:00 — namibj

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Content

If that tooling _looked_ like it could be convinced to route my differential pairs at least approximately like pairs, I'd actually have tried to let it do at least the R part of the PnR for all but the blue and red zone and probably even the P part up to just before the last latch before the MUX between green and blue. In part because _some_ of the early latches are wastefully duplicated between the two to three instances of the bottom section (wired like the top section suggests... except that I forgot to draw a latch pair instead of just a single latch in the top section wherever I drew one; they are both to be preceded by an opposite-phase latch to make the entire green section take inputs all at the nicely same clock.

(Damn, upon further review, I'm annoyingly less confident about the exact nominal bit ordering on the serial side of the MUX structure...)

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