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Thread: 3rd party IPs usage?

9 Discord messages from ℹ️ - Information/⁉️-questions/threads/3rd-party-ips-usage.md.

Category: ℹ️ - Information Parent channel: #⁉️-questions Thread ID: 1498249025344770138

Messages: 9

message-1498249025344770138

2026-04-27T09:06:43.763+00:00 — daobaanhvn

Content

Hello, may I ask whether it is permitted to use IP from third-party vendors (e.g., IO, SRAM, and standard cell IPs)? Can these be taped out in Wafer Space Run 2?
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message-1498261299803586570

2026-04-27T09:55:30.222+00:00 — tnt (@246tnt)

Content

If you have a license for them and if they meet DRC, I don't see why it wouldn't be.
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message-1498367491163033803

2026-04-27T16:57:28.215+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Also, many third party proprietary vendors might not be happy that wafer.space won't sign an NDA or other similar contract with them.
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message-1498524295318601759

2026-04-28T03:20:33.239+00:00 — daobaanhvn

Content

The situation is that the open GF180MCU PDK only provides 5 V standard cell, IO, and SRAM IP.
However, I have a license to use 3.3 V standard cell, IO, and SRAM IP from eMemory.

My understanding is that if the design passes the required DRC checks, it should still be possible to tape it out in Run 2. I will also take full responsibility for the use of the eMemory IP and ensure that it complies with its licensing terms.

Could you please confirm if this understanding is correct? Also, would I need to provide any additional documentation (for example, confirmation from eMemory) before tape-out?

In addition, are there any technical concerns with the padframe or COB packaging if the design uses 3.3 V IPs instead of the 5 V IPs provided in the open PDK?
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message-1498555706801000658

2026-04-28T05:25:22.32+00:00 — tnt (@246tnt)

Content

The bond pads need to have the same dimensions and be at exactly the same position as in the default pad frame.
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message-1498582794815799404

2026-04-28T07:13:00.606+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

Hi @daobaanhvn,

Yes, you are correct that if it passes the **wafer.space DRC checks** (which **could** be different from the checks that eMemory IP has been required to pass) **then** it can be submitted to run #2. wafer.space also don't offer waivers, so if the eMemory IP requires some type of waivers, then that probably won't work.

I would start by running an example design with the IP in it through the tool @ https://github.com/wafer-space/gf180mcu-precheck and see what it says.

You will also be the first person to try this something like, so **expect** it to be rather bumpy it may result in missing the run.

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message-1498583732544864286

2026-04-28T07:16:44.178+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@daobaanhvn - As tnt said, the bond pad locations and dimensions will need to be in exactly the right locations. We have not added a check for that to the precheck tooling.
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message-1498599225448071308

2026-04-28T08:18:17.974+00:00 — daobaanhvn

Content

Thank you, I will start with the precheck and update soon

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message-1507897731845324961

2026-05-24T00:07:14.657+00:00 — Zhekar1998 (@zhekar1998)

Content

Also you must check your license agrements with IP vendors.
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