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#🤪-off-topic

527 Discord messages from ℹ️ - Information/off-topic/channel.md.

Category: ℹ️ - Information Channel ID: 1361349523724570943

Messages: 527

message-1365305410101444648

2025-04-25T12:36:15.916+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Folks, we have a select group of people here in this wafer.space community who might be interested in this, and @Tim 'mithro' Ansell maybe this would be of interest to you for various reasons in your current explorations...Will Salcedo, who worked with us on customer design support for a while at Efabless, is developing GPU & AI acceleration for OpenLane. This is a blurb about their work:

Will Salcedo (https://www.linkedin.com/in/william-salcedo/) and Vamshi Balangala (https://www.linkedin.com/in/vamshibalanaga/) are building enhanced EDA tools on top of OpenLane that improve the speed, scalability, and quality of existing open-source tools. We are using GPU-accelerated approaches and AI to get at least 100x runtime improvements over legacy tools. If you are struggling with closing out designs, we would love to help you get to tapeout faster.

Will and Vamshi are hoping to find people interested in what they're doing, and possibly willing to experiment with what they've done so far, so if anyone would be prepared to at least reach out to them and find out more, please let me know. From what Will was telling me, their approach was to greatly accelerate parts of the resizing/repair, with the intent initially of doing far greater design-space exploration (since for larger designs or extreme timing/density requirements, this can often be a bottleneck). They have also contemplated adapting their work to things like IR drop analysis.

It sounds interesting (and a few of us at Efabless started talking to them late 2024 and it was already showing promise then), and I'm just sharing this around as a favour.
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message-1365305592817651723

2025-04-25T12:36:59.479+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

NOTE: I'm not sure yet whether their offering is intended to be open-source or at least include an open-source option.
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message-1366597369587568681

2025-04-29T02:10:03.061+00:00 — carlfk

Content

Radio Check.. calling laser fans
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message-1366597429276835932

2025-04-29T02:10:17.292+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

check check]
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message-1366597776749891666

2025-04-29T02:11:40.136+00:00 — carlfk

Content

can you help john get onshape box model for cutting
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message-1366597864482144266

2025-04-29T02:12:01.053+00:00 — Andrew Wingate (@anfroholic)

Content

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message-1366597877123514428

2025-04-29T02:12:04.067+00:00 — carlfk

Content

im at Tims.  John is going somewhere tonight where ther might be a laser
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message-1366597889794511028

2025-04-29T02:12:07.088+00:00 — Andrew Wingate (@anfroholic)

Content

I was already doing it
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message-1366597913895239733

2025-04-29T02:12:12.834+00:00 — carlfk

Content

thank you!
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message-1366598103582642267

2025-04-29T02:12:58.059+00:00 — Andrew Wingate (@anfroholic)

Content

nominal material thickness is 1/8" I can change it if needed
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message-1366600378208227381

2025-04-29T02:22:00.372+00:00 — carlfk

Content

if it is less, like cereal box cardboard, that's fine right?  the tabs won't be snug, but I can sitll goop hotglue all over the plance it will mostly work
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message-1366603145764933642

2025-04-29T02:33:00.209+00:00 — Andrew Wingate (@anfroholic)

Content

I mean, I can change the thickness, so if it's as thick as cereal box, it's fine. tab sizes will just auto-change too
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message-1366610973825171577

2025-04-29T03:04:06.564+00:00 — carlfk

Content

in case John is short on time and grabs whatever material is handy, wnated to make sure thinner is ok
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message-1366611132063944745

2025-04-29T03:04:44.291+00:00 — carlfk

Content

thicker I will have to turn the holes into notches - no biggie
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message-1366611801395167262

2025-04-29T03:07:23.872+00:00 — Andrew Wingate (@anfroholic)

Content

just lmk, it's all parametric
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message-1366612404661780542

2025-04-29T03:09:47.702+00:00 — digshadow

Content

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message-1366612471133114428

2025-04-29T03:10:03.55+00:00 — digshadow

Content

Experimenting with laser dicing. 355 NM mopa fiber
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message-1366660104514048061

2025-04-29T06:19:20.233+00:00 — digshadow

Content

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message-1366660210869014611

2025-04-29T06:19:45.59+00:00 — digshadow

Content

We ran a bunch more tests. Maybe slightly better results with the 355 but not enough to justify investments so far
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message-1366660331497193554

2025-04-29T06:20:14.35+00:00 — digshadow

Content

I did get a lot better with the software options and might be able to improve my 1064 nanometer flow. Some evidence also suggest that I don't have my existing 355 nanometer fiber laser setup ideally, so I might also give that another pass
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message-1367361848927846462

2025-05-01T04:47:49.139+00:00 — carlfk

Content

@Tim 'mithro' Ansell see die sorting robot in  https://discord.com/channels/1270929620224704544/1270933607011057776

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message-1367492511773491241

2025-05-01T13:27:01.589+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

I assume this is wafer dicing? What are the lines here?
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message-1367547582716317891

2025-05-01T17:05:51.525+00:00 — digshadow

Content

The lines were resolution tests
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message-1367547689419407531

2025-05-01T17:06:16.965+00:00 — digshadow

Content

Basically trying different parameters if we made it through the wafer
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message-1367703927587471360

2025-05-02T03:27:07.047+00:00 — Andrew Wingate (@anfroholic)

Content

Working on some camera type stuff

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message-1367712703120015411

2025-05-02T04:01:59.297+00:00 — Andrew Wingate (@anfroholic)

Content

More camera stuff

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message-1384635852902371481

2025-06-17T20:48:32.622+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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I would like to know more about this!
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message-1408996616400146483

2025-08-24T02:09:31.241+00:00 — Tholin (@tholin)

Content

I'm confused. Running global routing is what I'm trying to do?

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message-1422937667204808937

2025-10-01T13:26:16.765+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1422937701522346004

2025-10-01T13:26:24.947+00:00 — Leo Moser (mole99) (@mole99)

Content

There's just something so funny about this 😆

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message-1422953799936381039

2025-10-01T14:30:23.108+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Such a cute little core!

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message-1423012580561129532

2025-10-01T18:23:57.501+00:00 — tnt (@246tnt)

Content

Do you really need 4 ground pins ? 😅
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message-1423013566348267662

2025-10-01T18:27:52.531+00:00 — RebelMike (@rebelmike)

Content

That's ~1mm^2?  Makes it obvious why I was wondering about just having pins on a single side, you could probably fit 11 of the 12 pins while massively increasing the core area
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message-1423014077084733481

2025-10-01T18:29:54.3+00:00 — Leo Moser (mole99) (@mole99)

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Content

Who doesn't? 😄  No, that was just a quick chip for creating a reproducible for Tim E.
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message-1423015154202968083

2025-10-01T18:34:11.105+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Yes, the ratio between padring and core is massive in this case. You might be able to use the LibreLane padring script as a starting point to adjust the padring to only a single side. If this is already possible in OpenROAD today, I can then adjust the default script to allow this directly.

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message-1423016793521524929

2025-10-01T18:40:41.949+00:00 — RebelMike (@rebelmike)

Content

Needing this is a little way off as we'd need to have options to subdivide the dies first, but it's on my list of things to play with at some point 🙂
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message-1423018673731407873

2025-10-01T18:48:10.226+00:00 — Leo Moser (mole99) (@mole99)

Content

Well, you can already subdivide a die yourself and submit several of your sub-dies at once.
The individual dies won't be separated, of course, but we should still be able to bond the ones around the edges 😉
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message-1423025876177653880

2025-10-01T19:16:47.423+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Even though it is super funny, it is also super cool!

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message-1423029024237551688

2025-10-01T19:29:17.979+00:00 — Tholin (@tholin)

Content

Chip with just 4 pads. Power, ground, two bidir (clock provided by ring oscillator).

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message-1423030878296215663

2025-10-01T19:36:40.021+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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I think you can team up with @RebelMike  and share a subdivided die 😁
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message-1423030957438537729

2025-10-01T19:36:58.89+00:00 — Tholin (@tholin)

Content

I don't know what I would even put on there
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message-1423030973846782104

2025-10-01T19:37:02.802+00:00 — Tholin (@tholin)

Content

Something I²C, I guess?
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message-1423031373555433502

2025-10-01T19:38:38.1+00:00 — urish

Content

USB
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message-1423031519080874095

2025-10-01T19:39:12.796+00:00 — Tholin (@tholin)

Content

That sounds like a challenge. Doesn't that require precise timing? Out of a ring oscillator?
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message-1423031553554120745

2025-10-01T19:39:21.015+00:00 — urish

Content

(Precisely Clocking 12 MHz internally is a challenge left to the reader)
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message-1423031796945260554

2025-10-01T19:40:19.044+00:00 — Tholin (@tholin)

Content

I mean, how does the USB protocol work? Surely, there is some pre-defined discovery packet that is sent by the host? That could be used to tune the ring oscillator.
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message-1423031865224466634

2025-10-01T19:40:35.323+00:00 — urish

Content

ATtiny85's internal RC osc can somehow manage USB
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message-1423032065494089778

2025-10-01T19:41:23.071+00:00 — Tholin (@tholin)

Content

Oh, yeah, USB packets literally start with a bunch of even pulses as a clock sync.
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message-1423032249892212819

2025-10-01T19:42:07.035+00:00 — Tholin (@tholin)

Content

But not sure how you'd tune a ring oscilator off of that
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message-1423032276542951434

2025-10-01T19:42:13.389+00:00 — Tholin (@tholin)

Content

THAT I will leave as a challenge to the reader

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message-1423032713878704231

2025-10-01T19:43:57.658+00:00 — urish

Content

I guess you could also try to get a clock through VDD somehow
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message-1423032827334754345

2025-10-01T19:44:24.708+00:00 — urish

Content

like swing it between 3V and 3V3 at 12MHz (or whatever you need), and then use that internally to generate the clock
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message-1423033101726122035

2025-10-01T19:45:30.128+00:00 — urish

Content

an easy-ish way to create it would be to connect the VDD pin to the power supply through a FET in parallel with a diode
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message-1423033204931297360

2025-10-01T19:45:54.734+00:00 — urish

Content

then you feed the clock to the FET, and whenever the FET is off, the voltage will drop by the diode forward voltage drop
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message-1423033895086981296

2025-10-01T19:48:39.28+00:00 — RebelMike (@rebelmike)

Content

We have OTP, right?  So, you first start in a mode where you can blow OTP bits somehow to tune the ring oscillator.  Then once that's within tolerances you blow a bit that permanently turns the device into a USB
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message-1423033962946891911

2025-10-01T19:48:55.459+00:00 — Tholin (@tholin)

Content

One way a ring oscillator could be made tuneable is by using transmission gates to bypass some of the inverters. Have one path that goes through the inverters and one path that goes around them. I'm not sure if that'll provide ultra fine control, but it doesn't need to be perfect. The clock only needs to line up with the USB data bits for one packet before the next one re-tunes the oscillator.
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message-1423033979715588207

2025-10-01T19:48:59.457+00:00 — Tholin (@tholin)

Content

Okay, now I'll stop!
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message-1423034211790749836

2025-10-01T19:49:54.788+00:00 — Tholin (@tholin)

Content

(The idea of using a NFET and DAC as a digitally controllable impedance to speed down the oscillator also occured to me, but I'm not sure how well that'd work, actually)
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message-1423034627421110294

2025-10-01T19:51:33.882+00:00 — Tholin (@tholin)

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Not really feasible, since you need to dynamically account for drift of the oscillator by supply voltage and temperature.
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message-1423047073611382846

2025-10-01T20:41:01.285+00:00 — Tim 'mithro' Ansell (@mithro_)

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Reminds me of some very old 4 pin PIC10F devices which had a shared GPIO/VDD pin and a large internal capacitor with specs of how long you could pull the GPIO line low.....
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message-1423047374196179116

2025-10-01T20:42:12.95+00:00 — Tim 'mithro' Ansell (@mithro_)

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PLL on the USB packet with oscillator as initial frequency input is how the SiLab HappyGecko parts are able to meet spec without an external crystal
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message-1423050264138481806

2025-10-01T20:53:41.966+00:00 — Tholin (@tholin)

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message-1423050407516569722

2025-10-01T20:54:16.15+00:00 — Tim 'mithro' Ansell (@mithro_)

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😛
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message-1423752140198907966

2025-10-03T19:22:42.259+00:00 — Tholin (@tholin)

Content

I finished developing a software network stack to run on my RISC-V core on my GFMPW-1 chips.
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message-1423752157844340736

2025-10-03T19:22:46.466+00:00 — Tholin (@tholin)

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message-1423752917621542912

2025-10-03T19:25:47.611+00:00 — Tholin (@tholin)

Content

Powering on the board does this

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message-1423753086350004314

2025-10-03T19:26:27.839+00:00 — Tholin (@tholin)

Content

I need to turn this around and make it capable of accepting incoming TCP connections.
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message-1423753183452332264

2025-10-03T19:26:50.99+00:00 — Tholin (@tholin)

Content

Will I be the first person to get open-source custom silicon connected to the internet? Or host a website with it?

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message-1423754179851194540

2025-10-03T19:30:48.55+00:00 — Tholin (@tholin)

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I went the extra mile to support both IPv4 *and* IPv6 **and** auto-configuration for both.
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message-1423790721890255061

2025-10-03T21:56:00.851+00:00 — Tim Edwards (@rtimothyedwards_19428)

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This is impressive.
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message-1423793682368434238

2025-10-03T22:07:46.684+00:00 — Tholin (@tholin)

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https://github.com/AvalonSemiconductors/gfmpw1-multi-bringup/tree/main/TholinRISCV/Software/Ethernet

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message-1423793699686711378

2025-10-03T22:07:50.813+00:00 — Tholin (@tholin)

Content

The source code is here, btw
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message-1423794571233595492

2025-10-03T22:11:18.606+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Tholin - That is super cool!
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message-1423794906823921804

2025-10-03T22:12:38.617+00:00 — Tim 'mithro' Ansell (@mithro_)

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I guess depends on how you define that -- @carlfk put the Tiny Tapeout board on the internet but I think that is cheating. I wonder if you could run ppp over the uart to the Linux core.....
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message-1423795071475650650

2025-10-03T22:13:17.873+00:00 — Tholin (@tholin)

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Due to the fact that dial-up modems once existed, you can actually pipe a network connection over UART to this day with some basic Linux utilities.
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message-1423796107401756723

2025-10-03T22:17:24.857+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Tholin - I think the Tiny Tapeout Linux core might be too slow? I think there are some real time requirements for PPP? I've forgotten what was the thing that we used before PPP.
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message-1423796700857892985

2025-10-03T22:19:46.348+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Also, I wouldn't say your work above is particularly off-topic, seems very much on topic to me.
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message-1423798589393469512

2025-10-03T22:27:16.61+00:00 — Tholin (@tholin)

Content

Well, its more software dev on a RISC-V core
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message-1423798611849908285

2025-10-03T22:27:21.964+00:00 — Tholin (@tholin)

Content

Its just that the core happens to be custom silicon
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message-1423880147681148999

2025-10-04T03:51:21.621+00:00 — urish

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The original one only supports 8mb PSRAM, so it's not sufficient to run the TCP/IP stack
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message-1423880385024229436

2025-10-04T03:52:18.208+00:00 — urish

Content

I recently patched it to support 16mb so the future version (on ttsky25a/ttihp25b) might be able to
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message-1423882117695279134

2025-10-04T03:59:11.309+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@urish - Cool!
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2025-10-04T04:00:41.27+00:00 — urish

Content

Hirosh is also currently working on adding FIFO to the UART to make it more reliable
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message-1423952150706520104

2025-10-04T08:37:28.48+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

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Are you thinking of SLIP? I remember THOSE good ol’ days 😉
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message-1423952470383657001

2025-10-04T08:38:44.697+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

Content

Btw @Tholin , awesome and exciting work as usual 🙂 What I really want to know is how you managed to crack the usual limit of 24 hours per day in order to get all of this done 😉

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message-1423963375213346816

2025-10-04T09:22:04.611+00:00 — Xobs (@xobs)

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SLIP is still very much alive. The ESP32 uses it to communicate with its bootloader, for example.

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2025-10-04T10:03:15.976+00:00 — algofoogle (Anton Maurovic) (@algofoogle)

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Oh cool, and unexpected 🙂
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2025-10-04T17:02:40.563+00:00 — Tim 'mithro' Ansell (@mithro_)

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Probably!
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message-1425303980963008592

2025-10-08T02:09:09.929+00:00 — carlfk

Content

> 40000 / 3600
> 11.11111111111111
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message-1425304144692117585

2025-10-08T02:09:48.965+00:00 — carlfk

Content

11 hours for 40,000 seconds?   I thought it was nore like 20 hours?
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message-1425304196076408833

2025-10-08T02:10:01.216+00:00 — carlfk

Content

or mayb eit was 3 sec per die = 33 hours
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message-1425312858752811039

2025-10-08T02:44:26.559+00:00 — Andrew Wingate (@anfroholic)

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You may have had part of my calculation in your head when it was
28 reticles * 40 projects * 50 wafers = 56000 dies
56000/3600 = 15.55
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2025-10-08T03:03:48.107+00:00 — carlfk

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that sounds about right
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message-1426660745948696657

2025-10-11T20:00:27.909+00:00 — Tholin (@tholin)

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https://testing.tholin.dev/
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message-1426660774818091079

2025-10-11T20:00:34.792+00:00 — Tholin (@tholin)

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Now hosting a website on my custom silicon

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2025-10-11T20:00:48.107+00:00 — Tholin (@tholin)

Content

It'll remain online for as long as the 18650 powering it lasts.
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2025-10-11T20:01:24.723+00:00 — madbrain (@mrmadbrain)

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it's kinda meta 😛
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message-1430997050962481162

2025-10-23T19:11:23.589+00:00 — HardWall (@hardwall)

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I'm curious what people here make of this: https://tenstorrent.com/vision/tenstorrent-announces-open-chiplet-atlas-ecosystem

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message-1431375817304440984

2025-10-24T20:16:28.522+00:00 — Tim 'mithro' Ansell (@mithro_)

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@HardWall - Multiple people have attempted this - none have succeeded. https://antmicro.com/blog/2020/10/open-chiplet-initiative/

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message-1431377409604845739

2025-10-24T20:22:48.156+00:00 — HardWall (@hardwall)

Content

It's true until it's not. I have a bit of a bias since I'm kind of a keller fanboy, but I really don't understand the industry enough to make an educated guess.
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message-1431377840632238183

2025-10-24T20:24:30.921+00:00 — HardWall (@hardwall)

Content

My understanding though is that chiplet designs will be by their nature inferior to the same design but integrated on the same die. But more composable and faster turnaround. ( again, i'm not sure I even understand properly what I'm talking about)
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message-1431379828342263960

2025-10-24T20:32:24.828+00:00 — HardWall (@hardwall)

Content

Wow, threw Claude a request to do some research, You weren't kidding, the world is littered with the bodies of chiplet interconnect initiatives.
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message-1431432199806259331

2025-10-25T00:00:31.158+00:00 — Andrew Wingate (@anfroholic)

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If this were ever to be a thing, I think the first step would be an open source [SerDes](https://en.wikipedia.org/wiki/SerDes) for ASIC design.
I was speaking with @carlfk the other day about putting HDMI on an ASIC design and he said this part was still a current hurdle.
Chiplets--at least the current versions from AMD--all communicate over SerDes.

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message-1431455236605608079

2025-10-25T01:32:03.559+00:00 — Tim 'mithro' Ansell (@mithro_)

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The problem turns out to be economics -- at the moment chiplets makes sense when things are very expensive -- but to get an ROI you need to sell a lot of units, thus if you are selling lots of units you want the chiplets to be customized for your use case.....
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message-1431522960832724992

2025-10-25T06:01:10.273+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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I was under the impression that some of the economics came from just yield gains?
I also personally think some of the coolest stuff (other than wafer.space) happening right now is in the packaging space.

@HardWall I do see a potential case *maybe* where the design for the opposing interconnect would be designed by the one party. And the second party can put that into their design.
Also something else, is if you start to think of things like PCBs where you have a series of components on a PCB, a similar concept would be a series of dies on a silicon interposer.
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message-1431841504938164308

2025-10-26T03:06:57.106+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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@Andrew Wingate - Below 5nm, chiplets ***do*** make sense for making these high end chips (for yield and other cost reasons).

The problem is the chiplet marketplace / reuse idea.

Basically, the people working on these high end nodes need to make a large number of parts to recoup the cost of the design. When you go, "I'm going to need to make 1 million of these parts" then it pretty much always makes sense to customize the chiplet for that part.

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message-1444888126144385095

2025-12-01T03:09:33.996+00:00 — BreakingTaps (@polyfractal)

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🥵

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message-1444895374186647713

2025-12-01T03:38:22.064+00:00 — Marcus (@bigturtle8)

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I feel like I've seen this program before and it looks very nice, could i ask what it is
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message-1444895659806294228

2025-12-01T03:39:30.161+00:00 — BreakingTaps (@polyfractal)

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`btop`! https://github.com/aristocratos/btop

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message-1445020377637191751

2025-12-01T11:55:05.209+00:00 — Tim 'mithro' Ansell (@mithro_)

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I generally use htop
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message-1446212702765842534

2025-12-04T18:52:57.672+00:00 — BreakingTaps (@polyfractal)

Content

looks like this'll be roughly what I tape out, modulo a few last minute tweaks!

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message-1446213370272284834

2025-12-04T18:55:36.818+00:00 — urish

Content

gorgeous!

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message-1446257644208914553

2025-12-04T21:51:32.547+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Memory Bank
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message-1446258509292245294

2025-12-04T21:54:58.799+00:00 — BreakingTaps (@polyfractal)

Content

haha yeah, it's basically memory with a some logic thrown in for fun 😂

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message-1446282741032419449

2025-12-04T23:31:16.096+00:00 — Tim 'mithro' Ansell (@mithro_)

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That is pretty cool! Specially seeing the SRAM layout.
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message-1446286300926709851

2025-12-04T23:45:24.841+00:00 — BreakingTaps (@polyfractal)

Content

thanks! took some finagling to get everything placed nicely. I knocked together a quick tool to make it easier to hand edit/place macro blocks, i'll upload it tonight when I get home in case anyone else wants to use it.
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message-1446286485832732732

2025-12-04T23:46:08.926+00:00 — BreakingTaps (@polyfractal)

Content

not entirely certain this is needed now that I discovered the 9T cells, but having everything physically close instead of columns helped get timing issues under control
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message-1446311554558464081

2025-12-05T01:25:45.776+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - Also this is very on topic....
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message-1446313357257871492

2025-12-05T01:32:55.573+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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For some reason discord won't let me forward your message to #general....
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message-1446313412652040355

2025-12-05T01:33:08.78+00:00 — Tim 'mithro' Ansell (@mithro_)

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Cool!
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message-1446431488651558935

2025-12-05T09:22:20.292+00:00 — urish

Content

Nice to see all the wafer.space logos that were not picked:
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message-1446431490505445376

2025-12-05T09:22:20.734+00:00 — urish

Content

https://www.freelancer.in/contest/logo-design-for-waferspace-2545806/entries

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message-1446559793635524771

2025-12-05T17:52:10.584+00:00 — asic destroyer (@logic_destroyer)

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message-1446559858168955043

2025-12-05T17:52:25.97+00:00 — urish

Content

Nice!

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message-1446661633056309328

2025-12-06T00:36:50.994+00:00 — Andrew Wingate (@anfroholic)

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I never noticed the dies in the logo are 'W' and 'S' for wafer.space.
Thought that was neat.
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message-1446667310822723704

2025-12-06T00:59:24.679+00:00 — BreakingTaps (@polyfractal)

Content

Hah! missed that as well, clever 🙂
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message-1446734231354081312

2025-12-06T05:25:19.777+00:00 — urish

Content

Same here
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message-1446764649306521640

2025-12-06T07:26:11.982+00:00 — Tim 'mithro' Ansell (@mithro_)

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Wanna share the code which produces that?
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message-1446764769292845119

2025-12-06T07:26:40.589+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

The W and S where inspired by things like the hidden arrow in the Fedex logo 🙂
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message-1446957854094528683

2025-12-06T20:13:55.593+00:00 — BreakingTaps (@polyfractal)

Content

off to camp in the woods for the weekend, hope nothing breaks while I'm gone 😂

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message-1447054947781836930

2025-12-07T02:39:44.532+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Enjoy!
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message-1448688667509129357

2025-12-11T14:51:33.668+00:00 — BreakingTaps (@polyfractal)

Content

🥳

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message-1449450491892334602

2025-12-13T17:18:46.755+00:00 — BreakingTaps (@polyfractal)

Content

Are there MPW shuttles out there for "more" modern nodes, say 22-65nm? Obviously would need NDA and probably be a lot more expensive. Was just curious now that I've been bitten by the silicon bug 😅
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message-1449450614969860280

2025-12-13T17:19:16.099+00:00 — BreakingTaps (@polyfractal)

Content

or do you have to go and buy a full wafer from the fab at more modern nodes?
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message-1449451245634064435

2025-12-13T17:21:46.461+00:00 — urish

Content

Check out Europractice and muse semi for some
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message-1449451470834630787

2025-12-13T17:22:40.153+00:00 — urish

Content

Surprisingly, signing the NDA can sometimes take longer than the shuttle's turnaround
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message-1449452677103751270

2025-12-13T17:27:27.75+00:00 — BreakingTaps (@polyfractal)

Content

will take a look, thanks!
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message-1449452727968202954

2025-12-13T17:27:39.877+00:00 — BreakingTaps (@polyfractal)

Content

and oof, that sounds awful. why so long for NDA and paperwork?
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message-1449459348957958318

2025-12-13T17:53:58.444+00:00 — urish

Content

I ask - why NDA at all?

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message-1449466838399455443

2025-12-13T18:23:44.066+00:00 — BreakingTaps (@polyfractal)

Content

hah yeah that's fair. especially for older nodes, it's not like there's a lot of cutting edge IP that could be reverse engineered there... presumably the industry knows all the tricks already and has applied it to the latest nodes

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message-1449488708783964222

2025-12-13T19:50:38.372+00:00 — LukeW (@luke_w)

Reply/reference

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Content

I think my employer has used IMEC for MPW tapeouts on non-cutting-edge TSMC (e.g. 40LP): https://www.imeciclink.com/en/asic-fabrication/mpw-schedules-2025

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message-1449488914766368818

2025-12-13T19:51:27.482+00:00 — LukeW (@luke_w)

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it's more of a "send an email and talk to a guy" experience rather than an online shopping experience
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message-1449489458507284622

2025-12-13T19:53:37.12+00:00 — LukeW (@luke_w)

Content

also I don't think just booking an MPW slot is enough to actually get your hands on the design rule manual, foundry cell libraries and foundry RAM compiler etc for your process. That part probably involves talking directly to TSMC. I've luckily been insulated from this 😅
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message-1449489879263215707

2025-12-13T19:55:17.436+00:00 — LukeW (@luke_w)

Content

The real magic of wafer.space for me so far has been that the PDK is open, and equally importantly that people like Leo have done a ton of work to put a baseline flow together so you can get to GDS on day 1 and then iterate from there

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message-1449498608415281152

2025-12-13T20:29:58.628+00:00 — BreakingTaps (@polyfractal)

Content

fascinating. I knew the industry was pretty locked down, didn't realize it was to that degree
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message-1449498663800799232

2025-12-13T20:30:11.833+00:00 — BreakingTaps (@polyfractal)

Content

makes me appreciate TT and wafer.space even more!

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message-1449501792361779271

2025-12-13T20:42:37.74+00:00 — Tim Edwards (@rtimothyedwards_19428)

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Some of us have been fighting the industry mindset for decades.  It's a wonderful feeling to see some progress come out of all of that, finally.

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message-1449541886196056198

2025-12-13T23:21:56.855+00:00 — Lofty (@ravenslofty)

Content

<https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs>

> Here’s a more professional and polished version of your Markdown — ready to paste directly into your README.md:

I...would suggest getting rid of that line

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message-1449583403266478101

2025-12-14T02:06:55.296+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

Because lawyers are involved and nobody really has an incentive to make it better.
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message-1449583988946632734

2025-12-14T02:09:14.933+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I assume @Andrew Wingate asked an AI to make his words seem more professional and had a copy and paste oppsie.
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message-1449584135562592417

2025-12-14T02:09:49.889+00:00 — Andrew Wingate (@anfroholic)

Content

Lmao. Oops
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message-1449584320326144000

2025-12-14T02:10:33.94+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

BTW Most foundries have MPW programs. My understand is that most of these MPW programs *lose* the foundry money which leads to them being very restrictive about what you can do with their MPW program.

Both EuroPractice / MOSIS also **lose** money and can only continue to run with government grants and such.
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message-1449585001657270392

2025-12-14T02:13:16.382+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I did this comparison back in 2022 - https://docs.google.com/document/d/1rGOHsDU8XALX7jKw31Q59y3njZ0865T2qZPzhHIjIYo/edit?tab=t.0

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message-1449585225909665854

2025-12-14T02:14:09.848+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

One of my goals with wafer.space is to show that you can run an MPW service for profit (with both the MPW company is making money, the foundry is making money) and then slowly take over the rest of GF's MPW program.
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message-1449585287029068047

2025-12-14T02:14:24.42+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

(goals might be the wrong word -- maybe dreams?)
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message-1449585497922863315

2025-12-14T02:15:14.701+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

My (very limited) understanding is their current MPW program consumes somewhere between $50m and $100m in ongoing funding every year.

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message-1449784227502625032

2025-12-14T15:24:55.525+00:00 — BreakingTaps (@polyfractal)

Content

woah crazy, I didn't realize they were net-negatives to the foundry. guess they view it as a necessary evil and "marketing", but not something they really want to support
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message-1449807564274405428

2025-12-14T16:57:39.445+00:00 — asic destroyer (@logic_destroyer)

Content

Hello  @Tim 'mithro' Ansell  could you create a new channel for PCB design where we can discuss?
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message-1450231285371899975

2025-12-15T21:01:22.427+00:00 — Lofty (@ravenslofty)

Content

<https://github.com/Ravenslofty/blog/issues/17>
Perhaps this will inspire some people to help me ^^;

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message-1450272963856433212

2025-12-15T23:46:59.352+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I think most people have been using the #📦-cob channel for now?

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message-1450279395901051022

2025-12-16T00:12:32.871+00:00 — Tea-Rex (@the.tearex)

Content

hey @Tim 'mithro' Ansell nice community! this is alex from linkedin \:)
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message-1450279582535127082

2025-12-16T00:13:17.368+00:00 — Tim 'mithro' Ansell (@mithro_)

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You'll have to remind me who that is, I have a terrible memory 🙂
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message-1450279777683636234

2025-12-16T00:14:03.895+00:00 — Tea-Rex (@the.tearex)

Content

😅 No worries

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message-1450908917738770442

2025-12-17T17:54:02.573+00:00 — BreakingTaps (@polyfractal)

Content

pushed the button this morning, exciting / terrifying! Cheers to all the folks who made Wafer.space possible. even if my silicon comes back totally useless it was a fun project. excited to make a video about it and share WS more widely with folks!

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message-1450932763606913155

2025-12-17T19:28:47.871+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

Now you have your life back.

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message-1450943272217481409

2025-12-17T20:10:33.319+00:00 — BreakingTaps (@polyfractal)

Content

at least for a little while, then I have to write an assembler/compiler/simulator and documentation 😅

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2025-12-17T20:30:16.968+00:00 — asic destroyer (@logic_destroyer)

Content

AI is your friend
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2025-12-17T20:30:27.989+00:00 — asic destroyer (@logic_destroyer)

Content

5 minutes job 🙂
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message-1450977263263678485

2025-12-17T22:25:37.416+00:00 — Tholin (@tholin)

Content

I found a few more minor bugs in my RTL. Cutting it a little close now!
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message-1450977321971482717

2025-12-17T22:25:51.413+00:00 — Tholin (@tholin)

Content

Turned of all the DRC and just crossing my fingers the precheck passes first try.

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message-1450982041377312891

2025-12-17T22:44:36.607+00:00 — BreakingTaps (@polyfractal)

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Content

hah, well, with a TTA all the tricky work is in the compiler (the compiler handles all the timing, register bypassing, etc etc)

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message-1450982218959945861

2025-12-17T22:45:18.946+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Die Panik hatte ich auch gestern!
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message-1450988227816063087

2025-12-17T23:09:11.569+00:00 — Trevor Peyton (@trev5514)

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Same here 🙃

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message-1450988344241557646

2025-12-17T23:09:39.327+00:00 — Tholin (@tholin)

Content

If I don’t get zero antenna violations on this current run, its toast!
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2025-12-17T23:16:15.587+00:00 — Tholin (@tholin)

Content

Its clear

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message-1450990093631361205

2025-12-17T23:16:36.414+00:00 — Tholin (@tholin)

Content

I opened the GDSII in KLayout and did a DRC check with my own eyeballs, since I’m just looking for the PDN bug.
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message-1450993977695408312

2025-12-17T23:32:02.447+00:00 — Tholin (@tholin)

Content

Precheck running
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message-1451023066422317088

2025-12-18T01:27:37.74+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Thank you for getting involved. I'm super excited to see the eventual video. If you need anything from us to help make the video better please don't hesitate to ask!

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message-1451023184097710080

2025-12-18T01:28:05.796+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I think that is called the "real industry flow" 😛
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message-1451027128761188392

2025-12-18T01:43:46.277+00:00 — Tim 'mithro' Ansell (@mithro_)

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How does the precheck runtime on platform.wafer.space compare to your local runtime?

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2025-12-18T03:08:28.568+00:00 — Tea-Rex (@the.tearex)

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I look forward to watching it!

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2025-12-18T05:17:15.401+00:00 — Thorben (@thorben_61995)

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The precheck on platform.wafer.space is running at least 30 minutes faster (on a 4 to 5 hour check) compared to an AWS EC2 c6a.4xlarge instance. I will try to get more accurate numbers.
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message-1451088009931001877

2025-12-18T05:45:41.479+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Thorben - That is a useful comparison! The prechecker machines are 2 * Hetzner EX63 with Intel Core Ultra 7 265 (Arrow Lake) and 20 (8 Performance + 12 Efficiency) cores with 192GB of memory.
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message-1451125315211366542

2025-12-18T08:13:55.751+00:00 — Tholin (@tholin)

Reply/reference

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Content

This is probably much faster than running the precheck locally.
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message-1451158455619551285

2025-12-18T10:25:37.04+00:00 — Tholin (@tholin)

Reply/reference

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Content

Another example of real industry:

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message-1451158576696660116

2025-12-18T10:26:05.907+00:00 — Tholin (@tholin)

Content

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message-1451158621206609951

2025-12-18T10:26:16.519+00:00 — Tholin (@tholin)

Content

That footnote won’t stop me from trying, because I choose not to read it!

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message-1451235877593284651

2025-12-18T15:33:15.877+00:00 — Noritsuna Imamura (@noritsunaimamura)

Content

I wrote an article about the Wafer.Space GF180MCU Run 1 for the Japanese technology magazine I/O( https://www.kohgakusha.co.jp/io/ , The release date is the 18/Jan, Japan Only).
I hope to see more submissions from Japan next time.

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message-1451311867900334092

2025-12-18T20:35:13.378+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Do you need a high quality wafer.space logo to embed in it?
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message-1451326817892827239

2025-12-18T21:34:37.734+00:00 — Noritsuna Imamura (@noritsunaimamura)

Reply/reference

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It has already been submitted, so it is not necessary.
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message-1451523469094293659

2025-12-19T10:36:03.034+00:00 — Thorben (@thorben_61995)

Reply/reference

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Even better, averaging over 3 runs each, the 1.5.5. precheck on my design took ~6:04 hours on the AWS EC2 c6a.4xlarge instance and ~4:24 hours on platform.wafer.space. A full 100 minutes saved 👍
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message-1452082944230297793

2025-12-20T23:39:12.301+00:00 — Andrew Wingate (@anfroholic)

Content

I took part in a lightning talk competition for the Chicago Python users group. [chipy](https://www.chipy.org/)
For what it's worth I won!! 🎉

Here were the slides from my talk.
https://docs.google.com/presentation/d/1aJlZnewZyQ7TH-IltYSDIhDfgPEW-apW4D6T0YGUq8k/edit?usp=sharing

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message-1452280412473655356

2025-12-21T12:43:52.399+00:00 — asic destroyer (@logic_destroyer)

Content

@Tim 'mithro' Ansell @Leo Moser (mole99)
It’s crazy — I started my gate-level simulation on **December 3rd**, and **18 days later**, today **December 21st**, I can finally see the first kernel messages… maybe in **two weeks** it’ll boot into the console.

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message-1452280922216075471

2025-12-21T12:45:53.931+00:00 — asic destroyer (@logic_destroyer)

Content

This gate-level simulation runs against the Micron SDRAM model, so we’re simulating real SDRAM accesses.
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message-1452281559813066813

2025-12-21T12:48:25.946+00:00 — asic destroyer (@logic_destroyer)

Content

We have two caches: a 2-way set-associative instruction cache and a direct-mapped data cache. We also have 4-way I-TLB and 4-way D-TLB MMU caches.
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message-1452281798749851671

2025-12-21T12:49:22.913+00:00 — asic destroyer (@logic_destroyer)

Content

I can’t believe that 300k lines of Verilog generated by Yosys (thanx @Lofty) can actually work… that’s crazy.

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message-1452282605046071473

2025-12-21T12:52:35.149+00:00 — asic destroyer (@logic_destroyer)

Content

@Leo Moser (mole99)  helped a lot with LibreLane, and his name is immortalized on the chip. Thanks, Leo Moser.

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message-1452378850586656859

2025-12-21T19:15:01.874+00:00 — asic destroyer (@logic_destroyer)

Content

facts about my remote machine:
cpu: AMD Ryzen Threadripper 7960X s (48) @ 5.3GHz
gpu: AMD ATI Radeon RX 470/480/570/570X/580/580X/590
memory: 47.43 GiB / 251.20 GiB (18%)
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message-1452397808429695007

2025-12-21T20:30:21.776+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I wouldn't have the patience to wait for that! 😛

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message-1452413184509214861

2025-12-21T21:31:27.719+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

Linux booting is great, but that’s an integration milestone, not verification.
Nobody runs full OS workloads in gate level simulation. That’s what FPGA or emulation is for (Shen & Lipasti).
https://books.google.de/books/about/Modern_Processor_Design.html?id=VIWLAAAACAAJ&redir_esc=y

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message-1452413677528416475

2025-12-21T21:33:25.264+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

I have lots of thoughts about modern processor design coming from my time in Google's compiler & toolchain group.

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message-1452413979660910693

2025-12-21T21:34:37.298+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But I already try to do way too many things at the same time 🙂

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message-1452418025398603797

2025-12-21T21:50:41.877+00:00 — asic destroyer (@logic_destroyer)

Content

@Tim 'mithro' Ansell ,  I was excited for three weeks and checked every day, monitoring internal states. I wasn’t sure it would run. If it had run on my local PC, the noise would’ve killed me. Seeing the first output on remote machine today, I shouted with joy.
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message-1452705259867865251

2025-12-22T16:52:03.911+00:00 — BreakingTaps (@polyfractal)

Content

after the final reticle is stitched and approved by GF, would love to see an image of the combined GDS for it 🙂
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message-1452705342243733715

2025-12-22T16:52:23.551+00:00 — BreakingTaps (@polyfractal)

Content

would be neat to see all the projects laid out
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message-1452713628917563412

2025-12-22T17:25:19.248+00:00 — Lofty (@ravenslofty)

Content

Unfortunately while a number of projects have put a bunch of effort into aesthetics, some designs are just "how much logic can we cram into the die area" like mine ^^;
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message-1452714006325231719

2025-12-22T17:26:49.229+00:00 — Lofty (@ravenslofty)

Content

Like, mine is 110kgates :p

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message-1452715362545303553

2025-12-22T17:32:12.577+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

How do you calculate it?
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message-1452715475996770474

2025-12-22T17:32:39.626+00:00 — Lofty (@ravenslofty)

Reply/reference

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Yosys tells you
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message-1452715560667185233

2025-12-22T17:32:59.813+00:00 — asic destroyer (@logic_destroyer)

Content

stage 6?
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message-1452715790976553021

2025-12-22T17:33:54.723+00:00 — asic destroyer (@logic_destroyer)

Content

I have in metrics.csv

`design__instance__count__stdcell,136515`
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message-1452716529589289187

2025-12-22T17:36:50.822+00:00 — CatIsFluffy (@catisfluffy)

Content

You can use \`s to avoid formatting: "\`a\__b\__c\`"->`a__b__c`
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message-1452716607372791903

2025-12-22T17:37:09.367+00:00 — CatIsFluffy (@catisfluffy)

Content

(Or backslashes if you don't want the code formatting)
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message-1452717022067556363

2025-12-22T17:38:48.238+00:00 — BreakingTaps (@polyfractal)

Reply/reference

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hehe mine is similar, bunch of sram blocks and logic crammed in the middle 😅
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message-1452717884009877525

2025-12-22T17:42:13.741+00:00 — Lofty (@ravenslofty)

Content

```
=== chip_top ===

   Number of wires:             115772
   Number of wire bits:         115823
   Number of public wires:        7676
   Number of public wire bits:    7727
   Number of ports:                  5
   Number of port bits:             56
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:             115789
```
`yosys-synthesis.log`
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message-1452718625218756648

2025-12-22T17:45:10.459+00:00 — asic destroyer (@logic_destroyer)

Content

```
=== chip_top ===

   Number of wires:              66338
   Number of wire bits:          66391
   Number of public wires:       10925
   Number of public wire bits:   10978
   Number of ports:                  3
   Number of port bits:             56
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              66210
```
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message-1452719851905745098

2025-12-22T17:50:02.924+00:00 — asic destroyer (@logic_destroyer)

Content

@Lofty, I have a question for understanding: behind the standard cells, are there smaller/bigger “cells” like SRAM? I’d like to know how many transistors there are.
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message-1452720106055667854

2025-12-22T17:51:03.518+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

it's worth pointing out that yosys' definition of cell is "an instantiated thing", which would include SRAM blocks, yes
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message-1452720257268449391

2025-12-22T17:51:39.57+00:00 — Lofty (@ravenslofty)

Content

but even then, it's a bit tricky to count transistors
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message-1452720366299516999

2025-12-22T17:52:05.565+00:00 — asic destroyer (@logic_destroyer)

Content

I’m using 21 SRAM 512×8 cells. 🙂
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message-1452721070246461685

2025-12-22T17:54:53.399+00:00 — asic destroyer (@logic_destroyer)

Content

I was only confused because of the word gates.
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message-1452721298953470012

2025-12-22T17:55:47.927+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

```
$ grep "design__instance__count__stdcell" final/metrics.csv
design__instance__count__stdcell,212713
```
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message-1452721502909894907

2025-12-22T17:56:36.554+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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@Lofty
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message-1452721564813496424

2025-12-22T17:56:51.313+00:00 — Lofty (@ravenslofty)

Content

yes, stage 6

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message-1452721744619241624

2025-12-22T17:57:34.182+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

sorry! Wrong reply
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message-1452722736605692094

2025-12-22T18:01:30.69+00:00 — asic destroyer (@logic_destroyer)

Content

But it's not transistor count 🙁
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message-1452722905577295872

2025-12-22T18:02:10.976+00:00 — Lofty (@ravenslofty)

Content

as I said, transistor count is hard to calculate.
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message-1452723335913017385

2025-12-22T18:03:53.576+00:00 — asic destroyer (@logic_destroyer)

Content

I’m not very familiar with this. I thought the primitives might contain such metadata.
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message-1452723627362353172

2025-12-22T18:05:03.063+00:00 — Lofty (@ravenslofty)

Content

yes and no.
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message-1452723676003959059

2025-12-22T18:05:14.66+00:00 — Lofty (@ravenslofty)

Content

the "source" of the gates is gonna be the spice simulation models
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message-1452723784220934267

2025-12-22T18:05:40.461+00:00 — Lofty (@ravenslofty)

Content

but...two transistors in parallel behave identically to a single transistor that is twice as wide

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message-1452724322211725342

2025-12-22T18:07:48.728+00:00 — Lofty (@ravenslofty)

Content

and this isn't just theoretical
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message-1452724363206856745

2025-12-22T18:07:58.502+00:00 — Lofty (@ravenslofty)

Content

```
.SUBCKT gf180mcu_fd_sc_mcu7t5v0__inv_1 I ZN VDD VNW VPW VSS
X_i_0 ZN I VSS VPW nfet_05v0 W=8.2e-07 L=6e-07
X_i_1 ZN I VDD VNW pfet_05v0 W=1.22e-06 L=5e-07
.ENDS
```
here's a size-1 inverter
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message-1452724410883637369

2025-12-22T18:08:09.869+00:00 — Lofty (@ravenslofty)

Content

```
.SUBCKT gf180mcu_fd_sc_mcu7t5v0__inv_2 I ZN VDD VNW VPW VSS
X_i_0_0 ZN I VSS VPW nfet_05v0 W=8.2e-07 L=6e-07
X_i_0_1 VSS I ZN VPW nfet_05v0 W=8.2e-07 L=6e-07
X_i_1_0 ZN I VDD VNW pfet_05v0 W=1.22e-06 L=5e-07
X_i_1_1 VDD I ZN VNW pfet_05v0 W=1.22e-06 L=5e-07
.ENDS
```
here's a size-2 inverter
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message-1452724522867494942

2025-12-22T18:08:36.568+00:00 — Lofty (@ravenslofty)

Content

so, do we say that the size-2 inverter has 4 transistors and the size-1 inverter has 2?
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message-1452724589456134174

2025-12-22T18:08:52.444+00:00 — Lofty (@ravenslofty)

Content

even though the size-2 inverter can be implemented with 2 transistors of twice the width?
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message-1452724659966574640

2025-12-22T18:09:09.255+00:00 — Lofty (@ravenslofty)

Content

I don't know, I think "number of transistors" is not a useful metric

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message-1452725919088119828

2025-12-22T18:14:09.453+00:00 — asic destroyer (@logic_destroyer)

Content

```
cat ./libs.ref/gf180mcu_fd_ip_sram/spice/gf180mcu_fd_ip_sram__sram512x8m8wm1.spice | grep fet | wc -l
2189
```
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message-1452726548930236589

2025-12-22T18:16:39.619+00:00 — asic destroyer (@logic_destroyer)

Content

crazy, why so little?
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message-1452726616319983848

2025-12-22T18:16:55.686+00:00 — asic destroyer (@logic_destroyer)

Content

@tnt
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message-1452727086094483668

2025-12-22T18:18:47.689+00:00 — BreakingTaps (@polyfractal)

Content

4T cells perhaps? 2048 for the bits and rest is the plumbing?
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message-1452727232039616759

2025-12-22T18:19:22.485+00:00 — asic destroyer (@logic_destroyer)

Content

IDK
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message-1452727339724046336

2025-12-22T18:19:48.159+00:00 — tnt (@246tnt)

Content

It's definitely a 6T cell
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message-1452727451271692410

2025-12-22T18:20:14.754+00:00 — tnt (@246tnt)

Content

But it's also not a flat model ...
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message-1452727486499655751

2025-12-22T18:20:23.153+00:00 — tnt (@246tnt)

Content

It uses subckt instances and such ...

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message-1452731900459356191

2025-12-22T18:37:55.523+00:00 — asic destroyer (@logic_destroyer)

Content

With a 6T cell, we have around 30k to 40k transistors.
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2025-12-28T00:06:03.392+00:00 — asic destroyer (@logic_destroyer)

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I miss the sound of running LibreLane ASIC builds. My room gets so hot when my i9-14900K is under load. 🙁
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2025-12-28T00:08:59.692+00:00 — BreakingTaps (@polyfractal)

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can always start on your next tapeout project 😇

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2025-12-30T02:35:31.893+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Ha, it's 45C here in Adelaide at the moment. I'm keeping most of my servers in the off position at the moment.

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2025-12-30T19:47:36.901+00:00 — Andrew Wingate (@anfroholic)

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Holy shit that's hot.
That's 113 in Freedom Units for those that need it

Stay cool!
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2025-12-31T20:44:42.482+00:00 — chvsnaveen12

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@Tim 'mithro' Ansell  Would you guys be looking at sky130nm as well or is it just gf180nm for now?
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2025-12-31T22:28:50.344+00:00 — Tim 'mithro' Ansell (@mithro_)

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Just gf180mcu
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2026-01-05T20:15:16.473+00:00 — Matt Venn (@mattvenn)

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Read my review of 2025 and goals for 2026 here!
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message-1457829896934916219

2026-01-05T20:15:32.599+00:00 — Matt Venn (@mattvenn)

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https://www.zerotoasiccourse.com/post/year_update_2025/

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message-1457829929973579827

2026-01-05T20:15:40.476+00:00 — Matt Venn (@mattvenn)

Content

Happy new year everyone!
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2026-01-05T21:11:08.609+00:00 — Andrew Wingate (@anfroholic)

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Cool!
First I've heard about the mini-MosBius. That's neat!
Looking forward to 2026 as well!!
I also subscribed to your newsletter and look forward to reading those!
Keep up the great work Matt!

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2026-01-08T00:57:34.428+00:00 — Andrew Wingate (@anfroholic)

Content

I know this is a little different than the steps for GF180MCU, but this asianometry video shows all the steps in making 45nm wafers. (There are a lot of steps, like a whole lot!)
https://www.youtube.com/watch?v=zUgy29h0alM

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2026-01-09T00:48:46.004+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

Great update Matt! That post would be perfectly fine in #general IMHO.

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2026-01-09T20:58:57.575+00:00 — Your account is suspended for (@banned_user)

Content

"die sorter" is, of course, German for "the sorter"

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message-1462082162554834966

2026-01-17T13:52:31.726+00:00 — Noritsuna Imamura (@noritsunaimamura)

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Released  the magazine!

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message-1462660961398821050

2026-01-19T04:12:28.124+00:00 — Andrew Wingate (@anfroholic)

Content

Just watched another [great presentation](https://www.youtube.com/watch?v=DaWkfSmIgRs) from @bunnie about his new chip/architectures.
This looks amazing Bunnie, can't wait to see more!

This also led me to listen to a 14yr old [the-amp-hour-84-bunnies-bibelot-bonification](https://theamphour.com/the-amp-hour-84-bunnies-bibelot-bonification/) podcast where he made a prediction about the future.
He predicted there would not be much architectural improvements, because moore's law was moving so fast, but eventually when that slowed down we would start to see some novel and new approaches.

Seems it's coming true in the best way!! @bunnie did you think you'd be the hero you were looking for? 😉
Anyways, great stuff! Thank you for everything you're doing!

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message-1462663866373767310

2026-01-19T04:24:00.724+00:00 — bunnie (@bunnievorpal)

Content

Hah! well I've been champing at the bit for years to do something interesting with chips again...but my hope is that all the good people here will soon be putting out cool stuff I couldn't have thought up in my wildest dreams.

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message-1462665909222117376

2026-01-19T04:32:07.777+00:00 — Andrew Wingate (@anfroholic)

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Content

For sure! I think you've definitely set a bar though.
It's great to see
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message-1462730646450471017

2026-01-19T08:49:22.335+00:00 — Your account is suspended for (@banned_user)

Content

FYI these talks are available on media.ccc.de before they're on YouTube

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message-1464903009996640381

2026-01-25T08:41:34.165+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://www.youtube.com/watch?v=Q41o08sSqSg

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message-1468826845930848406

2026-02-05T04:33:29.553+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://crackhead.technology/anjoy-ssc338q-libtools/

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2026-02-05T19:04:23.533+00:00 — Matt Venn (@mattvenn)

Content

What a domain name😆

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message-1470451545685622913

2026-02-09T16:09:28.16+00:00 — Matt Venn (@mattvenn)

Content

Posted a fun thread on twitter about a recent FIB experiment I did with Zeptobars - https://x.com/matthewvenn/status/2020521149713600550

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message-1473565849523589231

2026-02-18T06:24:36.056+00:00 — urish

Content

Tim, what's your fav animal?
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message-1474934906495696899

2026-02-22T01:04:44.674+00:00 — q3k (@q3k_)

Content

Hey there! Hope this is the right place to ask, got directed here by Matt. I threw an efabless OpenMPW GF180 die under the SEM today (not sure which shuttle this was, I was gifted this by a friend who wanted to get some SEM shots of it). Did not do any prep to the die other than cleaning, expected to see the topmost metal layer across whatever passivation later might be on top, same as with the SKY130 dies from an earlier OpenMPW run. However, the die was fully opaque to BSE and only very light contours of... CMP pads? Maybe PDN? were visible with SE imaging. Even at 30kV! Is this just that GF180 has one damn thick passivation layer on top, or am I missing something?

First photo is SE, second is BSE.

(The bright thing in the bottom left corner is copper tape for better sample conductivity. I cannot promise that this is standard procedure for sample prep. The bubbly thing to the right is conductive double-sided tape.)

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message-1474952155847725251

2026-02-22T02:13:17.24+00:00 — Tim 'mithro' Ansell (@mithro_)

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@q3k - Cool! I would love more GF180MCU photos and such
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2026-02-22T02:14:06.933+00:00 — Tim 'mithro' Ansell (@mithro_)

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@q3k - Maybe look at the stack up diagrams? See https://gf180mcu-pdk.readthedocs.io/en/latest/analog/layout/inter_specs/inter_specs_3.html @Tim Edwards might know more.
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2026-02-22T02:31:07.926+00:00 — Tim Edwards (@rtimothyedwards_19428)

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That's definitely Caravel;  I can identify the major blocks.  Where the layout is visible, it looks like the darker lines are the power distribution network;  The horizonal lines would be top level metal, and the vertical lines are the metal under that.  Not much else is visible.  As to what kind of passivation is on top of the chip, I really don't know.  I would not expect anything unusual.

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2026-02-22T09:31:40.739+00:00 — ZeptoBars (@zeptobars)

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As we just discussed with Matt - this is likely top polyimide passivation layer, which is likely present on GF180.
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2026-02-22T09:34:05.057+00:00 — ZeptoBars (@zeptobars)

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Polyimide is all light elements, so weak back-scattered signal.

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2026-03-04T03:11:42.008+00:00 — Tim 'mithro' Ansell (@mithro_)

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@tannewt - https://shop.m5stack.com/products/unit-poe-with-esp32-p4 <-- That device might do what you wanted (POE+USB Host) with a bit of coding

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2026-03-04T04:30:45.022+00:00 — tannewt

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Ya! I missed the usb c at the bottom
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2026-03-04T04:32:57.25+00:00 — Tim 'mithro' Ansell (@mithro_)

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2026-03-04T04:38:27.35+00:00 — tannewt

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definitely gonna make an order. thanks!
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2026-03-04T05:22:43.782+00:00 — tannewt

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did it literally just come out? it's first on new products
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2026-03-16T08:59:16.678+00:00 — nmz787

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https://nw-ai-hub.org/cxr

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2026-03-16T08:59:33.302+00:00 — nmz787

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28nm TSMC MPW cost covered for eligible applicants

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2026-03-25T15:17:15.973+00:00 — Essen (@essen__)

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2026-04-02T07:38:17.628+00:00 — RebelMike (@rebelmike)

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Does anyone else have a problem where this Discord server keeps being shown as unread even when there are no new messages?

I can normally clear it for a while by looking at the announcements channel, but it happens repeatedly.
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2026-04-02T11:39:38.629+00:00 — Leo Moser (mole99) (@mole99)

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2026-04-14T06:56:26.494+00:00 — Jason Yang (@.pogeg)

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Is it just me, or has gitter.im been down? When I try to log in with web, it says "no login methods available"
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2026-04-14T06:56:49.9+00:00 — Jason Yang (@.pogeg)

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I've never had a good experience with Matrix in general :<
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2026-04-14T22:02:37.394+00:00 — futaris [AU] (@futaris)

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https://www.tomshardware.com/tech-industry/artificial-intelligence/nvidia-says-ai-cuts-10-month-eight-engineer-gpu-design-task-to-overnight-job-company-is-still-a-long-way-from-ai-designing-chips-without-human-input

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message-1494164344991125545

2026-04-16T02:35:40.077+00:00 — BreakingTaps (@polyfractal)

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i think I saw it posted somewhere here, what was the rough cost of a GF180 reticle mask set? Seem to recall it's like 100k something?
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message-1494289751337996378

2026-04-16T10:53:59.28+00:00 — acidbourbon (@acidbourbon_85117)

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Hi! Is anyone of you going to be at Hackaday Europe in May? Apart from Mr. Venn, of course 🙂
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message-1494296517882941531

2026-04-16T11:20:52.55+00:00 — tnt (@246tnt)

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Pretty much all the TT crew will be there not just Matt 😅

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message-1494874681969217619

2026-04-18T01:38:17.61+00:00 — Tim 'mithro' Ansell (@mithro_)

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Somewhere between $100k and $200k depending on feature set and such.
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2026-04-18T01:59:51.753+00:00 — BreakingTaps (@polyfractal)

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got it, thanks @Tim 'mithro' Ansell!
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message-1496363691937890464

2026-04-22T04:15:05.251+00:00 — futaris [AU] (@futaris)

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https://youtu.be/h6GWikWlAQA

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message-1496968656746446908

2026-04-23T20:19:00.101+00:00 — The Computer Guy (@thecomputerguy)

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Got OSHWA certification on Aegis
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message-1498245540620537857

2026-04-27T08:52:52.94+00:00 — Andrew Wingate (@anfroholic)

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@needsadrink|woke I was told you would be interested in my power brick

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2026-04-27T12:21:59.437+00:00 — needsadrink|woke (@needsadrink)

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Nice lol
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message-1499146804791607426

2026-04-29T20:34:11.063+00:00 — Leon (@.leonmc)

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Do people here have opinions on the best way to get started with FPGA/ASIC design? My background is that I have a Master's degree in computer science, but it contained almost no courses in this direction (only one course where we created a simple RISC-V core in VHDL that ran on an FPGA, which was a lot of fun, but I still feel like I know nothing and should start learning from scratch). I love reading about TinyTapeout and wafer.space and what people do there, and would love to learn about this, but every time I try to get started I get lost trying to figure out the best way to start, and lose motivation.

I would like to create some designs that I can send to TinyTapeout (and maybe even wafer.space, but that's probably a too large investment for a hobby for me), and they don't need to have a practical purpose.
I know the Zero to ASIC course exists, but it's fairly expensive at $700, and I think I'd rather learn from a book/text than videos. But I could afford it and it seems to be the most popular resource aimed at beginners that don't want to study for years before getting something done, does anyone have any opinions if it's worth the price? And are there any other recommended resources? Should I simply find a book about Verilog and read that, and if so, which?
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message-1499148319933464588

2026-04-29T20:40:12.301+00:00 — kris (@kris____)

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i've heard good things about this book https://nandland.com/book-getting-started-with-fpga/ but i haven't personally read it
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message-1499148390607622245

2026-04-29T20:40:29.151+00:00 — Christopher (@fossify_37988)

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Do you have a particular goal? I don't think $700 is particularly expensive for what all is included
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message-1499148424338210889

2026-04-29T20:40:37.193+00:00 — kris (@kris____)

Content

there's a verilog/vhdl introduction on that website too
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message-1499148551543062528

2026-04-29T20:41:07.521+00:00 — Christopher (@fossify_37988)

Content

A master's education that would give you the tools for a novel desisgn and tapeout starts around 40k here for reference
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message-1499148988069187643

2026-04-29T20:42:51.597+00:00 — Leon (@.leonmc)

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Not really, other than making something (hopefully interesting/unique) and sending it to TinyTapeout. I'm hoping that as I learn, I come up with ideas.
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message-1499149148887449711

2026-04-29T20:43:29.939+00:00 — Leon (@.leonmc)

Reply/reference

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Cool, thanks for the link.
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message-1499149208635052193

2026-04-29T20:43:44.184+00:00 — Lofty (@ravenslofty)

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I feel like I might have a strong contender for the weirdest w.s submission :p
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message-1499149238892888064

2026-04-29T20:43:51.398+00:00 — Christopher (@fossify_37988)

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I'd start with fpgas personally then, but its up to you. There's a big "missing middle" problem in EE, where there's lots of stuff to start and almost nothing to bridge the gap between the cutting edge and the start

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message-1499149417750466760

2026-04-29T20:44:34.041+00:00 — Christopher (@fossify_37988)

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(usually because you're taking a tiny chunk of any given problem and spending a huge amount of time drilling down into a narrower and narrower spec)
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message-1499149524579516446

2026-04-29T20:44:59.511+00:00 — Leon (@.leonmc)

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For me the problem right now is
> there's lots of stuff to start
because I don't know what to choose 😅 So I hoped I could get some opinionated recommendations here to help me with this.
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message-1499149694419341363

2026-04-29T20:45:40.004+00:00 — Lofty (@ravenslofty)

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the classic example is a CPU. I think that's boring, so instead I made my chip play chess.
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2026-04-29T20:46:45.352+00:00 — Leon (@.leonmc)

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Yeah, I don't really want to do that (though I don't mind following some tutorial/book that uses this as an example for teaching stuff).
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message-1499150014667292723

2026-04-29T20:46:56.357+00:00 — Christopher (@fossify_37988)

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I learned on AMD's university program. You can get free access to fpgas at fpgas.online
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2026-04-29T20:46:57.063+00:00 — Leon (@.leonmc)

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At least a "normal" general purpose CPU
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message-1499150279210172537

2026-04-29T20:47:59.429+00:00 — Leon (@.leonmc)

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I assume I need to be enrolled at a university that offers that? Also that sounds too serious for me, I don't want to make this my carreer or anything like that
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2026-04-29T20:48:06.515+00:00 — Christopher (@fossify_37988)

Reply/reference

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No its all free
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message-1499150472412663808

2026-04-29T20:48:45.492+00:00 — Christopher (@fossify_37988)

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Vivado is probably the best environment other than the FOSS tools. EDA is pretty brutal
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2026-04-29T20:49:44.318+00:00 — Lofty (@ravenslofty)

Content

I have a kind of hot take that you do not need an FPGA to develop for hardware
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message-1499150739782766592

2026-04-29T20:49:49.238+00:00 — Leon (@.leonmc)

Content

Vivado is what we used in the course I mentioned. I hated it 😅
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message-1499150831109542038

2026-04-29T20:50:11.012+00:00 — Leon (@.leonmc)

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I'd like to stick with open source tools, assuming that's viable.
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message-1499150852944957554

2026-04-29T20:50:16.218+00:00 — Lofty (@ravenslofty)

Content

that in practice you spend so much time in sim and such that "synthesising the hardware" is kind of the very last step in the process

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2026-04-29T20:50:31.577+00:00 — Christopher (@fossify_37988)

Reply/reference

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Yeah but having a blinky is nice for students
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2026-04-29T20:50:36.845+00:00 — Lofty (@ravenslofty)

Reply/reference

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LibreLane uses FOSS tooling
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2026-04-29T20:50:44.134+00:00 — Lofty (@ravenslofty)

Content

(including a program I maintain :p)
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2026-04-29T20:51:05.566+00:00 — Christopher (@fossify_37988)

Reply/reference

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FOSS tools are plenty viable until you hit certain parts where they arent
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2026-04-29T20:51:34.842+00:00 — Christopher (@fossify_37988)

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They'll work fine for a cpu
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message-1499151236560191559

2026-04-29T20:51:47.679+00:00 — Brian Swetland (@dnaltews)

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I think there's good value in using FPGAs for development, to get a feel for running designs on some kind of hardware with quicker turnaround, but definitely agree that getting used to simulation and testing in simulation early is very worthwhile.
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message-1499151328239292557

2026-04-29T20:52:09.537+00:00 — Brian Swetland (@dnaltews)

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one thing you tend to find out quickly is debugging on-the-metal is a lot more involved than debugging software

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2026-04-29T20:53:24.656+00:00 — Brian Swetland (@dnaltews)

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harder to instrument things after the fact / instrument things without impacting timing, etc
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2026-04-29T20:55:14.239+00:00 — Lofty (@ravenslofty)

Reply/reference

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(I got the impression Leon didn't want to make a CPU...)
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2026-04-29T20:55:35.419+00:00 — kris (@kris____)

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make a gpu instead :P
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2026-04-29T20:56:19.934+00:00 — Lofty (@ravenslofty)

Content

Not a terrible suggestion, but I personally kinda suffer from scope creep when given such an idea
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2026-04-29T20:57:00.532+00:00 — Brian Swetland (@dnaltews)

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I feel like the open toolchain stuff was feeling very good on the supported lattice parts, and it's been a couple years since I've really poked at it, so I'd assume there are probably some other decently supported families.  And of course all the work done for going to actual silicon.
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2026-04-29T20:57:27.433+00:00 — Lofty (@ravenslofty)

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We're a first party toolchain for a vendor now :3

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2026-04-29T20:57:51.149+00:00 — Brian Swetland (@dnaltews)

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it really is fun seeing history repeat itself
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2026-04-29T20:58:43.144+00:00 — Brian Swetland (@dnaltews)

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I remember development in the mid-90s where every workstation vendor, etc, had a proprietary C compiler you had to wrangle with and wrote gcc off as a toy.
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2026-04-29T20:59:39.029+00:00 — Lofty (@ravenslofty)

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I think we're still being written off as a toy
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message-1499153235473207590

2026-04-29T20:59:44.257+00:00 — Lofty (@ravenslofty)

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^^;
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2026-04-29T21:00:53.522+00:00 — Brian Swetland (@dnaltews)

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oh they won't stop that even after you win
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2026-04-29T21:01:18.202+00:00 — Christopher (@fossify_37988)

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Substitute CPU for CPU-like (or simpler) abstraction then 😁
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2026-04-29T21:01:32.343+00:00 — Brian Swetland (@dnaltews)

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gah. now thinking about arguing with management in the early 2000s because they were convinced we'd be better off paying $7500/seat for the ARM compiler than using gcc

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2026-04-29T21:02:23.239+00:00 — Brian Swetland (@dnaltews)

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"but look at how much better it optimizes!"
"you do understand that all the critical path stuff (the vm core, the blitters, etc) are already hand-tuned assembly, right?"
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message-1499175303765950594

2026-04-29T22:27:25.748+00:00 — namibj

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CCGM1A1?
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2026-04-29T22:27:38.853+00:00 — Lofty (@ravenslofty)

Reply/reference

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the CCGM1 chips in general
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2026-04-29T22:27:57.41+00:00 — namibj

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afaik arguably it's just one chip 😄
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2026-04-29T22:28:02.31+00:00 — namibj

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just multi-chip packaging
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2026-04-29T22:28:16.602+00:00 — Lofty (@ravenslofty)

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eeeeh
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2026-04-29T22:28:33.129+00:00 — namibj

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but yes
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2026-04-30T09:36:29.56+00:00 — Tim 'mithro' Ansell (@mithro_)

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wafer.space is offering $4k USD and $7k USD slots (which get you 1,000 parts), Tiny Tapeout also offers tiles at ~$200 USD.
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2026-04-30T09:39:44.138+00:00 — Tim 'mithro' Ansell (@mithro_)

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Plenty of RTL developers don't use FPGAs (except by proxy of their very expensive emulation hardware from proprietary vendors having FPGAs inside them). There are plenty of options around using simulation and such too.

I personally think FPGAs are cool because of their speed of iteration. Plus you can always get access to them via https://fpgas.online 🙂
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2026-04-30T09:41:00.609+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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You can get suprisingly quite far with the hardware equivalent of printf debugging (IE blink an LED) -- 🙂
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2026-04-30T09:42:43.74+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Sadly, the Xilinx FPGA support can still be pretty rough in areas and I don't know anything about the state of Altera parts.
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2026-04-30T09:43:54.866+00:00 — Lofty (@ravenslofty)

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The future might perhaps be Gowin parts
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2026-04-30T18:50:22.653+00:00 — Dory (@dorythecat_v2)

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Asking on the proper channel now, I assume there must be some voltnuts around here right?
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2026-05-01T03:10:38.827+00:00 — Tim 'mithro' Ansell (@mithro_)

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https://antmicro.com/blog/2026/04/simulating-active-cooling-using-a-cfd-based-flow is pretty cool 🙂

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2026-05-01T20:46:16.97+00:00 — namibj

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I love it when system just breaks and you have to try and fix things when just wanting to take a lunch break...
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2026-05-01T21:38:21.976+00:00 — namibj

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running again, at least
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2026-05-01T21:39:19.13+00:00 — nmz787

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I'd recommend https://www.crowdsupply.com/1bitsquared/icebreaker-fpga since they have great tutorials https://docs.icebreaker-fpga.org/getting-started/, also lots of resources https://www.fpga4fun.com/

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message-1499889254074028033

2026-05-01T21:44:24.766+00:00 — nmz787

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apparently this "tang" fpga also is supported with open tools, and looks pretty cheap https://github.com/twied/TangPrimer-20K-example

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message-1499905014498459670

2026-05-01T22:47:02.344+00:00 — zyp (@vegard_e)

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strictly speaking, «tang» is not the name of a fpga, it's the name of sipeed's family of fpga devboards, they're based on gowin fpgas
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2026-05-01T22:50:20.958+00:00 — namibj

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any specialties from your compsci degree you may consider relevant to being able to do something more interesting than the average FPGA/ASIC "beginner after having finished a master's in compsci" perhaps?

There is of course the potential to work towards a demoscene entry for the spring 2027 competition I'd predict there to be on/with TT?
Unfortunately copyright of early video games (of the arcade era) might be in the way of doing a "remake" of such a game, perhaps using modern extensions/gamemodes to go along with the old.
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2026-05-01T22:51:38.939+00:00 — namibj

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was wondering why it didn't sound like any familiar fpga family; but gowin explains that well.
Yeah, they do have quite good price/performance and I've heard them to not demand $$$$ vendor tooling to utilize.
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message-1499967674883506206

2026-05-02T02:56:01.744+00:00 — Tim 'mithro' Ansell (@mithro_)

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I would also say that teaching software engineers hardware design has been significantly easier than teaching hardware engineers software design.
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2026-05-02T02:58:08.868+00:00 — Tim 'mithro' Ansell (@mithro_)

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There is also the Fomu workshop -> https://workshop.fomu.im -- And if you are at an event I'm also at, then I'll happily give you one of the Fomu boards for free if you show me that you have installed the toolchain.
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2026-05-02T06:25:39.809+00:00 — Leon (@.leonmc)

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Not sure, I haven't been able to come up with something, but currently I'm more worried about learning the basics than figuring out to do once I have.
Demoscene sounds cool, though spring 2027 is quite some time away (and speculative, if I understand your message correctly?).
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2026-05-02T06:31:12.716+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Leon - I think there is currently a demoscene competition open right now? https://tinytapeout.com/competitions/demoscene-ttsky26a-announce/

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2026-05-02T06:32:20.68+00:00 — Tim 'mithro' Ansell (@mithro_)

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The infrastructure that Tiny Tapeout has which lets you see the simulated VGA output in the browser is super cool.
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2026-05-02T06:38:53.156+00:00 — Leon (@.leonmc)

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As far as I understand, the deadline for submissions is about a week from now, this is too soon for me 😅
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2026-05-02T12:10:25.924+00:00 — namibj

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hence me suggesting to aim _calmly_ for the one we'd expect a year after.
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message-1500169570466402488

2026-05-02T16:18:17.402+00:00 — Tim 'mithro' Ansell (@mithro_)

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The best time to plant a tree was 30 years ago, the next best time is today 🙂

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2026-05-02T17:55:17.418+00:00 — namibj

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https://discord.com/channels/1361349522684510449/1361349523724570941/1500181556608635151
Honestly doesn't even need to be that huge, but I don't think the thin 0.8 mil wire is appropriate for a 5V output gate consuming on the order of 2~5 W (in what I assume to be mostly the gate "poly" of the GaN die).
Yes that's supposed to be a class-B power amplifier output stage on the wafer.space die into an impedance matching network (on consideration of the capacitive load and trying to be less wasteful, and not melting the wafer.space die).

It'd serve as PoC of the drive so that together with extensive simulation of the larger topology it should be far less risky to get someone to pay for the approximately 4-ish MW of fixed 1:2 ratio (but bidirectional current support) DC/DC converter that one would get out of a single tall-type wafer.space slice.
(The assumed 5x parallel EPC2019 per die amount to just over 9$ per such 5 in quantity. And that's just the semiconductors for the converter; it also needs a bunch of capacitors subjected to about 1% voltage ripple at a (possibly few) dozen MHz.
Sadly not really "cheap" but for reference, substation transformers in that power range had 2019 pricing around 100~150 kUSD.  But those are able to do higher ratios so feel free to adjust that by 4x for more comparable scale (assuming the DC/DC unit is segmented into 4 equal-power chunks with one set up for one W.S die in parallel in the stacks, and the others with 2/4/8 in parallel, to create an overall 1:16 voltage ratio).

There's a different topology for higher voltage ratios I have to look at again with the W.S driven EPC-co 200V GaN dies as assumption.
That's technically capable of buck-like down-regulation of operating voltage and the more complex phase-shift control would nominally give full suft-switching at least under compatible load.

I had meant to try a prototype of the topology for a microwave oven to do a monolithic boost-APFC & HVDC regulator (take in grid frequency or "alirack DC" at European voltages, emulate an ohmic resistor to the grid, turn the power into something the magnetron likes, provide good control over magnetron output power over at least a 100:1 range with over 10 dB of PSRR at DC w.r.t. targeted output power, to have an ability for accurate radiation dose control),
...but then I had to move and am now back on TinyTapeout MCML after I found out the project survived the efabless.
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message-1502929961256878160

2026-05-10T07:07:05.852+00:00 — Andrew Wingate (@anfroholic)

Content

@peterkinget @xianglin_pu Nice logo!

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message-1502930910377672715

2026-05-10T07:10:52.14+00:00 — Andrew Wingate (@anfroholic)

Content

Beautiful @Tholin!!
-# @kris

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message-1502978450808639549

2026-05-10T10:19:46.662+00:00 — Tholin (@tholin)

Content

Do you see this fill pattern in the background of my art? That’s not metal. I turned off all metal fills around my art. That is the COMP layer. Its diffusion. Somehow, you can see all the way down to the silicon behind the art.

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message-1502980142186893452

2026-05-10T10:26:29.918+00:00 — Leo Moser (mole99) (@mole99)

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Yes, you can see that also around the wafer.space logo. Good to know for the next run :)
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message-1502980653879398412

2026-05-10T10:28:31.915+00:00 — Tholin (@tholin)

Content

Indeed. I wonder if P and N type look different.
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message-1503079443785056366

2026-05-10T17:01:05.264+00:00 — peterkinget

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Credit goes to Cade Gleekel (see https://mosbius.org) who developed the logo.
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message-1503079622764658758

2026-05-10T17:01:47.936+00:00 — peterkinget

Reply/reference

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SiO2 is glass so transparent 😉
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message-1503081652925104288

2026-05-10T17:09:51.964+00:00 — Tholin (@tholin)

Content

I’m trying to get the SCL characterization scripts to work in a nix shell instead of the iic-osic-tools container and its failing because numpy won’t load

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message-1503081797045714974

2026-05-10T17:10:26.325+00:00 — Tholin (@tholin)

Content

But

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message-1503094532080795678

2026-05-10T18:01:02.594+00:00 — Tholin (@tholin)

Content

Its because I need to install lctime from my fork on git
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message-1503094576389427281

2026-05-10T18:01:13.158+00:00 — Tholin (@tholin)

Content

And I don’t know how to properly do that in this context
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message-1503095469201559703

2026-05-10T18:04:46.021+00:00 — Tholin (@tholin)

Content

Adding `git+https://codeberg.org/TholinVali/lctime.git` to `extra-python-packages` had no effect
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message-1503107584142344383

2026-05-10T18:52:54.448+00:00 — Leo Moser (mole99) (@mole99)

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`extra-python-packages` expects a Nix derivation, not a git URL. So you first need to create `lctime.nix` that uses your fork, and then you can use it in the Nix flake, afaik.
You can find some examples at nix-eda: https://github.com/fossi-foundation/nix-eda/tree/main/nix

Best to ask that question on [FOSSi Chat](https://fossi-chat.org), by the way. Donn, our Nix expert, might be able to help you :)

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message-1503151994678935754

2026-05-10T21:49:22.745+00:00 — Lofty (@ravenslofty)

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(I have come to have feelings about lctime...)
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message-1503153034623193128

2026-05-10T21:53:30.687+00:00 — Tholin (@tholin)

Content

I tried not using nix and just installing the required packages directly into the ubuntu container
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message-1503153104827191387

2026-05-10T21:53:47.425+00:00 — Tholin (@tholin)

Content

Since very few are required for this
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message-1503153215527456940

2026-05-10T21:54:13.818+00:00 — Tholin (@tholin)

Content

But the version of magic that installs through apt is too old
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message-1503153291062677505

2026-05-10T21:54:31.827+00:00 — Tholin (@tholin)

Content

And if I build magic from source, it somehow behaves differently than the version from the package manager?
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message-1503153733897293974

2026-05-10T21:56:17.407+00:00 — Tholin (@tholin)

Content

I don’t think its parsing the environment variables in this

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message-1503153741606551682

2026-05-10T21:56:19.245+00:00 — Dory (@dorythecat_v2)

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This actually happened to me on Fedora too. Turns out the magic repo for the package managers is a different repo than the "normal" one
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message-1503153794232352869

2026-05-10T21:56:31.792+00:00 — Dory (@dorythecat_v2)

Content

God knows why but the artifacts are built from what's effectively a different branch
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message-1503153926793461800

2026-05-10T21:57:03.397+00:00 — Dory (@dorythecat_v2)

Content

For Ubuntu just follow the instructions on Magic's website, it's your safest bet. I ended up doing an Ubuntu distrobox and that worked
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message-1503154255094349894

2026-05-10T21:58:21.67+00:00 — Tholin (@tholin)

Content

I was missing the tcl and tk dev packages, I think
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message-1503156956255486114

2026-05-10T22:09:05.677+00:00 — Tholin (@tholin)

Content

Look! No nix!

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message-1503157121544618114

2026-05-10T22:09:45.085+00:00 — Tholin (@tholin)

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Characterization is next, I already did all the prerequisite work

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message-1503182315248025640

2026-05-10T23:49:51.732+00:00 — Tholin (@tholin)

Content

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message-1503182321640275989

2026-05-10T23:49:53.256+00:00 — Tholin (@tholin)

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Its taking a bit
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message-1503204718489505863

2026-05-11T01:18:53.081+00:00 — namibj

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I almost accidentally made a broken DAC :ferrisBallSweatSpin:
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message-1503205029622976623

2026-05-11T01:20:07.261+00:00 — namibj

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deviated from binary radix in the wrong direction.... good thing alarm bells rung while trying to validate drive strength of SCL latches for use as bit feeds
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message-1508950172829352106

2026-05-26T21:49:16.141+00:00 — HardWall (@hardwall)

Content

I'll just leave this here:

https://pavona.org/

Not sure I understand exactly what they're trying to do, seems an off-shoot of zero-risc, but it's... interesting.

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message-1511984759843192862

2026-06-04T06:47:38.065+00:00 — Andrew Wingate (@anfroholic)

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Looking like Tiny Tapeout may need a second slot 👍

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message-1511991573271937024

2026-06-04T07:14:42.513+00:00 — tnt (@246tnt)

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@Andrew Wingate Repo already ready https://github.com/TinyTapeout/tinytapeout-gf-26b 😅
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message-1511992342091927552

2026-06-04T07:17:45.814+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Content

:waferspace: Nice!!
You guys should consider showing more Open Shuttles on your homepage
https://www.tinytapeout.com/

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message-1511992988442558474

2026-06-04T07:20:19.916+00:00 — tnt (@246tnt)

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But they're not open yet 😅  ( As in, you can't submit it yet ).

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message-1514150112794902611

2026-06-10T06:11:58.439+00:00 — Andrew Wingate (@anfroholic)

Content

100% filled!!
That's awesome Tiny Tapeout Team!!!

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message-1516062454285729804

2026-06-15T12:50:56.18+00:00 — Thorben (@thorben_61995)

Content

Who from this crowd is going to be at FSiC 2026 (https://wiki.f-si.org/index.php/FSiC2026) in Ljubljana in three weeks? I see that at least @Leo Moser (mole99), @Simi, @Chips4Makers aka Staf Verhaegen and myself are giving presentations there. Anybody else presenting or attending?

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message-1516065314176241715

2026-06-15T13:02:18.031+00:00 — tnt (@246tnt)

Content

👋
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message-1516065345117618176

2026-06-15T13:02:25.408+00:00 — tnt (@246tnt)

Content

I'm presenting too.

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message-1516065658792706098

2026-06-15T13:03:40.194+00:00 — tnt (@246tnt)

Content

I'm presenting work I did on a custom SRAM register file on sky130 and the test chips are currently with fedex which was supposed to delivery today but delayed it to tomorrow ... result of which will decide if my talk is going to be a post-mortem or not 😅

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2026-06-15T13:04:09.2+00:00 — Thorben (@thorben_61995)

Content

Ah yes, right on Monday morning, I see. Looking forward to it 😊
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2026-06-15T13:05:32.643+00:00 — tnt (@246tnt)

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Wait, are you  Thorben Moos btw ?
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2026-06-15T13:06:38.615+00:00 — Thorben (@thorben_61995)

Content

Yes
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message-1516066474366603386

2026-06-15T13:06:54.642+00:00 — tnt (@246tnt)

Content

Oh your bio link seems to indicate yes 😅   When looking at the program I had noticed someone else was coming from Belgium and even more from my Alma Mater

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2026-06-15T13:08:11.656+00:00 — tnt (@246tnt)

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Did you do the bonding at Winfab ?  I was pondering pinging Christian (Renaux) about getting some time on the bonding machine if I ever needed to ...
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message-1516068395190190141

2026-06-15T13:14:32.602+00:00 — Thorben (@thorben_61995)

Content

Ha, very nice, did not know you're from here 😁 Yes, Christian from Winfab brought me the bonded samples on Friday. They are a little bit protective of their bonding machine at the moment, but as far as I know it's not used too much. And they seem to be getting a new semi-automated one soon (for some definition of soon). Then there's probably more availability and you have a fallback if one is temporarily out of order.
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2026-06-15T13:18:47.126+00:00 — tnt (@246tnt)

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Yeah, I studied there INGI then ELEC (was still FSA at the time).  And worked for intopix (a ucl spinoff) even before it was spunoff and I so I was in Maxwell for a year or so and also did some odd jobs for Quisquater and FX 🙂
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message-1516070125814681763

2026-06-15T13:21:25.215+00:00 — Thorben (@thorben_61995)

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Cool, will be a pleasure to chat with you in Slovenia 🙂

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2026-06-15T13:22:12.162+00:00 — tnt (@246tnt)

Content

Same 😄
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message-1516071612292661359

2026-06-15T13:27:19.619+00:00 — namibj

Content

now that I'm no longer actively suffering from whatever that bread contained, let's hurry back to get this serializer worked on before anything is too late for it.
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message-1516077537535463578

2026-06-15T13:50:52.307+00:00 — namibj

Content

VCO core, with enough fingers to let me tap off a single-finger feed to a clock tree without this causing undue load, probably do be aiming at exactly the 2.5 GHz though, maybe probably better like 3 GHz to handle a bit of layout parasitics and process variation.

Then clock buffer.
Then a latch fast enough to accomplish a DIV2 off of this.
Then a mux2 at least that would act as the final MUX in a C2 arrangement.
Then draw at least a plain serializer MUX tree up to have a fallback to submit; the base clock buf cells should be sufficient speed.

After, see how much time is left,
and see how good an inductor would be needed to clock the input-multiplexed current-mode C4 MUX (the pseudo-nmos style architecture of it).
If success, try to make an inductor that's good enough for pulling off a C4 architecture.
If success, go and implement the C4 with FIR taps furnished at the CLK/2 level (i.e., C8).

If inductor trials not success, instead go for some FIR taps at still CLK/2.
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message-1516077917749248051

2026-06-15T13:52:22.957+00:00 — tnt (@246tnt)

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You're not targetting gf0p3 are you ?
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message-1516078390048723014

2026-06-15T13:54:15.562+00:00 — namibj

Reply/reference

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Well, kinda; thanks for me realizing now that it's not a week but just 4 days.
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message-1516411601023008900

2026-06-16T11:58:19.249+00:00 — Andrew Wingate (@anfroholic)

Content

Gave a lightning talk at the Chicago Python Users Group (Chipy)
Hard to talk about much of anything in 5 min, but figured I'd share
https://youtu.be/0ROkPEg5Jl8

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message-1516488833754202286

2026-06-16T17:05:12.967+00:00 — namibj

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Oscillation success:

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message-1516522578649284682

2026-06-16T19:19:18.377+00:00 — namibj

Content

clock buffer at FO4, though with limited fancyness of harness

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message-1516523421897457796

2026-06-16T19:22:39.423+00:00 — namibj

Content

food break; then a latch that can DIV2 off of that.
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2026-06-16T19:44:38.9+00:00 — namibj

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forward device's drain current density oscillating between approximately 16 and 72 A/m
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message-1516536004847210658

2026-06-16T20:12:39.432+00:00 — namibj

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thanks past-me for making a plan so present-me doesn't wander off of the minimum-viable-submission route.
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message-1516573719202631783

2026-06-16T22:42:31.235+00:00 — namibj

Content

pair of latches be DIV2-ing

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message-1516639488326107227

2026-06-17T03:03:51.816+00:00 — namibj

Content

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2026-06-17T03:10:09.892+00:00 — namibj

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16 half speed latches @ approx 100 mW each + 4 full-speed latches @ approx 400 mW each + 4 full-speed MUX2 @ somewhere_between_those each, so a "total" of 3.6 ~ 4.8 mW, not counting the clock feed (quadrature phases at both full clock and half clock), and not counting the output predriver limiting amplifier
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message-1516879859698237671

2026-06-17T18:59:00.817+00:00 — namibj

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yeah I don't want to draw the rest by hand, real ugly to tune that way....

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message-1517004354815787010

2026-06-18T03:13:42.766+00:00 — Andrew Wingate (@anfroholic)

Content

I designed some silicon lol.
Maybe I will talk about it someday, this was more of an exercise than something I care about.

A portion of the above was to understand the toolchain so I could make this docker based starter thing.
Some people have asked me for it, so now it exist @carlfk

https://github.com/evezor/wafer_space_docker_based_starter_kit
If someone would mind giving it a quick overview, that would be lovely.
Thanks and hope it's helpful!

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message-1518150107718221905

2026-06-21T07:06:31.545+00:00 — Andrew Wingate (@anfroholic)

Content

@needsadrink|woke Tim is asking me to look into getting the old Skywater masks from the google mpw run.
Would you mind giving me a little assistance there? Please DM me.
Thanks

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message-1518514897296687154

2026-06-22T07:16:04.158+00:00 — Tim 'mithro' Ansell (@mithro_)

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How do you draw these diagrams? Just by hand in some tool or?
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message-1518573269291241543

2026-06-22T11:08:01.126+00:00 — Matt Venn (@mattvenn)

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looks like draw.io to me
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message-1518579648248942622

2026-06-22T11:33:21.988+00:00 — namibj

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Hand in drawio.
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message-1518579825999351999

2026-06-22T11:34:04.367+00:00 — namibj

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I'd prefer a less-hand way to get free verification out of it.
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message-1518579975987527710

2026-06-22T11:34:40.127+00:00 — namibj

Content

I can send you the source this evening if you want.
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message-1518852373005602877

2026-06-23T05:37:04.637+00:00 — Trevor Peyton (@trev5514)

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Check out https://github.com/hneemann/digital !

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message-1518872373682507847

2026-06-23T06:56:33.17+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Cool!
There's also Wokwi which you can use to create designs for Tiny Tapeout
https://tinytapeout.com/digital_design/wokwi/

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message-1518874837697957889

2026-06-23T07:06:20.637+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

For smallish things netlistsvg worked okay for a while
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message-1518885791051415612

2026-06-23T07:49:52.12+00:00 — Trevor Peyton (@trev5514)

Content

As a follow up, https://github.com/logisim-evolution/logisim-evolution this is an alternative program also. I used Digital when I was at uni and it was really nice.

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message-1520005841384640584

2026-06-26T10:00:32.929+00:00 — namibj

Content

I'm melting 🙁

But I do see hope for the 4:1 MUX (and required clocking feed) getting tested as part of Run2.

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message-1520006096096464896

2026-06-26T10:01:33.657+00:00 — Tholin (@tholin)

Content

40 tomorrow, 39 sunday
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message-1520006114941468822

2026-06-26T10:01:38.15+00:00 — Tholin (@tholin)

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Gonna have a fun weekend
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message-1520006185116237916

2026-06-26T10:01:54.881+00:00 — Tholin (@tholin)

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But not gonna stop working
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message-1520017824720879616

2026-06-26T10:48:09.979+00:00 — namibj

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I'll ask and if I'm lucky I'll figure out how to remote into my workstation from the office 😉

Would be awesome for the heatwave situation.
Should just need a sufficiently effective codec to keep my sanity despite the inevitable lag.
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message-1520446083178696775

2026-06-27T15:09:54.752+00:00 — gojimmypi

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For all the Visual Studio developers out there: I've released my best ever version of the Verilog Syntax Highlighter Extension.

https://marketplace.visualstudio.com/items?itemName=gojimmypi.gojimmypi-verilog-language-extension

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message-1520677791174234214

2026-06-28T06:30:38.243+00:00 — nmz787

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hopefully low humidity!
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message-1521330769551953950

2026-06-30T01:45:20.42+00:00 — BreakingTaps (@polyfractal)

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not perfect, but pretty happy how this turned out 🙂

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message-1521339917475778660

2026-06-30T02:21:41.455+00:00 — Andrew Wingate (@anfroholic)

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Looks great!!

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message-1521869130217685182

2026-07-01T13:24:35.605+00:00 — Deepak (@deempak)

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Can i add custom chip art on the top and bottom right corner ( similar to the wafer space logo and qr in the left ) ? Or can i only add inside the pad ring ?
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message-1521915608055283763

2026-07-01T16:29:16.785+00:00 — BreakingTaps (@polyfractal)

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yep, you can! I have a little image on the bottom right of mine. I think the top right may be reserved for an arrow this time around (to help the wirebonding alignment) so I think we can't use that corner

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message-1521943159871901897

2026-07-01T18:18:45.65+00:00 — Deepak (@deempak)

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Hey sure got it thank you much Will use only the bottom right

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message-1521945329690480722

2026-07-01T18:27:22.975+00:00 — Leo Moser (mole99) (@mole99)

Content

You are also free to replace the wafer.space logo on the top left. The precheck only checks the bottom left and the top right, if you have CoB enabled.
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message-1522359990252343306

2026-07-02T21:55:05.757+00:00 — BreakingTaps (@polyfractal)

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hah, I was skimming an old Adapteva parallela forum post looking for something and saw @tnt. Guess I shouldn't be surprised 🙂
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message-1522360587680481371

2026-07-02T21:57:28.195+00:00 — tnt (@246tnt)

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@BreakingTaps Good old times 😅

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message-1522364659129389280

2026-07-02T22:13:38.904+00:00 — cartertu160rner

Content

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message-1522826808960094309

2026-07-04T04:50:04.01+00:00 — BreakingTaps (@polyfractal)

Content

Chinese open source 55nm PDK? https://github.com/openecos-projects/icsprout55-pdk

(Found via https://mp.weixin.qq.com/s/hDV_g7wtZvxg2IIAZ1XvGA)

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message-1522829851285913700

2026-07-04T05:02:09.357+00:00 — tnt (@246tnt)

Content

@BreakingTaps It was mentionned at FSiC last year but ... Not really open. If you look at it there is not much there. You get a standard cell library but only abstract view, no GDS. No DRC rules or any device simulation model.  So you can "assemble" a chip with purely digital design but nothing more, nothing custom, ...

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message-1522830021692227674

2026-07-04T05:02:49.985+00:00 — tnt (@246tnt)

Content

So you can do basically the same you can do with a FPGA.
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message-1522830374076416000

2026-07-04T05:04:14+00:00 — BreakingTaps (@polyfractal)

Content

ah, welp
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message-1522830464627249263

2026-07-04T05:04:35.589+00:00 — BreakingTaps (@polyfractal)

Content

maybe some day we'll get a 50-65nm open PDK
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message-1522992896414978221

2026-07-04T15:50:02.345+00:00 — Andrew Wingate (@anfroholic)

Content

I'll just leave this here....
-# Sometimes I feel I should not be allowed to use tools

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message-1522993098375037098

2026-07-04T15:50:50.496+00:00 — Andrew Wingate (@anfroholic)

Content

It's DRC clean btw
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message-1523005813155958854

2026-07-04T16:41:21.936+00:00 — BreakingTaps (@polyfractal)

Content

haha that's amazing. i can't imagine making it DRC clean too 😄

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message-1523131817576890408

2026-07-05T01:02:03.731+00:00 — Machine Kid myyerrol (@myyerrol)

Content

Next week at FSiC 2026, we'll be introducing the latest updates on the ics55 pdk, eda tools, and design platform, etc. We have also upgraded the ics55 pdk from tier1 to tier 0. Moving forward, we're planning the roadmap, restructuring the repo based on sky130, gfmcu180, ihp130, and will be gradually releasing the remaining files over the next some months.
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message-1523138496829718549

2026-07-05T01:28:36.189+00:00 — Essen (@essen__)

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Maybe we should indeed re-evaluate your permission to use tools 🤣

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message-1524066089812754553

2026-07-07T14:54:31.59+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Are you connected to ics55 in some way?
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message-1524276907376377976

2026-07-08T04:52:14.414+00:00 — Machine Kid myyerrol (@myyerrol)

Content

Yes, we have integrated the ics55 pdk to ECOS Studio, but now it can only generate partial gds because of some key files haven't be released, so we need to do some works (like DRC/LVS/PEX) by ourselves.
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message-1524278435902390354

2026-07-08T04:58:18.843+00:00 — Machine Kid myyerrol (@myyerrol)

Content

I read the IHP's slide at the FSiC 2026, their pdk and open mpw shuttle is fantastic, so we will learn from ihp sg13g2, to port more open-source eda tools to ics55, and release remaining data as soon as possilbe.
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message-1524279979968303184

2026-07-08T05:04:26.977+00:00 — Machine Kid myyerrol (@myyerrol)

Content

And "EuroCDP Open-source PDKS and EDA tooling  recommendations" book also give us great help-a good comparison table.
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message-1524280391542902904

2026-07-08T05:06:05.104+00:00 — Machine Kid myyerrol (@myyerrol)

Content

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message-1525692972824264856

2026-07-12T02:39:10.726+00:00 — Essen (@essen__)

Content

There was an attempt at compression ...
```
-rw-r--r--  1 gp gp 754346 Jul 11 21:24 chip_top.oas
-rw-r--r--  1 gp gp 727632 Jul 11 21:24 chip_top.oas.gz
```
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message-1525738832555933847

2026-07-12T05:41:24.538+00:00 — A44 (@a446949)

Content

Has anyone figured out an easy way to do GDS art?
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message-1525742330815054067

2026-07-12T05:55:18.588+00:00 — kcolley

Reply/reference

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at least the size went down and not up! 😄

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message-1525853301973975123

2026-07-12T13:16:16.174+00:00 — Essen (@essen__)

Reply/reference

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Pixel art in magic 👌 ... Okay there might be simpler ...
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message-1525863129194696835

2026-07-12T13:55:19.166+00:00 — TheZoq2 (@thezoq2)

Reply/reference

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Have a look at the FSiC talks from last year, there was one on how the pulp team do their art
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message-1526308296666124349

2026-07-13T19:24:15.362+00:00 — Essen (@essen__)

Content

The current diet: I am sure I can live off this for a few more days ...

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message-1526660695624515696

2026-07-14T18:44:33.821+00:00 — vpro

Reply/reference

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I miss HEB 😭
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message-1526660853045399672

2026-07-14T18:45:11.353+00:00 — vpro

Content

Sometimes I have dreams about HEB salsa, those are good dreams
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2026-07-14T19:03:42.445+00:00 — Essen (@essen__)

Reply/reference

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Started a thread.
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message-1527136616190181426

2026-07-16T02:15:42.126+00:00 — Andrew Wingate (@anfroholic)

Content

just cuz

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message-1527327125420642406

2026-07-16T14:52:43.066+00:00 — BreakingTaps (@polyfractal)

Content

that's a great shot!

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message-1527329817274486854

2026-07-16T15:03:24.854+00:00 — Essen (@essen__)

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Content

Comes out so well ! 😍

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message-1527692670175023245

2026-07-17T15:05:15.727+00:00 — asic destroyer (@logic_destroyer)

Content

@Tim 'mithro' Ansell @Leo Moser (mole99) @Andrew Wingate
https://bsky.app/profile/did:plc:ux7kshhvcz763o5eu7rzggig/post/3mqtzirifck2p

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message-1527692979920175234

2026-07-17T15:06:29.576+00:00 — Leo Moser (mole99) (@mole99)

Content

This is so cool to see! 👏

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message-1527779240198672454

2026-07-17T20:49:15.629+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1527779507774423181

2026-07-17T20:50:19.424+00:00 — asic destroyer (@logic_destroyer)

Content

7 hours uptime and still running linux

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message-1527830575103217695

2026-07-18T00:13:14.824+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@asic destroyer - That is in no way off-topic! That is #general content.

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message-1527831095498903573

2026-07-18T00:15:18.896+00:00 — BreakingTaps (@polyfractal)

Content

very impressed you have a working DRAM controller! from the little I've dabbled it feels very non-negligible achievement!

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message-1527839822788431973

2026-07-18T00:49:59.644+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

I got lucky that everything just fit. In the end it used the very last pin.

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message-1528168609103478944

2026-07-18T22:36:28.41+00:00 — asic destroyer (@logic_destroyer)

Content

How hot do your chips get? I'm measuring 35°C on the top surface of the chip.
@Leo Moser (mole99) @Andrew Wingate @BreakingTaps @RebelMike @Tholin @Greg ...
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message-1528168851412615330

2026-07-18T22:37:26.181+00:00 — Tholin (@tholin)

Content

What clock speed?
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message-1528169039631880272

2026-07-18T22:38:11.056+00:00 — asic destroyer (@logic_destroyer)

Content

I hadn't even thought of that. Right now I'm still running at 24 MHz because I'm too lazy to hook up an external clock. But in theory, 35–40 MHz should be achievable.
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message-1528169964631228466

2026-07-18T22:41:51.593+00:00 — Tholin (@tholin)

Content

35° is normal at 24MHz

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message-1528170093341577296

2026-07-18T22:42:22.28+00:00 — asic destroyer (@logic_destroyer)

Content

@Tholin  Looking at how power scales with frequency, I figure the chip would end up at around 45°C at most. That should still be fine, right?
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message-1528170194214584442

2026-07-18T22:42:46.33+00:00 — Tholin (@tholin)

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Yes
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message-1528170226208997536

2026-07-18T22:42:53.958+00:00 — asic destroyer (@logic_destroyer)

Content

thanx
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message-1528172283531755721

2026-07-18T22:51:04.462+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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I thought the chip might be running a bit hotter because of all the I/O activity.
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message-1528225934279442524

2026-07-19T02:24:15.797+00:00 — Andrew Wingate (@anfroholic)

Content

Cross posting a message from @Tim Edwards
> Calling on all analog designers. . . the Chipalooza Challenge is back! Looking for high-quality open source analog circuits that support system-on-chip. This is a 2-year-long project with five individual challenges covering the three major open source PDKs, with the goal of making SoC designs with analog components portable across all of the major open PDKs. It costs nothing but your (valuable) design time, and awards will be given for successful completed circuits. To participate, join the https://fossi-chat.org forum and go to hashtag#Chipalooza for details and updates!

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message-1528386951609188404

2026-07-19T13:04:05.32+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

@Tim 'mithro' Ansell @Leo Moser (mole99) @Andrew Wingate

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message-1528398567859818704

2026-07-19T13:50:14.85+00:00 — BreakingTaps (@polyfractal)

Content

I haven't clocked mine faster than like 5hz so far 😄 so not sure how hot it will get. need to carve out some more time to work on bringup

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message-1528407258319425556

2026-07-19T14:24:46.817+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Chipalooza Challenge is off-topic for now but there will be a GF180MCU/Wafer.Space version of it coming soon enough.
@Andrew Wingate :  Thanks for posting!
@Tim 'mithro' Ansell :  My proposed schedule assumes a Wafer.Space tapeout some time around Feb. 1 next year, so if that target is way off the mark, please let me know.  I am also targeting a 2nd Wafer.Space tapeout Aug. 1 of next year, which is even more of a wild guess.
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message-1528408842566897846

2026-07-19T14:31:04.531+00:00 — Andrew Wingate (@anfroholic)

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Sure thing, sounds awesome. DM'd you a bit about super rough timing outlines.
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2026-07-21T21:20:10.244+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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At 24 MHz, the board draws **80 mA** under normal operation and **100 mA** when accessing the SD card over SPI.

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message-1529280485430137012

2026-07-22T00:14:40.384+00:00 — Tim 'mithro' Ansell (@mithro_)

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Dunno if that is good or bad? 😛
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message-1529280976578937004

2026-07-22T00:16:37.483+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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good! sdram, mcu, led, sd card, uart, regulator,  flash , wires , pcb and asic
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message-1529554239116808243

2026-07-22T18:22:28.349+00:00 — asic destroyer (@logic_destroyer)

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If there's a 28 nm process available, I'd love to build it.

https://bsky.app/profile/logicdestroyer.bsky.social/post/3mravzo3xqk2r

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message-1529911527577092276

2026-07-23T18:02:12.556+00:00 — Andrew Wingate (@anfroholic)

Content

If any of you will be at **Teardown 2026** I'd love to meet you!
Come find me.
I have also been asked to talk and will have the Sat 1:30 slot.
My slides can be seen here: https://anfroholic.github.io/teardown2026_talk

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2026-07-24T07:39:46.562+00:00 — Essen (@essen__)

Reply/reference

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Started a thread.
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message-1530299945830322287

2026-07-24T19:45:38.684+00:00 — asic destroyer (@logic_destroyer)

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https://bsky.app/profile/logicdestroyer.bsky.social/post/3mrfwa2dmjk2p

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2026-07-27T20:17:13.308+00:00 — asic destroyer (@logic_destroyer)

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message-1532907162265845770

2026-08-01T00:25:47.522+00:00 — asic destroyer (@logic_destroyer)

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message-1533328672537313500

2026-08-02T04:20:43.402+00:00 — Essen (@essen__)

Content

Run3 is open! 🎉
And I am now committed:

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message-1533631242258354428

2026-08-03T00:23:01.645+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Great writeup in Ars Technica on Bunnie Huang's Baochip for DEFCON:  https://arstechnica.com/security/2026/08/defcons-new-badge-is-a-security-key-you-can-see-inside/

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message-1533632024085139619

2026-08-03T00:26:08.047+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Essen :  Run 3 is off-topic??
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message-1533650957215203458

2026-08-03T01:41:22.057+00:00 — Essen (@essen__)

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Alright, maybe not my best work 😅
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message-1533766009872191548

2026-08-03T09:18:32.748+00:00 — Andrew Wingate (@anfroholic)

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Still great! Can't wait to see your design!!

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message-1533856021053702334

2026-08-03T15:16:13.086+00:00 — Essen (@essen__)

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Thanks @Andrew Wingate
On another subject, your meme chip is taking over the humor on my  side with phrases like `much food` and `wow fun` creeping into the discourse. 😅

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message-1533856310523859206

2026-08-03T15:17:22.101+00:00 — Andrew Wingate (@anfroholic)

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Very thanks!

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message-1533857961846505542

2026-08-03T15:23:55.807+00:00 — Essen (@essen__)

Reply/reference

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Much response 👌
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message-1534583731522633809

2026-08-05T15:27:52.782+00:00 — Essen (@essen__)

Content

Was it the process of up everything just to realize I ordered the wrong footprint on my ferrite bead and I don't have any replacements in stock ... vdm

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message-1535472622836654232

2026-08-08T02:20:00.986+00:00 — namibj

Content

FO2 buffer on IHP....
C4 clock of 25G....
Promising!
C8 of 10G should be eerily comfy that way (on gf180mcuD), and with enough luck a straight port of what comes for the IHP chipalooza, so.... yeah.....

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message-1535814064511651922

2026-08-09T00:56:47.025+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://github.com/xoreaxeaxeax/asm-hall-of-shame is pretty fun

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message-1535866108631056394

2026-08-09T04:23:35.31+00:00 — Essen (@essen__)

Content

kicad fail

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message-1536033342145962096

2026-08-09T15:28:06.887+00:00 — Andrew Wingate (@anfroholic)

Content

https://www.tomshardware.com/pc-components/cpus/owner-of-original-intel-8080-pre-production-layout-seeks-restorer-handcrafted-rubylith-mask-shows-5-000-transistors-and-interconnect-patterns-of-the-fabled-2-mhz-cpu

Embeds

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    "description": "The same computing history artifact was previously pictured alongside Andy Grove, Robert Noyce, and Gordon Moore in 1978.",
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    "title": "Owner of original Intel 8080 pre-production layout seeks restorer ...",
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