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Thread: Random thoughts about current bond pads

53 Discord messages from ℹ️ - Information/general/threads/random-thoughts-about-current-bond-pads.md.

Category: ℹ️ - Information Parent channel: #general Thread ID: 1498556045927125132

Messages: 53

message-1498556052247937085

2026-04-28T05:26:44.681+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) - Forgive me if these things are stupid / don't make sense but I had some random thoughts / ideas about ways we should probably modify the "default" template / setup for the padring / pads based on random theories from being at the bond house.
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message-1498559528915177492

2026-04-28T05:40:33.583+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Firstly, the pads seem like they are currently very close to the edge of the die. Looking through the microscope they kinda look like they almost connected to it. I assume they must not be, otherwise nothing would work but it was concerning the first time I looked at them.

Could we add a bit more space between the pads and the edge/seal ring?

I know it reduces the available silicon area but I /think/ it should help have more margin there.
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message-1498559789632848004

2026-04-28T05:41:35.743+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Secondly, do you know if the top polyimide layer overlaps the metal pad edges? IE Is something like this possible? https://docs.google.com/drawings/d/1YPRHE-uZNg3iSm3SlMcJvfinUueOHtiQbLqJo35Pt_M/edit -- If so could we increase the amount of overlap?

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message-1498572350160113824

2026-04-28T06:31:30.406+00:00 — Leo Moser (mole99) (@mole99)

Content

Will take a closer look later!
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message-1498574694344032277

2026-04-28T06:40:49.303+00:00 — tnt (@246tnt)

Content

Changing padring would mean we have an issue for TT because changing silicon area means we might need to change the size of tiles (and worst case, even size of power gates meaning we'd need to re-design them ... meaning closing the shuttle)
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message-1498575001857560727

2026-04-28T06:42:02.62+00:00 — tnt (@246tnt)

Content

The passivation already looks like that drawing. The metal pad is 65.35 um x 68 um  and tha passivation opening is 60 x 60 um.
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message-1498576099016441916

2026-04-28T06:46:24.203+00:00 — tnt (@246tnt)

Content

Distance from guard ring to pads meets `GR.2` ( It's 10 um from the marking layer and 11 um away from the actual pad ).   That's more than twice the clearance between pad and first power ring.
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message-1498578424237920287

2026-04-28T06:55:38.579+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - I'm thinking more along the lines of providing more margin in the "default - I just want something which works" configuration of the template.
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message-1498578677821214770

2026-04-28T06:56:39.038+00:00 — tnt (@246tnt)

Content

But that would move the bonding pads, hence the bonding setup.
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message-1498578695844139029

2026-04-28T06:56:43.335+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

But I also might be suggesting things which make no sense 😛
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message-1498579057162326056

2026-04-28T06:58:09.48+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - If I understand correctly, Tiny Tapeout/you are doing your own bonding (even if we are at the same place) - so that is not something that effects you?
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message-1498579070064267414

2026-04-28T06:58:12.556+00:00 — tnt (@246tnt)

Content

Do we have GDS from the chipathon or from the google GF runs to compare.
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message-1498579199819120651

2026-04-28T06:58:43.492+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - The Google GF shuttle GDS is at https://foss-eda-tools.googlesource.com/third_party/shuttle/gf180mcu
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message-1498579365791797380

2026-04-28T06:59:23.063+00:00 — tnt (@246tnt)

Content

Well one thing we were thinking about is to also offer the TT chips on the standard WS breakout for if people want to use in their own PCB. ( So you'd get the standard TT demo+breakout  and also TT chips on the WS breakout 😅  ).
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message-1498579861424570439

2026-04-28T07:01:21.231+00:00 — tnt (@246tnt)

Content

I think the repo above doesn't have seal ring and fill, this was added later by GF ?  Not sure if they sent back the altered gds ...
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message-1498579918555054182

2026-04-28T07:01:34.852+00:00 — tnt (@246tnt)

Content

( I can't check ... can't figure out how to actually download the files from the repo above .. )
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message-1498580161283756123

2026-04-28T07:02:32.723+00:00 — tnt (@246tnt)

Content

But let's see how it works out with the next set of wafers ...
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message-1498580230967656599

2026-04-28T07:02:49.337+00:00 — tnt (@246tnt)

Content

When do you think you'll start trying with those ?
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message-1498581053173010504

2026-04-28T07:06:05.366+00:00 — Tim 'mithro' Ansell (@mithro_)

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That would be cool!

I'm just throwing stuff out there. It might make sense to do some type of tests along these lines to see if they make any difference.
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message-1498581269389246558

2026-04-28T07:06:56.916+00:00 — Tim 'mithro' Ansell (@mithro_)

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I'm pretty sure if they did send back any altered gds it got lost inside efabless
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message-1498581506451443713

2026-04-28T07:07:53.436+00:00 — tnt (@246tnt)

Content

Someone here (on run 1, on this discord) getting one of the chip probably has equipment to do a cross section and SEM of the failure.
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message-1498581584922804245

2026-04-28T07:08:12.145+00:00 — tnt (@246tnt)

Content

Would be interested to see 😅
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message-1498586392631050290

2026-04-28T07:27:18.392+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

I'm guessing someone like @azonenberg or @BreakingTaps will eventually look into. I will try and make sure they have some samples.

I'm also trying to figure out if there are any failure analysis labs with SEMs in the Shenzhen area that are within my price range that we can get stuff done with too.
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message-1498604871199363113

2026-04-28T08:40:44.026+00:00 — azonenberg

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I am absolutely capable of doign a sem/fib section but would need work's approval since it would be on their gear
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message-1498604920239034388

2026-04-28T08:40:55.718+00:00 — azonenberg

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i have a friend across town with a fib 200 she's trying to bring up but it's not yet in usable condition
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message-1498667079753007194

2026-04-28T12:47:55.701+00:00 — BreakingTaps (@polyfractal)

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parallel lapping and cross-sectioning my chip are on the eventual-todo list (time permitting, have to do it after-hours at work)

What failure in particular would I be looking out for?
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message-1498673673052098671

2026-04-28T13:14:07.666+00:00 — tnt (@246tnt)

Content

@BreakingTaps Bond pad shorted to GND.

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message-1498699202757263481

2026-04-28T14:55:34.422+00:00 — azonenberg

Reply/reference

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is it just one pin on one chip? wire bonded or bare?
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message-1498699361725710567

2026-04-28T14:56:12.323+00:00 — tnt (@246tnt)

Content

@azonenberg No, I have 9 chips here, 6 have several failed bonds.
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message-1498699423683973322

2026-04-28T14:56:27.095+00:00 — azonenberg

Content

but randomly distributed, not the same bond pad on each?
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message-1498699502654066729

2026-04-28T14:56:45.923+00:00 — azonenberg

Content

any obvious pattern to failure locations?
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message-1498699522841251930

2026-04-28T14:56:50.736+00:00 — azonenberg

Content

e.g. power vs io
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message-1498699549903028346

2026-04-28T14:56:57.188+00:00 — azonenberg

Content

or one side of the package
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message-1498699662046134322

2026-04-28T14:57:23.925+00:00 — tnt (@246tnt)

Content

It's not the same bond no. But strangely they seem grouped on the same side of the chip ... it's not the same side on every chip but on a given chip I'll have 1 side perfect and another with all the failed bonds.
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message-1498699955685294321

2026-04-28T14:58:33.934+00:00 — tnt (@246tnt)

Content

( I'm only testing 2 sides because the samples I got have "survivor bias", they were the one passing the digital test which tests North/South side at the factory ... but the East/West were not tested at the factory ).
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message-1498700503033581729

2026-04-28T15:00:44.432+00:00 — azonenberg

Content

My first guess would be excessive force during the bonding process punching through layers
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message-1498700522516119553

2026-04-28T15:00:49.077+00:00 — azonenberg

Content

That should show nicely in a FIB section
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message-1498700538278187181

2026-04-28T15:00:52.835+00:00 — tnt (@246tnt)

Content

If @BreakingTaps has a multimeter, it's pretty easy to test .. Use diode more, put positive lead on GND on one of the cap, then probe along the connector for the IOs.  Good ones should show roughly 0.75V.

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message-1498700590111395911

2026-04-28T15:01:05.193+00:00 — azonenberg

Content

How wide is the bond pad?
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message-1498700667336790156

2026-04-28T15:01:23.605+00:00 — tnt (@246tnt)

Content

@azonenberg There is nothing underneath the pad. It would  need to be deformed to push inward to reach the power ring to be shorted to GND.
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message-1498700717802786928

2026-04-28T15:01:35.637+00:00 — azonenberg

Content

Substrate is grounded if it's punched hard enough
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message-1498700814624231555

2026-04-28T15:01:58.721+00:00 — tnt (@246tnt)

Content

True ... I didn't think about that.
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message-1498700923931852881

2026-04-28T15:02:24.782+00:00 — tnt (@246tnt)

Content

I did manage to clear a short using brute force. ( 8V / 3A to the IO ... now it works )
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message-1498701124558000239

2026-04-28T15:03:12.615+00:00 — tnt (@246tnt)

Content

Attachments

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message-1498701190928797737

2026-04-28T15:03:28.439+00:00 — tnt (@246tnt)

Content

Pad passivation opening is  60 x 60 um.
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message-1498701281751990365

2026-04-28T15:03:50.093+00:00 — tnt (@246tnt)

Content

And as noted above, ~4.6 um from the GND power rail.

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message-1498704182775910592

2026-04-28T15:15:21.751+00:00 — azonenberg

Reply/reference

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Content

lol. the rest of the chip works?
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message-1498705200389816440

2026-04-28T15:19:24.369+00:00 — azonenberg

Reply/reference

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I would be interested in seeing that die, tbh
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message-1498705261425070262

2026-04-28T15:19:38.921+00:00 — azonenberg

Content

there may be visible damage or melt marks
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message-1498705325090537653

2026-04-28T15:19:54.1+00:00 — azonenberg

Content

that might make an otherwise hard to find short more obvious
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message-1498708791389327421

2026-04-28T15:33:40.53+00:00 — tnt (@246tnt)

Content

Yes, rest of the chip works. And that pin now works too ( it was the `clk` input of TT ) ... I ran several designs with no issues.

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message-1498853589228195850

2026-04-29T01:09:03.025+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - Would the reverse bias 0.75V test work on any die which is using the standard GF IO?
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message-1498920675740614666

2026-04-29T05:35:37.696+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell Yes
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