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Thread: Not yet, it's mainly blinky and the test

16 Discord messages from ℹ️ - Information/general/threads/not-yet-its-mainly-blinky-and-the-test.md.

Category: ℹ️ - Information Parent channel: #general Thread ID: 1490719846084903163

Messages: 16

message-1490721451328798750

2026-04-06T14:34:50.262+00:00 — Leo Moser (mole99) (@mole99)

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message-1490721454889631985

2026-04-06T14:34:51.111+00:00 — Leo Moser (mole99) (@mole99)

Content

Well, before you go for a tapeout, it is probably a good idea to validate that the fabric can support more complex designs.

From what I can see, your switch matrix only has direct connections to neighboring tiles. You may need connections that span multiple tiles to improve connectivity, otherwise you may end up with unroutable situations.

After all, 90% of an FPGA is just the routing 😉
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message-1490722138389348465

2026-04-06T14:37:34.07+00:00 — The Computer Guy (@thecomputerguy)

Content

Yeah, I've been able to verify most of the design. I've asked a couple people to review and give feedback but I haven't heard back from them yet.
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message-1490722316122984651

2026-04-06T14:38:16.445+00:00 — The Computer Guy (@thecomputerguy)

Content

I'm mainly focused on making the tapeout workflow not be as heavy and slow.
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message-1490723137426555102

2026-04-06T14:41:32.259+00:00 — Leo Moser (mole99) (@mole99)

Content

I see! I really dig the automated and reproducible build of the chip. I use LibreLane to build the FABulous FPGA reproducibly as well, but I only use Nix for the tools.
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message-1490723417127649380

2026-04-06T14:42:38.945+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

BTW Have you seen my ramberlings in https://docs.google.com/document/d/1n2YaYvHRq6sSTN80jMbDDu8qRKy45c0DJyZbVrDrv_o/edit?tab=t.0 ?

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message-1490723432764018882

2026-04-06T14:42:42.673+00:00 — The Computer Guy (@thecomputerguy)

Content

Yeah so I looked at LibreLane and I see why it was made. However, I can get better utilization by splitting the tapeout workflow.
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message-1490723545704169594

2026-04-06T14:43:09.6+00:00 — The Computer Guy (@thecomputerguy)

Content

This is what I've been working on. Each tile gets taped out and everything is placed together at the end.

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message-1490723692215271635

2026-04-06T14:43:44.531+00:00 — The Computer Guy (@thecomputerguy)

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Interesting
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message-1490723785014509795

2026-04-06T14:44:06.656+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

See also my kinda silly spreadsheet at https://docs.google.com/spreadsheets/d/1KIqtzRaZbrWsbKwZqevY2elmVIz1gm5UJqOP75bxcOg/edit?gid=1500563840#gid=1500563840

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message-1490723955915493386

2026-04-06T14:44:47.402+00:00 — Leo Moser (mole99) (@mole99)

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Very nice! My LibreLane plugin also first implements the tile macros in parallel and then stitches the fabric: https://github.com/mole99/librelane_plugin_fabulous
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message-1490724210224533595

2026-04-06T14:45:48.034+00:00 — The Computer Guy (@thecomputerguy)

Content

I get the benefit of being able to use a Nix cache and I can cache things much easily.
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message-1490724379598786640

2026-04-06T14:46:28.416+00:00 — The Computer Guy (@thecomputerguy)

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Huh
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message-1490724598323351712

2026-04-06T14:47:20.564+00:00 — Tim 'mithro' Ansell (@mithro_)

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@The Computer Guy - Don't worry if it doesn't make sense, I was just thinking about the problem by trying to pack standard cells together to get 100% density and not actually doing anything useful.
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message-1490724690136928317

2026-04-06T14:47:42.454+00:00 — The Computer Guy (@thecomputerguy)

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Yeah, I was kinda gathering that
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message-1490725369056071927

2026-04-06T14:50:24.321+00:00 — Leo Moser (mole99) (@mole99)

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Yeah, that is a nice approach! I use Make to build the tiles. In theory, I could also only rebuild what is needed, however, that hasn't been necessary so far since implementing all tiles doesn't take that long. But it's a good future improvement.

I also cache the tiles in the CI, see here for the HeiChips fabric: https://github.com/FPGA-Research/heichips25-tapeout/actions/runs/23842507549
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