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Thread: I managed to persuade pdngen to connect

24 Discord messages from ℹ️ - Information/general/threads/i-managed-to-persuade-pdngen-to-connect.md.

Category: ℹ️ - Information Parent channel: #general Thread ID: 1410252190282678284

Messages: 24

message-1410252312555028652

2025-08-27T13:19:12.534+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1410252315264417812

2025-08-27T13:19:13.18+00:00 — Leo Moser (mole99) (@mole99)

Content

The trick (or problem) is that the DVDD/DVSS pins are all on Metal2, which means the PDN ring will only connect to the pads via Metal2. Metal2 is vertical by default, which means we can only have I/O power/ground cells in the northern or southern I/O row (in the current setup, I hope we can change this).
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message-1410252372957069343

2025-08-27T13:19:26.935+00:00 — Leo Moser (mole99) (@mole99)

Content

This example design now runs through the whole flow without any problems, except that netgen LVS fails since the power/ground pins are not yet properly represented in the PNL.
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message-1410252472588566569

2025-08-27T13:19:50.689+00:00 — Leo Moser (mole99) (@mole99)

Content

@tnt I think you looked into overriding the preferred directions in pdngen at some point? Did you manage to achieve this?
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message-1410252619066249226

2025-08-27T13:20:25.612+00:00 — Leo Moser (mole99) (@mole99)

Content

@htamas I noticed that you have some `CONNECT_POWER_PADS` defines in your code. Did you manage to get the PNL to properly connect the core PDN to the I/O power/ground bondpad pins?
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message-1410252707960193034

2025-08-27T13:20:46.806+00:00 — Leo Moser (mole99) (@mole99)

Content

I'm gonna upload this repo soon to the wafer.space GitHub with a WIP PDK so anyone can reproduce this with the LibreLane padring step.
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message-1410254307466678363

2025-08-27T13:27:08.158+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) No, I didn't manage to do it, it's pretty wired down everywhere ...   and in the end the IHP guys changed the direction in the tech LEF 😅
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message-1410255682703458345

2025-08-27T13:32:36.04+00:00 — Leo Moser (mole99) (@mole99)

Content

Well, that's one solution 😄

Actually, I think the `add_pdn_ring -connect_to_pads` function should be more flexible. If we have a core ring with Metal5 and Metal4, it should still be able to make all connections with Metal2 and then drop vias. Maybe this function just needs another argument to override this. I'll ask the folks at OpenROAD what they think about this.
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message-1411401048547131502

2025-08-30T17:23:52.537+00:00 — Leo Moser (mole99) (@mole99)

Content

I got the power/ground bondpads connected and LVS to match 👏
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message-1411401157003444254

2025-08-30T17:24:18.395+00:00 — Leo Moser (mole99) (@mole99)

Content

@htamas In your padring script, I saw that you used `place_io_terminals` to place the BTerms for the I/O pads, since the bondpads are integrated into the cells (as opposed to IHP):

```
place_io_terminals gf180mcu_fd_io__*/DVSS
place_io_terminals gf180mcu_fd_io__*/DVDD
```

It seems that `place_io_terminals` simply promotes the first pin of the specified port to a BTerm.
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message-1411401179925184532

2025-08-30T17:24:23.86+00:00 — Leo Moser (mole99) (@mole99)

Content

For the default power/ground pads that would be one of the pins on the side, resulting in this:
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message-1411401227786518723

2025-08-30T17:24:35.271+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1411401305083215922

2025-08-30T17:24:53.7+00:00 — Leo Moser (mole99) (@mole99)

Content

It turns out that the power/ground pads don't even have pins at the bondpad locations, so by default the `place_io_terminals` command cannot work as we want it to work.

Therefore, I tried to add a `PAD` port, just like the other I/O pads, which initially seemed to work fine: I could global-connect it to the respective VDD/VSS net. However, PSM would throw an error, because there is no physical connection between PAD and any of the power pins.

```
[18:32:56] ERROR    [PSM-0069] Check connectivity failed on VDD.
[18:33:07] ERROR    [PSM-0069] Check connectivity failed on VSS.
```
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message-1411401404593213461

2025-08-30T17:25:17.425+00:00 — Leo Moser (mole99) (@mole99)

Content

So instead I added another pin to the DVSS/DVDD ports that matches the location of the bondpads (same as PAD) and is listed as the first pin in the LEF file. This way `place_io_terminals` promotes the correct pin to a BTerm.

However, instead of:

```
place_io_terminals gf180mcu_fd_io__*/DVSS
place_io_terminals gf180mcu_fd_io__*/DVDD
```

We have to write:

```
place_io_terminals gf180mcu_fd_io__dvss*/DVSS
place_io_terminals gf180mcu_fd_io__dvdd*/DVDD
```

As otherwise we would still get one BTerm at the side of the power/ground pad.
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message-1411401460440367104

2025-08-30T17:25:30.74+00:00 — Leo Moser (mole99) (@mole99)

Content

With this change the PDN is complete:
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message-1411401489586327582

2025-08-30T17:25:37.689+00:00 — Leo Moser (mole99) (@mole99)

Content

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message-1411401526529884161

2025-08-30T17:25:46.497+00:00 — Leo Moser (mole99) (@mole99)

Content

PSM is happy:

```
[INFO PSM-0040] All shapes on net VDD are connected.
[INFO PSM-0040] All shapes on net VSS are connected.
```

And netgen as well:

```
Final result:
Circuits match uniquely.
```

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message-1411401665273266369

2025-08-30T17:26:19.576+00:00 — Leo Moser (mole99) (@mole99)

Content

I think that would be reasonable change in the PDK. What do you think @tnt @htamas @Tholin?
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message-1411404600610656318

2025-08-30T17:37:59.415+00:00 — htamas (@h.tamas)

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Content

Sounds good to me, thanks for figuring it out.

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message-1411405175037493270

2025-08-30T17:40:16.369+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks, your script was really helpful!
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message-1411406382087012504

2025-08-30T17:45:04.152+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) ack.
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message-1411407285707739176

2025-08-30T17:48:39.592+00:00 — Tholin (@tholin)

Content

Definitely a less scuffed solution than me giving the power/ground IO cells tails.
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message-1411407411809484800

2025-08-30T17:49:09.657+00:00 — Tholin (@tholin)

Content

And tricking pdngen into thinking those tails are part of the PDN grid.
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message-1411408857711775794

2025-08-30T17:54:54.387+00:00 — Leo Moser (mole99) (@mole99)

Content

Sounds good then. I'll update the LEF view of `gf180mcu_fd_io__dvss` and `gf180mcu_fd_io__dvdd` to add the pin geometry.

Reactions

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