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Thread: Hi @azonenberg , I am currently

150 Discord messages from ℹ️ - Information/general/threads/hi-azonenberg-i-am-currently.md.

Category: ℹ️ - Information Parent channel: #general Thread ID: 1531770318237204500

Messages: 150

message-1531770440932917279

2026-07-28T21:08:52.037+00:00 — Essen (@essen__)

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message-1531770444535824636

2026-07-28T21:08:52.896+00:00 — Essen (@essen__)

Content

As I understand it, there are 3 modes for the test pattern generation:
- PRBS
- square
- pseudo-random (scrambler)
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message-1531770796295454940

2026-07-28T21:10:16.762+00:00 — azonenberg

Content

PRBS is pseudorandom
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message-1531770837080740073

2026-07-28T21:10:26.486+00:00 — azonenberg

Content

but using specific standardized LFSRs in particular
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message-1531771051959259280

2026-07-28T21:11:17.717+00:00 — azonenberg

Content

I have an FPGA-proven 10GbaseR MAC/PCS that would be straightforward to add a few resets to and get working in ASIC, the scrambler block has already been ported successfully to TS28HPC+ and used with a commercial SERDES
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message-1531771180070211615

2026-07-28T21:11:48.261+00:00 — azonenberg

Content

I wouldn't waste time thinking about Ethernet for this stage of things though. Focus on the PHY
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message-1531771238073106544

2026-07-28T21:12:02.09+00:00 — azonenberg

Content

the line coding and framing is a solved problem once we get the PHY working
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message-1531771264400883713

2026-07-28T21:12:08.367+00:00 — azonenberg

Content

I could write the missing pieces in an afternoon
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message-1531771382684192858

2026-07-28T21:12:36.568+00:00 — azonenberg

Content

if you can generate and read back PRBS7 and PRBS31 that should be sufficient

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message-1531771541967339702

2026-07-28T21:13:14.544+00:00 — azonenberg

Content

We can worry about whatever comes downstream of the transceiver on a future chip
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message-1531771681972945089

2026-07-28T21:13:47.924+00:00 — azonenberg

Content

or bolt on an experimental MAC/PCS but it wont be the focus of testing
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message-1531771705167708262

2026-07-28T21:13:53.454+00:00 — Essen (@essen__)

Content

Alright, I also have a 10GBASE-R PCS, but it hasn't been successfully taped out, so yours is safer.
Is the code for it public ? Mind if I torture it ?
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message-1531771827586859028

2026-07-28T21:14:22.641+00:00 — azonenberg

Content

It is public and on azonenberg/antikernel-ipcores on github, dont have the full link handy. again, it was written for FPGA and will need a little bit of tweaking
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message-1531771906561278012

2026-07-28T21:14:41.47+00:00 — azonenberg

Content

but i have successfully got it running at one point or other on efinix titanium, xilinx kintex-7, and xilinx ultrascale+
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message-1531771942753796127

2026-07-28T21:14:50.099+00:00 — azonenberg

Content

i have gearboxes and 64/66b coding blocks etc that we can add to it as needed

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message-1531771986810765352

2026-07-28T21:15:00.603+00:00 — Essen (@essen__)

Content

Perfect.
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message-1531772022445572317

2026-07-28T21:15:09.099+00:00 — azonenberg

Content

The internal-facing interface for the MAC is axi4-stream
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message-1531772143044395303

2026-07-28T21:15:37.852+00:00 — Essen (@essen__)

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Content

I hate you .... (Just kidding.)
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message-1531772240239267920

2026-07-28T21:16:01.025+00:00 — azonenberg

Content

at some point i'll polish things up more and document it etc
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message-1531772259017035886

2026-07-28T21:16:05.502+00:00 — Essen (@essen__)

Content

I will go though the code and see what we want to add: does it have a MDIO interface ?
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message-1531772349303619654

2026-07-28T21:16:27.028+00:00 — azonenberg

Content

No

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message-1531772415988862996

2026-07-28T21:16:42.927+00:00 — azonenberg

Content

just logic outputs for link up etc
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message-1531772450868691004

2026-07-28T21:16:51.243+00:00 — azonenberg

Content

I wanted to add some performance counters and adjustments to it in the future, but it would probably just be a register interface
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message-1531772670528585929

2026-07-28T21:17:43.614+00:00 — azonenberg

Content

Attachments

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message-1531772695694545016

2026-07-28T21:17:49.614+00:00 — Essen (@essen__)

Content

Mind if I bolt one on then?
I think we really want one. I can handle it.
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message-1531772741546545303

2026-07-28T21:18:00.546+00:00 — azonenberg

Content

Here's a capture of it running on an Efinix platform

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message-1531772844822888518

2026-07-28T21:18:25.169+00:00 — azonenberg

Content

Again, let's worry about the phy first
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message-1531772945242787976

2026-07-28T21:18:49.111+00:00 — azonenberg

Content

given the transceiver, the MAC/PCS is trivial. there are no major engineering challenges and there's existing code including but not limited to mine that we can build on
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message-1531772991044845588

2026-07-28T21:19:00.031+00:00 — azonenberg

Content

the transceiver is the part we don't have, and that is actually hard
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message-1531773684606304386

2026-07-28T21:21:45.389+00:00 — Essen (@essen__)

Content

Yeah, but my analog skills are far from good enough to be able to design a transiver, so I will stick to what I know I can do.
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message-1531773909987495977

2026-07-28T21:22:39.124+00:00 — azonenberg

Content

Well feel free to poke at my code but i suggest you not spend a lot of time on porting at this stage
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message-1531774019748233356

2026-07-28T21:23:05.293+00:00 — azonenberg

Content

I am planning to do some improvements here to make it more portable across a wider range of transceivers, and documenting it better, in the coming weeks/months

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message-1531774066346950726

2026-07-28T21:23:16.403+00:00 — azonenberg

Content

So you might end up with a lot of merge conflicts if you mess with the code much
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message-1531774374573772922

2026-07-28T21:24:29.89+00:00 — azonenberg

Content

especially things around clocking and resets that will be important for asic porting are going to get revamped
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message-1531774454600827012

2026-07-28T21:24:48.97+00:00 — azonenberg

Content

it ideally will end up being something that will run on any xilinx or efinix part, or asic, with few if any rtl changes needed to integrate
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message-1531778424685985867

2026-07-28T21:40:35.512+00:00 — azonenberg

Content

The bigger question, honestly, is how things like the CRC are going to do timing wise
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message-1531778466285097090

2026-07-28T21:40:45.43+00:00 — azonenberg

Content

in the MAC more than the PCS. the PCS is straightforward
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message-1531778500199972979

2026-07-28T21:40:53.516+00:00 — azonenberg

Content

but the MAC was written for 28nm and smaller FPGAs
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message-1531778590302142526

2026-07-28T21:41:14.998+00:00 — azonenberg

Content

I do not know how well it will perform on GF180 especially without the 1.8V transistors
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message-1531778725400678561

2026-07-28T21:41:47.208+00:00 — azonenberg

Content

I think 1000baseX and PCIe gen1/2 are far more reasonable goals for GF180MCU, and 10G is probably something we should be targeting at a future 90/65/40nm open PDK
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message-1531778770443173918

2026-07-28T21:41:57.947+00:00 — azonenberg

Content

I would be happy if someone proves me wrong and gets 10G working on 180 though
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message-1531778950076956774

2026-07-28T21:42:40.775+00:00 — Essen (@essen__)

Reply/reference

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Tapeout is november 9th, so unfortunalty it looks like I will take the risk.
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message-1531779636713881761

2026-07-28T21:45:24.482+00:00 — Essen (@essen__)

Content

Do you have a top for the PCS somewhere, looking at the code I see a lot of modules but I was wondering if you had another repo where you fit them all together ?
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message-1531781266297589860

2026-07-28T21:51:53.005+00:00 — azonenberg

Content

This is purely an IP library repo
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message-1531781465912770650

2026-07-28T21:52:40.597+00:00 — azonenberg

Content

interface/ethernet-stream/AXIS_XGEthernetMACWrapper is the top level wrapper for the Xilinx FPGA version of the block

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message-1531781578143957226

2026-07-28T21:53:07.355+00:00 — azonenberg

Content

It includes an UltraScale+ GTY instance, clocks from the quad PLL, the PCS, and the MAC
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message-1531781653196967946

2026-07-28T21:53:25.249+00:00 — azonenberg

Content

goes all the way from external differential pairs to axi streams facing the FPGA internals
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message-1531781789582885094

2026-07-28T21:53:57.766+00:00 — azonenberg

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There are a lot of state machines and blocks in there that rely on FPGA power-on reset so you'll have to add external reset inputs for all of that
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message-1531781850438045897

2026-07-28T21:54:12.275+00:00 — azonenberg

Content

You may have to increase pipeline depth for some stuff
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message-1531781865059516647

2026-07-28T21:54:15.761+00:00 — Essen (@essen__)

Content

( perfect I just to happen to have an UltraScale+ in the corner )
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message-1531781957720084532

2026-07-28T21:54:37.853+00:00 — azonenberg

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But if you don't have a transceiver yet, how are you going to tape this out?
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message-1531781967039696997

2026-07-28T21:54:40.075+00:00 — azonenberg

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i'm confused
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message-1531782000715895024

2026-07-28T21:54:48.104+00:00 — Essen (@essen__)

Content

Yeah, not a fan of the 64b wide data path too ...
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message-1531782139387969566

2026-07-28T21:55:21.166+00:00 — azonenberg

Reply/reference

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10GbaseR is natively a 64b block size although my MAC is mostly running double rate at 32 bit datapath
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message-1531782183063130225

2026-07-28T21:55:31.579+00:00 — azonenberg

Content

since that's what the GTY typically gives you
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message-1531782253800329216

2026-07-28T21:55:48.444+00:00 — azonenberg

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It passes timing for a -2 kintex7 with a GTX as well, i've used it there successfully
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message-1531782290500354149

2026-07-28T21:55:57.194+00:00 — azonenberg

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i did have to add an extra pipeline stage there after having originally wrote it on ultrascale+
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message-1531782448613167235

2026-07-28T21:56:34.891+00:00 — Essen (@essen__)

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namibj is doing the transceiver, I am doing the digital side and we are targeting the chipalooza challenge
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message-1531782491197669397

2026-07-28T21:56:45.044+00:00 — azonenberg

Content

ah ok you're working together
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message-1531782522323730462

2026-07-28T21:56:52.465+00:00 — azonenberg

Content

If you poke around there are 64/66b gearboxes under serdes/ in the same repo

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message-1531782558893740132

2026-07-28T21:57:01.184+00:00 — azonenberg

Content

and block alignment
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message-1531782585989074956

2026-07-28T21:57:07.644+00:00 — azonenberg

Content

that i've used to interface with transceivers that don't include this functionality natively
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message-1531782618687733791

2026-07-28T21:57:15.44+00:00 — azonenberg

Content

the wrapper i mentioned above assumes your transceiver has the gearbox
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message-1531782764200857821

2026-07-28T21:57:50.133+00:00 — azonenberg

Content

but yeah, i did not try super hard to save on area etc because i targeted this at large FPGAs where e.g. block ram is cheap

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message-1531782822367461468

2026-07-28T21:58:04.001+00:00 — Essen (@essen__)

Content

Right, you don't provide a gearbox.
I will just bring mine.
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message-1531782944593674381

2026-07-28T21:58:33.142+00:00 — azonenberg

Content

I have a gearbox
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message-1531782955972821052

2026-07-28T21:58:35.855+00:00 — azonenberg

Content

it's just not in the wrapper
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message-1531783041653936370

2026-07-28T21:58:56.283+00:00 — azonenberg

Content

it's in serdes/linecode/
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message-1531783222541947030

2026-07-28T21:59:39.41+00:00 — azonenberg

Content

Gearbox32PlusHeaderTo32 and Gearbox32To32PlusHeader are probably the ones to look at

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message-1531783362040172594

2026-07-28T22:00:12.669+00:00 — azonenberg

Content

All the pieces are there, i just dont have any docs on how they fit together yet
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message-1531783404071424100

2026-07-28T22:00:22.69+00:00 — azonenberg

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but i am using them in real designs across several FPGAs internally

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message-1531783547109507102

2026-07-28T22:00:56.793+00:00 — Essen (@essen__)

Content

Perfect, at least then I can be confident that they work.
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message-1531783567800008896

2026-07-28T22:01:01.726+00:00 — azonenberg

Content

and again they're missing the asic resets

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message-1531783635198546083

2026-07-28T22:01:17.795+00:00 — azonenberg

Content

especially on the axi stream versions rather than the older legacy ones using the native interface
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message-1531783679301386372

2026-07-28T22:01:28.31+00:00 — azonenberg

Content

some stuff is reset on the axi stream ARESET#
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message-1531783687086014464

2026-07-28T22:01:30.166+00:00 — azonenberg

Content

but not everything
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message-1531783831093510214

2026-07-28T22:02:04.5+00:00 — azonenberg

Content

note also that the datapath supports running at both 312.5 and 322.2625 MHz depending on if you are using the weird xilinx pll flow that gives you a 32b data word every clock
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message-1531783915524587603

2026-07-28T22:02:24.63+00:00 — azonenberg

Content

or if you are just at 1/32 rate on the serdes and occasionally have gaps in the data due to gearboxing

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message-1531783935909040280

2026-07-28T22:02:29.49+00:00 — azonenberg

Content

so there's a data-valid strobe to account for
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message-1531783965092872425

2026-07-28T22:02:36.448+00:00 — azonenberg

Content

and the axi stream on the tx side can occasionally backpressure

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message-1531784044591845567

2026-07-28T22:02:55.402+00:00 — azonenberg

Content

the rx side stream does not support backpressure and if you can't process the data as it comes in, any FIFOs are up to you as the integrator

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message-1531785929210069123

2026-07-28T22:10:24.73+00:00 — Essen (@essen__)

Content

For now I will try to assemble a top level with your code and get an area estimate + see how much work timing needs.
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message-1531786110722773283

2026-07-28T22:11:08.006+00:00 — Essen (@essen__)

Content

Thanks @azonenberg
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message-1531786276519411722

2026-07-28T22:11:47.535+00:00 — azonenberg

Content

The older version of the MAC had FIFOs that needed block ram, the AXI version backpressures on the TX so I don't think there is any SRAM anywhere in the mac/pcs
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message-1531786306781319258

2026-07-28T22:11:54.75+00:00 — azonenberg

Content

what you put on the far side of the MAC is up to you
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message-1531786344676724889

2026-07-28T22:12:03.785+00:00 — azonenberg

Content

But yeah, timing was not designed for an old slow cmos process
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message-1531786360619405463

2026-07-28T22:12:07.586+00:00 — azonenberg

Content

so i am curious just how bad it will be
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message-1531786472410316860

2026-07-28T22:12:34.239+00:00 — azonenberg

Content

There is also a PRBS31 generator core under math/ in that same repo BTW

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message-1531786515527630938

2026-07-28T22:12:44.519+00:00 — azonenberg

Content

that you should be able to just mux straight into the serdes at whatever bit width it runs at
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message-1531786590156751129

2026-07-28T22:13:02.312+00:00 — azonenberg

Content

i don't currently have a PRBS checker IP you'll have to write that yourself

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message-1531786697627668540

2026-07-28T22:13:27.935+00:00 — azonenberg

Content

i dont think i ever wrote PRBS7 but 31 is the more important test pattern since it more closely approximates the spectral characteristics of scrambled 10GbaseR data
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message-1531786728162070794

2026-07-28T22:13:35.215+00:00 — azonenberg

Content

PRBS7 is better to simulate 8b10b

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message-1531788490398761072

2026-07-28T22:20:35.365+00:00 — Essen (@essen__)

Reply/reference

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I should have the results soon, maybe by tomorrow, but I don't think it will be too bad.
Let's see.
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message-1531789274930741418

2026-07-28T22:23:42.412+00:00 — Essen (@essen__)

Content

The first node we are targetting is the ihp cmos 5l, which is about ~8x faster than the gf180 7 track.
But I think I will indeed be having a lot of fun with it ... 🫠
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message-1531789715416551474

2026-07-28T22:25:27.432+00:00 — azonenberg

Content

oh, if you're going for IHP it'll definitely be a lot faster lol
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message-1531789782819147967

2026-07-28T22:25:43.502+00:00 — azonenberg

Content

i was thinking gf180mcu with 3.3/5v cells
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message-1531795726336786645

2026-07-28T22:49:20.547+00:00 — Essen (@essen__)

Content

Apparently the 9 track cells are a lot faster, but with just the 7 track closing that timing at 3.3V sounds like hell on earth
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message-1531796018167943409

2026-07-28T22:50:30.125+00:00 — Essen (@essen__)

Content

That being said ... the plan of the challenge is to port the IP to all the nodes, and gf is defiantly on that list.
So sooner or later I will have to walk though that hell ...
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message-1531797005603442799

2026-07-28T22:54:25.548+00:00 — azonenberg

Content

Lol. Well let me know how it goes, I'll see if i have time to do the cleanup of the MAC/PCS on my end
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message-1531797084968321218

2026-07-28T22:54:44.47+00:00 — azonenberg

Content

I do also have a tri-speed 10/100/1000 baseX/SGMII MAC and 8b10b block
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message-1531797135970799757

2026-07-28T22:54:56.63+00:00 — azonenberg

Content

which i think is likely to be easier to close timing for

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message-1531809561307254906

2026-07-28T23:44:19.061+00:00 — Essen (@essen__)

Content

Thanks, and in this trade I can offer the 100BASE-T/RMII MAC.
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message-1531815744759922700

2026-07-29T00:08:53.311+00:00 — azonenberg

Content

I probably have one of those around somewhere too but I don't use RMII much
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message-1531815842948321381

2026-07-29T00:09:16.721+00:00 — azonenberg

Content

Normally I just run RGMII for everything since I have RGMII PHYs all over the place and even if i don't *need* gigabit it's easier than inventorying another phy and support passives
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message-1531815872925274303

2026-07-29T00:09:23.868+00:00 — azonenberg

Content

i can just slap the same design down anywhere and use it
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message-1532128269351256086

2026-07-29T20:50:44.98+00:00 — namibj

Reply/reference

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We're targeting Tim Edward's IHP tapeout for now; then doing the muxed e-test for W.S. Run3; then porting the SerDes from IHP to the next one in line (I think it was aimed roughly at W.S. Run4?).
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message-1532129353352220792

2026-07-29T20:55:03.426+00:00 — namibj

Reply/reference

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~~ngl I was thinking about 33b wide to kill the gearbox but `3¹ × 11¹` is not a good vibe to target with the MUX~~
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message-1532130128929488998

2026-07-29T20:58:08.338+00:00 — namibj

Reply/reference

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Do you know if it's easier or harder to check than the scrambled idle test pattern they added as an optional one in the 25GBASE-R PCS?
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message-1532130176207556808

2026-07-29T20:58:19.61+00:00 — azonenberg

Content

Yeah 32:1 serialization followed by 33:32 gearboxing is the way to do it IMO
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message-1532130257065480273

2026-07-29T20:58:38.888+00:00 — azonenberg

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I have not looked at 25GbaseR so can't comment. I believe it is the same 64/66b line code as 10GbaseR but with FEC added on top
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message-1532130329031213078

2026-07-29T20:58:56.046+00:00 — azonenberg

Content

PRBS7/31 are trivial LFSRs and super easy to check
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message-1532130376355418324

2026-07-29T20:59:07.329+00:00 — namibj

Content

And any wants regarding statistics that go beyond very plain&obvious counters?
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message-1532130470236524544

2026-07-29T20:59:29.712+00:00 — azonenberg

Content

So, *ideally* if you want something the most flexible and useful - i don't expect this for the first tapeout
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message-1532130505850491061

2026-07-29T20:59:38.203+00:00 — azonenberg

Content

your receiver would have two slicers with controllable phase and voltage offset
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message-1532130539870490806

2026-07-29T20:59:46.314+00:00 — azonenberg

Content

One always tries to be in the eye center, the other is adjustable
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message-1532130568551141487

2026-07-29T20:59:53.152+00:00 — namibj

Reply/reference

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Yeah the FEC is only lacking in CR-S and SR-S; it only has minor additions on 10G other than that FEC.
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message-1532130579074777126

2026-07-29T20:59:55.661+00:00 — azonenberg

Content

And you can sweep phase/voltage shift and check how much of the time they disagree
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message-1532130642396184616

2026-07-29T21:00:10.758+00:00 — azonenberg

Content

Which will let you do full BER eye scan
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message-1532130717113516125

2026-07-29T21:00:28.572+00:00 — azonenberg

Content

This is how serdes eye scan works on e.g. xilinx transceivers, and IMO is a feature we very much want in a production grade open serdes IP
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message-1532130788936781904

2026-07-29T21:00:45.696+00:00 — azonenberg

Content

it isn't a day-one requirement for a first tapeout but the more you can validate early on the better
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message-1532130844309852292

2026-07-29T21:00:58.898+00:00 — azonenberg

Content

and it will make receiver margin testing much easier if we can eye-scan internally, post equalization
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message-1532130891764334744

2026-07-29T21:01:10.212+00:00 — azonenberg

Content

we can then play with CTLE settings to see what gives the most open eye at the RX
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message-1532130971401584651

2026-07-29T21:01:29.199+00:00 — azonenberg

Content

If done right, this eye scan is non-intrusive (the actual signal-out slicer doesn't change) and can work on arbitrary data not just a PRBS
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message-1532131053752287312

2026-07-29T21:01:48.833+00:00 — namibj

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So, the good thing, if lucky a phase interpolator thingy falls out of the CDR design blocks; if that's easily digitally controllable I would very much attempt to give you a capture ability akin to the 10G reclocker you linked a couple days ago.
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message-1532131127953850389

2026-07-29T21:02:06.524+00:00 — azonenberg

Content

Great. Look at e.g. the xilinx GTX/GTY datasheets for an example of how you'd use this
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message-1532131167908921345

2026-07-29T21:02:16.05+00:00 — azonenberg

Content

I have code written for the GTX, haven't done GTY yet
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message-1532131306962423910

2026-07-29T21:02:49.203+00:00 — azonenberg

Content

Long term, I would want an APB or similar register interface on the transceiver that we can use to access eye scan as well as various configuration settings like enabling PRBS test, controlling emphasis, etc
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message-1532131346829414522

2026-07-29T21:02:58.708+00:00 — azonenberg

Content

It probably makes sense for this to be an external module
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message-1532131459475705926

2026-07-29T21:03:25.565+00:00 — azonenberg

Content

i.e. the transceiver has a native interface with separate ports you can drive directly from RTL, then you supply a bus wrapper with a memory map around those ports as an optional addon
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message-1532131661708263435

2026-07-29T21:04:13.781+00:00 — azonenberg

Content

If you have a proposed feature set and RTL interface documented anywhere yet, I can give feedback I've worked with multiple vendors' FPGA SERDES as well as one ASIC SERDES so far
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message-1532131701655076925

2026-07-29T21:04:23.305+00:00 — azonenberg

Content

So i have a decent idea of what i do and don't like
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message-1532131785281114293

2026-07-29T21:04:43.243+00:00 — namibj

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I'm not gonna attempt CTLE if I can get enough amplitude in to where I can hit the eye box with the whatever kind of clocked comparator it's gonna rely on.
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message-1532133192935669801

2026-07-29T21:10:18.854+00:00 — azonenberg

Content

well anyway, internal eye scan is something we need long term
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message-1532133224212598784

2026-07-29T21:10:26.311+00:00 — azonenberg

Content

if it can't make the initial tapeout, we'll survive
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message-1532133258802757683

2026-07-29T21:10:34.558+00:00 — azonenberg

Content

but it is a must-have feature for a long term professional grade transceiver
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message-1532135080791900220

2026-07-29T21:17:48.954+00:00 — namibj

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I did/do want to be able to express that spectrum for e.g. the USB-SS, DP HBR2/3 (5.4/8.1 GBaud), PCIe 1/2, SATA 3, and depending on performance possibly SAS-3 (12G NRZ 8b10b).
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message-1532135150710821027

2026-07-29T21:18:05.624+00:00 — azonenberg

Content

Yes. Which is why i suggested you implement both
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message-1532135242645766235

2026-07-29T21:18:27.543+00:00 — azonenberg

Content

Given my PRBS31 module it should be trivial to make a PRBS7 generator, just change the length of the LFSR and tweak the tap positions
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message-1532135284278296738

2026-07-29T21:18:37.469+00:00 — azonenberg

Content

should be like two lines of code changed
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message-1532135391057023230

2026-07-29T21:19:02.927+00:00 — azonenberg

Content

or i can do it and fpga verify it at some point
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message-1532135707307675708

2026-07-29T21:20:18.327+00:00 — namibj

Content

Is loopback from an offset slicer if the clock recovery is sufficiently independent to stay locked an acceptable substitute for an internal eye scanner?

At least if e.g. area limitations stand in the way of an actual second slicer & demuxer package?
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message-1532234165192364054

2026-07-30T03:51:32.516+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Essen - Other resources you might want to consider looking into are:
 * LiteEth
 * https://github.com/corundum/corundum

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message-1532289673618133135

2026-07-30T07:32:06.756+00:00 — azonenberg

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What do you mean loopback from an offset slicer? can you draw a dtapath block diagram or something?
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message-1532335637146112093

2026-07-30T10:34:45.315+00:00 — namibj

Reply/reference

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I'll draw you a diagram in bit once I'm at the office.
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message-1532429765875597343

2026-07-30T16:48:47.353+00:00 — Essen (@essen__)

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Yup, alex is going an amazing job there.
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message-1532432376599154979

2026-07-30T16:59:09.798+00:00 — Essen (@essen__)

Content

On another topic, I think I will be not be using your RTL, just as inspiration for getting some early area utilization number for now @azonenberg (and won't be actually porting it for now).
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message-1532453392583229520

2026-07-30T18:22:40.399+00:00 — azonenberg

Content

OK, doesnt matter to me one way or the other. I do plan to polish it up to an ASIC-friendly format at some point but it was not on my near term agenda

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message-1532761158073978880

2026-07-31T14:45:37.41+00:00 — namibj

Reply/reference

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message-1532761185399738389

2026-07-31T14:45:43.925+00:00 — namibj

Content

Sorry forgot to send it yesterday.
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message-1532764839837958324

2026-07-31T15:00:15.211+00:00 — namibj

Content

Reason is in part because depending on how the clock recovery works, it might pretty much need an adjustment dial for the slicer phase and depending on how DC offsets in the input buffer/amplifier/etc. work, slicer level might also need to be adjusted vertically anyways, which together would make the main slicer already capable of the eye pattern sampling.

Together with if clock recovery can run on the edges independently of the slicer-proper, I.e., without depending on the data recovery part of the whole CDR, this would allow using the phase lock of normal CDR while telling the data slicer to sample deliberately not in the center of the eye.

And if that outcome could be exported by feeding the "recovered" data to a TX serializer that's slaved to the same recovered clock, this would AFAIK allow something resembling a "SAR-ADC sampling oscilloscope".
Notably the transmitted bitstream may lack sufficient transition density for easy CDR, but as it's slaved to the RX recovered clock, I'd assume a far far smaller PLL bandwidth for the CDR (together with a lock of frequency being hard-locked to the test signal sent to the DUT) to suffice and ideally thus allow dealing with such poor patterns.
I mean it might need to be captured with an ADC and processed in configurable or even programmable compute, but oh well...
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