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Thread: GitHub - SUD0NET-as16- 16-bit RISC CPU d

32 Discord messages from ℹ️ - Information/general/threads/github-sud0net.md.

Category: ℹ️ - Information Parent channel: #general Thread ID: 1527256895386157127

Messages: 32

message-1527446433391968256

2026-07-16T22:46:48.303+00:00 — kcolley

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message-1527446441012756532

2026-07-16T22:46:50.12+00:00 — kcolley

Content

Very cool! Documentation of instruction format could use some improvement though. It took me a while to figure out that this architecture **CAN** in fact read memory, as the opcode is actually only 3 bits (not 4 like in the readme) and the top bit is actually the "read memory bit". Predicates aren't defined either, so I'm still a bit confused on what bits to set for the C/Z/Invert predicate bits to do something logical, or if there's a way to make an unconditional instruction.
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message-1527446776733237470

2026-07-16T22:48:10.162+00:00 — kcolley

Content

And if I'm correct the only way to branch is by writing to the PC register? Which combined with predicates instructions allows for conditional branching, nice

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message-1527447648397820018

2026-07-16T22:51:37.983+00:00 — kcolley

Content

Also I think there's no way to add reg + reg, you can only add reg + imm or reg + mem?

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message-1527462870063775844

2026-07-16T23:52:07.111+00:00 — судонет (@sudonet)

Content

documentation, indeed, needs improvement
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message-1527463045897650398

2026-07-16T23:52:49.033+00:00 — судонет (@sudonet)

Content

the opcode is actually 3-bit, as you stated
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message-1527463854727237685

2026-07-16T23:56:01.873+00:00 — судонет (@sudonet)

Content

but there is a modifier for the ADD/ADC mnemonics in line 35 of as16.v: `ADD, ADC : {carry, result} = grf_dout + OR_q + (!IR_q[8] & C_q);`
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message-1527465419886039323

2026-07-17T00:02:15.036+00:00 — kcolley

Content

Though bit 8 is just one of the normal opcode bits, specifically the low bit that distinguishes between ADD and ADC. So still a 3-bit opcode

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message-1527465506670510100

2026-07-17T00:02:35.727+00:00 — судонет (@sudonet)

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exactly.
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message-1527470859361587381

2026-07-17T00:23:51.908+00:00 — kcolley

Content

Oh also it looks like you can only read and write to constant memory addresses? No array indexing or stack?
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message-1527470917997826189

2026-07-17T00:24:05.888+00:00 — kcolley

Content

Unless you do some self modifying code shenanigans, I guess...
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message-1527471849254949064

2026-07-17T00:27:47.917+00:00 — судонет (@sudonet)

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Content

well, `EA_ED` does let you add a reg to an offset to form an address...
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message-1527472223256969407

2026-07-17T00:29:17.086+00:00 — kcolley

Content

Ah, missed that

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message-1527472329351761980

2026-07-17T00:29:42.381+00:00 — kcolley

Content

I also don't see how sram is connected to anything in the core module. Seems unconnected?

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message-1527472364630048970

2026-07-17T00:29:50.792+00:00 — судонет (@sudonet)

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exactly
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message-1527472447584993290

2026-07-17T00:30:10.57+00:00 — судонет (@sudonet)

Content

kinda just hardwired it outside from the cpu
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message-1527472556431380591

2026-07-17T00:30:36.521+00:00 — kcolley

Content

So you're planning to use an external SRAM chip and ignore the internal SRAM you're generating?
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message-1527472588337578064

2026-07-17T00:30:44.128+00:00 — судонет (@sudonet)

Reply/reference

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Content

yep
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message-1527472668461240431

2026-07-17T00:31:03.231+00:00 — судонет (@sudonet)

Content

just going to treat the as16 as a microprocessor
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message-1527472866050834615

2026-07-17T00:31:50.34+00:00 — судонет (@sudonet)

Content

besides, i kinda rushed the design in those 3 days
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message-1527472941074485390

2026-07-17T00:32:08.227+00:00 — kcolley

Content

Gotcha, yeah that was a very quick window haha
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message-1527473946826379348

2026-07-17T00:36:08.017+00:00 — судонет (@sudonet)

Content

overall, i'm kinda happy for my first tapeout

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message-1527480697428906136

2026-07-17T01:02:57.486+00:00 — kcolley

Content

Yeah looks like it'll be a fun chip to play around with!
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message-1527480698372489389

2026-07-17T01:02:57.711+00:00 — kcolley

Content

congrats 🙂
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message-1527482920988577953

2026-07-17T01:11:47.624+00:00 — судонет (@sudonet)

Reply/reference

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thx
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message-1527482990039662633

2026-07-17T01:12:04.087+00:00 — судонет (@sudonet)

Content

i'm not sure how i'm going to wirebond it
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message-1527483054996721725

2026-07-17T01:12:19.574+00:00 — судонет (@sudonet)

Content

as i didn't choose for COB packaging

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message-1527483438322421873

2026-07-17T01:13:50.966+00:00 — судонет (@sudonet)

Content

i'll probably have to find some national facility to do it for me as an "academic institution"
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message-1527563388543172718

2026-07-17T06:31:32.584+00:00 — kcolley

Content

hmm, I wonder if it would be feasible for WS to provide at least one CoB-packaged chip even if you elected to not have them all packaged. Could be really useful for initial testing, and I'd think it would logistically be not too difficult to do one extra CoB wirebonding per design. Main challenge would be to keep them separated without accidentally mixing them up I guess. cc @Tim 'mithro' Ansell for the idea

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message-1527564123850674218

2026-07-17T06:34:27.895+00:00 — судонет (@sudonet)

Reply/reference

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Content

fair enough
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message-1527573488225747096

2026-07-17T07:11:40.536+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

One of the biggest problem is the shipping costs and dealing with paperwork.

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message-1527573741536677918

2026-07-17T07:12:40.93+00:00 — kcolley

Content

ah, didn't think about the fact that it would require shipping to a separate facility for packaging, meaning that one chip would be a separate shipping expense...
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