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Thread: DIY SCL

36 Discord messages from ℹ️ - Information/general/threads/diy-scl.md.

Category: ℹ️ - Information Parent channel: #general Thread ID: 1499830130900598967

Messages: 36

message-1499830281161408624

2026-05-01T17:50:04.528+00:00 — namibj

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Content

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message-1499830285427146872

2026-05-01T17:50:05.545+00:00 — namibj

Content

I'm guessing my MCML SCL efforts are not particularly relevant for those/that application?
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message-1499830322710450397

2026-05-01T17:50:14.434+00:00 — Lofty (@ravenslofty)

Content

MCML?
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message-1499830324148834360

2026-05-01T17:50:14.777+00:00 — namibj

Content

@Lofty @Tholin
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message-1499830472434258051

2026-05-01T17:50:50.131+00:00 — namibj

Content

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message-1499830478104956998

2026-05-01T17:50:51.483+00:00 — Lofty (@ravenslofty)

Content

"mos current mode logic"
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message-1499830483394101288

2026-05-01T17:50:52.744+00:00 — namibj

Content

MUX2
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message-1499830596896034846

2026-05-01T17:51:19.805+00:00 — Lofty (@ravenslofty)

Content

um, does this use differential signalling?
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message-1499830827469771013

2026-05-01T17:52:14.778+00:00 — namibj

Content

stacks up to about 4~5 on sky130; probably more on gf180mcu due to higher voltage margins allowing for more stacked nmos to be in saturation, at least if there's near-zero-native-threshold voltage devices that can be placed in a raised pwell
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message-1499830854535483563

2026-05-01T17:52:21.231+00:00 — namibj

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Content

yes!
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message-1499830887813091460

2026-05-01T17:52:29.165+00:00 — namibj

Content

means inverters are free
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message-1499831044088660098

2026-05-01T17:53:06.424+00:00 — namibj

Content

this is a delay cell of which you can use just 2 to get a quadrature VCO

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message-1499831262737858791

2026-05-01T17:53:58.554+00:00 — namibj

Content

well, you want a bias generator to adjust the load to get good swing at the tail current that gives the desired frequency
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message-1499831543605231696

2026-05-01T17:55:05.518+00:00 — Lofty (@ravenslofty)

Content

so, Tholin's 3.3V static CMOS library will fit naturally into a synthesisable flow. mine will require...some finagling but *is* intended to be targetable by synthesis tools.

I'm...much less convinced about the feasibility of dual-rail logic from a synthesis tool. Of course people can hand-design all they want, but I think both Tholin and I want a library which is "good enough" for people.
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message-1499831583555977307

2026-05-01T17:55:15.043+00:00 — namibj

Content

I'm _trying_ to get the TX part of a serdes onto my tile on ttsky26a and would be porting the design to wafer.space Run2.
I'd expect to get a sprinkle of SCL done for the fall ttsky26
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message-1499831637779808397

2026-05-01T17:55:27.971+00:00 — namibj

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Content

wdym dual-rail?
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message-1499831878491046120

2026-05-01T17:56:25.361+00:00 — Lofty (@ravenslofty)

Content

"dual-rail" is the term for differential logic inside an integrated circuit
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message-1499832011953668290

2026-05-01T17:56:57.181+00:00 — namibj

Content

the cells once done as actual SCL blocks are just sipped with what currently looks to be a second metal trace over or right adjacent to the Vdd and GND power rails of a normal SCL footprint setup.
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message-1499832381484568747

2026-05-01T17:58:25.284+00:00 — namibj

Content

The GND-side one is the tail bias; the Vdd-side one is the PMOS active tie one; that one is skippable in exchange for loosing the ability to dial power-delay-product without having to do dynamic Vdd scaling.
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message-1499832414929686790

2026-05-01T17:58:33.258+00:00 — namibj

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ohhhh
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message-1499832613865656390

2026-05-01T17:59:20.688+00:00 — namibj

Content

(I mean I'm pretty sure it can be routed as just a double-pitch track on the usual DRCs for metal corners.)
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message-1499832815494103222

2026-05-01T18:00:08.76+00:00 — Lofty (@ravenslofty)

Content

um, not what I meant, exactly.
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message-1499832910595883260

2026-05-01T18:00:31.434+00:00 — namibj

Content

But yes, sure.
The bigger hurdle would likely be to teach yosys that some cells _exist_ but are often slower than decomposing (not always, and usually not smaller).
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message-1499833132713509077

2026-05-01T18:01:24.391+00:00 — Lofty (@ravenslofty)

Content

Well, that's the job of the liberty library.
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message-1499833142637232382

2026-05-01T18:01:26.757+00:00 — namibj

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Are you suggesting that yosys would have more fundamental issues coping with the concept of free inversion?
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message-1499833255187452010

2026-05-01T18:01:53.591+00:00 — namibj

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can't google
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message-1499833711313817802

2026-05-01T18:03:42.34+00:00 — Lofty (@ravenslofty)

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I'm... going to assume this was asked in good faith and you're not trying to imply I don't know how inverters work.
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message-1499833948359102514

2026-05-01T18:04:38.856+00:00 — Lofty (@ravenslofty)

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https://people.eecs.berkeley.edu/~alanmi/publications/other/liberty07_03.pdf

It's a specification by Synopsis that basically all standard cell libraries use (sky130, gf180mcu, ihp sg13g2...)
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message-1499834521019748412

2026-05-01T18:06:55.389+00:00 — namibj

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No I'm well aware you know yosys and almost certianly the gate names way better than me.
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message-1499834734530924665

2026-05-01T18:07:46.294+00:00 — namibj

Content

But without differential logic it's AFAIK not the case that inversion is (close enough to) free.
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message-1499835090266624010

2026-05-01T18:09:11.108+00:00 — Lofty (@ravenslofty)

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So, ABC flatly does not understand differential logic, so you have to treat your differential cells as single-rail (non-differential logic) for the purposes of mapping it, and then map from single-rail to dual-rail and duplicate the single-rail nets.

Realistically? That means writing a Yosys pass to do that transform.
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message-1499835260727459935

2026-05-01T18:09:51.749+00:00 — Lofty (@ravenslofty)

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In domino logic inversion is free because it's impossible to express inverting functions :p
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message-1499837125720281188

2026-05-01T18:17:16.398+00:00 — namibj

Content

oh right forgot that single-ended companion exists
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message-1499837378334953542

2026-05-01T18:18:16.626+00:00 — namibj

Content

well, more like, that it (a) does exist and that (b) domino logic refers to it.
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message-1499837695478726782

2026-05-01T18:19:32.239+00:00 — namibj

Content

which makes them somewhat similar in synthesis considerations, though MCML isn't as forced to use a dedicated one-shot precharge
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message-1499838735607533778

2026-05-01T18:23:40.225+00:00 — namibj

Content

I've been more concerned with the difficulty of power gating MCML and it's near indifference to clock gating (and related, abhorrent power consumption of DFF-RAM), regarding practical usability.
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