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Thread: 3.3V SRAM

66 Discord messages from ℹ️ - Information/general/threads/33v-sram.md.

Category: ℹ️ - Information Parent channel: #general Thread ID: 1439805978022510703

Messages: 66

message-1439876762057183283

2025-11-17T07:16:11.691+00:00 — urish

Reply/reference

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message-1439876776292651083

2025-11-17T07:16:15.085+00:00 — urish

Content

Congrats Tim!
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message-1439876884862079038

2025-11-17T07:16:40.97+00:00 — urish

Content

How many bits?

300x300 will make it useful for TT projects
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message-1439879938546073621

2025-11-17T07:28:49.025+00:00 — tnt (@246tnt)

Content

512 bytes AFAIR

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message-1439989030778441831

2025-11-17T14:42:18.64+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

512 bytes was the largest of the four GF 5V SRAM macros.  I was thinking of expanding that to 1kB for another macro;  shouldn't be too hard.  But I'll get this one done first.
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message-1439994503833325719

2025-11-17T15:04:03.518+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@urish :  What size is a TT slot on GF180MCU?
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message-1439995008634720306

2025-11-17T15:06:03.872+00:00 — tnt (@246tnt)

Content

346.64 um x  160.72 um
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message-1439995222691156109

2025-11-17T15:06:54.907+00:00 — urish

Content

https://github.com/TinyTapeout/tt-support-tools/blob/main/tech/gf180mcuD/tile_sizes.yaml

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message-1439995373484769361

2025-11-17T15:07:30.859+00:00 — tnt (@246tnt)

Content

But that means in a 2x2 ( 711.20 um x 325.36 um ) you can fit a decent size SRAM and some logic.

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message-1440117679569637457

2025-11-17T23:13:30.902+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

The SRAM block is now both DRC and LVS clean.  I will work tomorrow on squeezing out additional space at the bottom and then I will push to the repository.  Again, don't expect timing values at this point in the process.

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message-1440167035186188298

2025-11-18T02:29:38.198+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - Super cool!
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message-1440408122899300354

2025-11-18T18:27:37.988+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

First commit of the 3.3V SRAM (512 bytes) is now *LIVE* at https://github.com/RTimothyEdwards/gf180mcu_ocd_ip_sram/ !

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message-1440499556541399201

2025-11-19T00:30:57.467+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - Awesome work!
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message-1440499591261720608

2025-11-19T00:31:05.745+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

What's `ocd`?
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message-1440514788282073148

2025-11-19T01:31:28.997+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Open Circuit Design (or Obsessive-Compulsive Disorder;  take your pick).
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message-1440832611181133876

2025-11-19T22:34:23.881+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Pushed an update today.  I managed to squeeze some space out of it, but not as much as I originally thought I could;  ultimately I recovered about 8um which is not terribly useful for having spent a full day and a half doing it.  The final layout area is 301.3um x 321.89um.  The fact that the height is now less than a TT slot height is purely coincidental, and probably meaningless.  All digital pinouts are on the bottom side and there is only enough space in the TT slot to get maybe 9 routes in from the side, whereas the block has 36 digital I/O.  It could be rotated 90 degrees but then the I/O are not in the preferred direction.
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message-1440832935430328501

2025-11-19T22:35:41.188+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - How does that compare to the 5V SRAM?
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message-1440866745907679253

2025-11-20T00:50:02.234+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Area-wise, it's slightly less than 1/2 the area.
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message-1440956079985922068

2025-11-20T06:45:01.138+00:00 — tnt (@246tnt)

Content

@Tim Edwards Well it would be easy enough to make a thin wrapper that brings the traces to the preferred routing direction ( and possibly adapts power rails so they connect nicely too ).
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message-1441117105536635030

2025-11-20T17:24:52.621+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

I thought about that but didn't do a feasibility study.  : )  Yet.
Also:  It's pretty easy to make the smaller SRAM versions, since GF used the same control block exactly, just removed a number of rows and grounded the upper address bits.  The 256 byte SRAM is 301.3um x 224.93um.  It took me less than 30 minutes to create the 256 byte layout from the 512 byte layout, but there are a couple of LVS errors I need to fix.  I should be able to get that pushed before the end of the weekend.
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message-1441186999498309643

2025-11-20T22:02:36.64+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

:joke: Shouldn't it be 1/4th the size? 😛
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message-1441192521756704798

2025-11-20T22:24:33.249+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

The transistors scale to 1/4 area;  everything else, not so much.
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message-1441193118920740904

2025-11-20T22:26:55.624+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

Yeah, sadly I knew that
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message-1441561475050246255

2025-11-21T22:50:38.569+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

I have pushed the 256 byte SRAM as well (now DRC and LVS clean).

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message-1441713984662147134

2025-11-22T08:56:39.694+00:00 — tnt (@246tnt)

Content

@Tim Edwards Do you have a test slot planned for those ?  Because I would love to have those validated in the first run, along with the split voltage IO lib since I'm planning to use those for the second tiny tapeout run ( and hopefully we'll have the results of the first run by then ).
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message-1441807666019303495

2025-11-22T15:08:55.07+00:00 — urish

Content

Thought on putting them on TTGF0p2?
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message-1441808131624669357

2025-11-22T15:10:46.079+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@tnt :  That was my plan.  I should be able to get something out in a week.  It won't be a very complex chip but I should be able to put together a simple "openframe" version of Caravel-GF using the mixed-voltage pads and drop some SRAMs in the middle along with some basic control logic and call it a day.
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message-1441808331848155230

2025-11-22T15:11:33.816+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@urish :  Maybe?  What's the current support for 3.3V on TTGF?
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message-1441809258768367656

2025-11-22T15:15:14.811+00:00 — urish

Content

TTGF runs in 3v3 by default
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2025-11-22T15:16:12.304+00:00 — urish

Content

The main question is if we feel confident enough to put it since designs aren't power gated
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message-1441810030314651668

2025-11-22T15:18:18.762+00:00 — tnt (@246tnt)

Content

@urish Well not really because there aren't power gates and I'd like to run comparison between 3.3v and 5v which means everything on there must support 5V without destroying the chip ...
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2025-11-22T15:23:15.054+00:00 — urish

Content

And I guess the SRAM isn't 5v tolerant?
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message-1441811783756284056

2025-11-22T15:25:16.815+00:00 — tnt (@246tnt)

Content

Well ... it's in the title, it's a 3.3V SRAM with all the transistors resized from 5V to 3.3V 😅
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2025-11-22T15:25:50.269+00:00 — tnt (@246tnt)

Content

I mean weather it would burst in flames at 5V ... probably not tbh.
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message-1441812859461046353

2025-11-22T15:29:33.283+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

I don't know the breakdown voltage for 3.3V transistors offhand.
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message-1441814815936090162

2025-11-22T15:37:19.743+00:00 — tnt (@246tnt)

Content

Punch-Through Voltage in the spec is 6.5V min
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message-1441814891710382110

2025-11-22T15:37:37.809+00:00 — tnt (@246tnt)

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(from https://gf180mcu-pdk.readthedocs.io/en/latest/analog/spice/elec_specs/elec_specs_1.html )
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2025-11-22T16:40:32.106+00:00 — urish

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So should be fine then?
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message-1441833655143239690

2025-11-22T16:52:11.36+00:00 — tnt (@246tnt)

Content

I guess so, to some extent ...
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2025-11-22T17:38:33.999+00:00 — urish

Content

It's your call
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message-1442294819304243221

2025-11-23T23:24:41.464+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Two thoughts:
 * I have offered Tim Edwards a slot...
 * I'm open to Tiny Tapeout using multiple slots, there should be some spare.

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message-1442384769135546400

2025-11-24T05:22:07.175+00:00 — urish

Content

Thanks Tim!
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2025-11-24T05:22:20.713+00:00 — urish

Content

Re using multiple slots - that's up to Sylvain
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message-1444751452412317899

2025-11-30T18:06:28.439+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Currently working through DRC errors as seen by klayout on the SRAM blocks.  It's a bit tedious but no major issues.
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message-1445486435959570504

2025-12-02T18:47:02.172+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

I have finished both SRAMs (256 byte and 512 byte), all completely DRC clean with respect to both magic and klayout, and LVS verified with magic and netgen.

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2025-12-02T22:07:52.093+00:00 — tnt (@246tnt)

Content

Do you have them in a test chip though ? 😅
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2025-12-03T01:10:44.032+00:00 — Tim Edwards (@rtimothyedwards_19428)

Reply/reference

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Working on it.  I have the picoRV32 openframe project from sky130, and porting it isn't too hard.  Getting it synthesized and verified in one day. . .  That might be tough (although the sky130 version was synthesized and manufactured, so the configuration files exist).  Worst case---I'll just drop a couple of SRAM modules directly into a user project and wire up the I/O by hand.
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message-1445600205776093254

2025-12-03T02:19:07.01+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Tim Edwards - I think we have a bunch of empty 0.5x1 and 1x0.5 slots - it would be great to just have a bunch of SRAM connected to I/O there...
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message-1445600288781369487

2025-12-03T02:19:26.8+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Does anybody happen to know if the `CEN` input to the SRAMs (this applies to the 5V SRAMs as well) is supposed to be always high after reset?  Based on some other implementation of Caravel (which was probably for SkyWater), I have `CEN` toggling with the `valid` signal on the wishbone bus.  I'm not sure if the SRAM is supposed to be operated that way.
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2025-12-03T02:20:09.063+00:00 — Tim Edwards (@rtimothyedwards_19428)

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@Tim 'mithro' Ansell :  I'd have to prepare a 0.5 x 1 mm padframe, though.  How much time are you willing to give me to do that?
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message-1445600494348271738

2025-12-03T02:20:15.811+00:00 — Tim 'mithro' Ansell (@mithro_)

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There was some discussion around it being confusingly name -- I think it was It's CE_N, not C_EN
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message-1445600633758421104

2025-12-03T02:20:49.049+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Tim Edwards - I ***believe*** @Leo Moser (mole99) has/had some prepare padframe for those layouts?
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message-1445600995781513267

2025-12-03T02:22:15.362+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Or do you have custom I/Os too?
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message-1445601036155748352

2025-12-03T02:22:24.988+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  I admit that I have not looked at the tapeout deadline specifics.   What is the last time to get something in?
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message-1445601220084633671

2025-12-03T02:23:08.84+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tim 'mithro' Ansell :  Yes, I have custom I/Os, although in principle the 5V I/Os also work at 3.3V and could be used to test the SRAM.
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message-1445601296110588097

2025-12-03T02:23:26.966+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Current @

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message-1445601460589953139

2025-12-03T02:24:06.181+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

I'm still waiting for some information from GF which might affect that
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message-1445601669445582969

2025-12-03T02:24:55.976+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://www.timeanddate.com/worldclock/fixedtime.html?iso=20251203T2359&p1=3399

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message-1445601960618365029

2025-12-03T02:26:05.397+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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message-1445677658058002504

2025-12-03T07:26:53.073+00:00 — Leo Moser (mole99) (@mole99)

Content

The area and padring definitions for the slots are in: https://github.com/wafer-space/gf180mcu-project-template/tree/main/librelane/slots
 The CI builds a chip with all four different slot sizes, so you can grab a GDS from the Artifacts section at the very bottom: https://github.com/wafer-space/gf180mcu-project-template/actions/runs/19820104811
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message-1445678319927558199

2025-12-03T07:29:30.875+00:00 — Leo Moser (mole99) (@mole99)

Content

@Tim Edwards, have you run the precheck on your design yet?
You can do so via the online platform: https://platform.wafer.space
Or, if that doesn't work, you can pass it to me and I can run the precheck locally for you.
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message-1448789129184935936

2025-12-11T21:30:45.598+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Surprisingly, I found out today that there is an "A[9]" line in the GF SRAM block, and it's connected to row decode circuitry, so at least logically, it's possible to extend the 512 byte SRAM to 1024 bytes.  So I did, and added the block to my test chip.  It's possible that there's a _reason_ that GF didn't have a 1024k macro for their 5V SRAM, and just tied off the A[9] line internally.  But worth finding out!

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message-1448789900160798870

2025-12-11T21:33:49.413+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

Also, since my SRAM test chip was failing antenna checks, I took the opportunity to add antenna tie-downs on all the input pins of the 3.3V SRAM macros that were connected only to FET gates internally.  I'm running the antenna check on the result now;  hopefully that prevents many future issues with the SRAM blocks.  Should try to do the same to the 5V SRAMs.  There's plenty of room right at the bottom to place a contact and a small piece of diffusion under each input line except for the address lines, and the address lines are going through some transmission gate so they're already connected to diffusion and don't need the antenna diode.
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message-1448803185522376725

2025-12-11T22:26:36.89+00:00 — tnt (@246tnt)

Content

I'm wondering, did you draw a schematic / architecure for the SRAM ?
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message-1448811693747601538

2025-12-11T23:00:25.409+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

No, that's on my to-do list.  I don't think I will be able to create a valid netlist for the 1kB SRAM without a schematic, though.  The existing netlists were generated with Calibre and are not schematic captured (and are, frankly, a big mess), so it needs doing and will get done when I get around to it.  For now I'm depending on the simplicity of converting the 512 byte layout to 1kB to be able to eyeball the LVS, but I hope to get proper LVS done before the Wafer.Space tapeout deadline passes.
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message-1450638641461334177

2025-12-17T00:00:03.687+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@tnt :  Today's update to the repository:  Complete schematics for all three SRAM blocks.

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