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#fpgas-online

419 Discord messages from 𐦂𖨆π€ͺπ– ‹ - Friends/fpgas-online/channel.md.

Category: 𐦂𖨆π€ͺπ– ‹ - Friends Channel ID: 1462645850042798101

Messages: 419

message-1462647807860146499

2026-01-19T03:20:12.076+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

This is a channel dedicated to the continued development of https://fpgas.online/ which has previously primarily been developed by @carlfk with the funding provided by @Tim 'mithro' Ansell

The two current highest priority items for development are:
 * Getting all Tiny Tapeout boards onto the site in similar manner as existing Tiny Tapeout 6 board.
 * Getting @bunnie's NeTV2 boards into the site

Other lower priority items include:
 * Getting Tim's other FPGAs into the site, these include @Xobs's Fomu (Tim has pratically unlimited), @Greg's Butterstick (Tim has 8 devices) and @GoranMahovlic's ULX3S (Tim has ~12 devices), GreatScottGadget's Cythion (Tim has ~12 devices) hardware onto the site.
 * Actually using fpgas.online for testing open source FPGA projects.

If anyone has ideas on how to get more people to use the site, that is also something we are very interested in.

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message-1462647878177521694

2026-01-19T03:20:28.841+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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message-1462647982146191420

2026-01-19T03:20:53.629+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

FYI - @Tisham Dhar (CSIRO EASI) / @carlfk / @asic destroyer / @Greg
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message-1462648238526959719

2026-01-19T03:21:54.755+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - @Tisham Dhar (CSIRO EASI) is looking at trying to get my NeTV2 hardware into https://fpgas.online
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message-1462648381980541023

2026-01-19T03:22:28.957+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - IIRC I left a bunch of NiteFury with RPi Compute modules and Compute Cluster blades with you?
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message-1462648887671128075

2026-01-19T03:24:29.523+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@LukeW - @Tisham Dhar (CSIRO EASI) is having some issues with programming the NeTV2 using an RPi 5 because the GPIO have moved from the Broadcom device to the RP1 hardware. I believe the PIO hardware in the RP1 should allow us to do significantly better JTAG driver than what is currently in OpenOCD / openfpgaloader.

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message-1462650790878511270

2026-01-19T03:32:03.283+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

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message-1462650906163155036

2026-01-19T03:32:30.769+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

My stack looks like this now, since I am loading gateware using RPi 4 and accessing PCI-e from Rpi5
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message-1462651620784603289

2026-01-19T03:35:21.148+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

The current pin assignments are here using the old driver : https://github.com/AlphamaxMedia/netv2mvp-scripts/blob/master/alphamax-rpi.cfg

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message-1462655503086915606

2026-01-19T03:50:46.761+00:00 β€” Andrew Wingate (@anfroholic)

Content

This is awesome! Way to go @carlfk!
I've been seeing a lot of work being done here on other channels. Looking forward to seeing more.
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message-1462655881354416261

2026-01-19T03:52:16.947+00:00 β€” Andrew Wingate (@anfroholic)

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I was having a thought the other day.
I know that @asic destroyer ran a whole simulation of his new linux asic, and was curious what size FPGA you would need to do that same thing, and if that would even be applicable here.
I assume that is something larger than you could load on to one of the ARTYboards?
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message-1462728974101909668

2026-01-19T08:42:43.616+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Captured rpi4 working config here : https://github.com/AlphamaxMedia/netv2mvp-scripts/pull/1

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message-1462729228918460457

2026-01-19T08:43:44.369+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

May need a kernel module to make pcileech arrive as a device on the raspi5 pci bus, I will try an M2 Sata to make sure PCI is indeed connected.
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message-1462730989544673392

2026-01-19T08:50:44.135+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I think a NiteFury / 200T can run a Linux ASIC gateware, depends how complicated it is.
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message-1462738363181301885

2026-01-19T09:20:02.147+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

This looks useful for the NeTV2 to slot in : https://geekworm.com/en-au/products/x1010?srsltid=AfmBOopO2oOKLbdXuqHiQd1Poq-Cz4X5Bp7eHgrN7mOhQquOnVFMYTlX

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message-1462742177917567059

2026-01-19T09:35:11.651+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Will need a ribbon to wire up the JTAG
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message-1462904873669496894

2026-01-19T20:21:41.341+00:00 β€” carlfk

Content

What are you jtag-ing?
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message-1462904930066104644

2026-01-19T20:21:54.787+00:00 β€” carlfk

Content

I have a pi hat with a pico on it that does jtag things
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message-1462905108781338677

2026-01-19T20:22:37.396+00:00 β€” carlfk

Content

https://github.com/CarlFK/pj

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message-1462905269272051795

2026-01-19T20:23:15.66+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I am jtaging the NeTV2
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message-1462905409344901355

2026-01-19T20:23:49.056+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

The bitbang JTAG from old references no longer works on Raspi 5.
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message-1462908506536673363

2026-01-19T20:36:07.484+00:00 β€” carlfk

Content

my pj project above was mean to debug pi boot - the pico PIO pins are routed to the Pi jgag.  but I also added a header so they could be hooked to somethint else (like NeTV2)
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message-1462908649075642451

2026-01-19T20:36:41.468+00:00 β€” carlfk

Content

I have no idea if this is helpful, and now I am wondering if being hoked to both will be a problem (seems like it)
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message-1462908779879338159

2026-01-19T20:37:12.654+00:00 β€” carlfk

Content

oh right, the idea was don't plug the hat into the pi, then it isn't hooked to the pi jtag.
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message-1462912288309776609

2026-01-19T20:51:09.129+00:00 β€” carlfk

Content

er.. looking at it in Kicad, there is no jtag header.  I guess the idea is I can use the pi hat header holes for something else if it isn't on a pi
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message-1462913144233000991

2026-01-19T20:54:33.197+00:00 β€” carlfk

Content

I am ordering some other boards this week, $5 for boards, $20 shipping.  I can tweek and add more PJ boards if you think there is some chance of being useful
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message-1462913290601500788

2026-01-19T20:55:08.094+00:00 β€” carlfk

Content

I am 1/2 thnking I need that jgag header I thought was there. but not if no one wants it.
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message-1462917655550890178

2026-01-19T21:12:28.779+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

We already have a mezzanine in the current stack that breaks out the PCI Express, ideally we need a board under like the sample PCI express above and a JTAG like yours wired from the top to the JTAG pins of the NeTV and perhaps RX / TX , power etc.
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message-1462917946371346544

2026-01-19T21:13:38.116+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Attachments

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message-1462918262210957582

2026-01-19T21:14:53.418+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

NeTV JTAG that wires itself to the Pi looks like this. This was a good idea for older pi's, since you could bitbang JTAG on those.
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message-1462918386311893065

2026-01-19T21:15:23.006+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

And have RX/TX to debug or shell into it after gateware loads.
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message-1462919167568122130

2026-01-19T21:18:29.272+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Out of interest, what kind of cable does the RPi PIO JTAG look like to openOCD and openfpgaloader?
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message-1462920780118753331

2026-01-19T21:24:53.734+00:00 β€” carlfk

Content

I am going to plead ignorance.  consider me just the board manufacture that doesn't really know how it works
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message-1462920938214396077

2026-01-19T21:25:31.427+00:00 β€” carlfk

Content

the pico/pio -> pi was desinged by Clever who is makign an open source boot loder to replace broadcom's boot.bin
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message-1462921168586805250

2026-01-19T21:26:26.352+00:00 β€” carlfk

Content

hea had a tangle of wires on his work bench connecting pico to pi, and I made something nice
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message-1462921460019626045

2026-01-19T21:27:35.835+00:00 β€” carlfk

Content

do you have the netv2 schematic URL handy?
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message-1462935740018327606

2026-01-19T22:24:20.452+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Hard to find : https://github.com/AlphamaxMedia/netv2-mainboard/blob/master/netv2mvp-pvt1.pdf

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message-1463050572591796385

2026-01-20T06:00:38.671+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I believe you can use the ulx3s to simulate his design.
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message-1463051301297455291

2026-01-20T06:03:32.408+00:00 β€” Andrew Wingate (@anfroholic)

Reply/reference

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I guess, I was wondering if someone would be able to easily use your guy's internet facing FPGA's to validate designs somehow.
Seems they aren't up to the task.
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message-1463051762478088335

2026-01-20T06:05:22.362+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Well, it's kind of complicated. The big issue is that the Arty has DDR3 memory but @asic destroyer's design only supports SDRAM (which is what is on the ULX3S).

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message-1463051990211756189

2026-01-20T06:06:16.658+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

The actually stuff he is putting on the ASIC should work fine on both FPGAs in theory
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message-1463052110034767964

2026-01-20T06:06:45.226+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

But really you want something like https://fires.im/ -- that makes the FPGA be an ASIC simulation accelerator

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message-1463052788895580215

2026-01-20T06:09:27.079+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Andrew Wingate - I have a bunch of the high end boards which people use for things like that. But as they are like $20k USD each I'm less happy to put them randomly on the internet for anyone to access.
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message-1463052945984716915

2026-01-20T06:10:04.532+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

The NeTV2 and NiteFury cards that @Tisham Dhar (CSIRO EASI) is playing with might be a good option for doing small firesim like stuff with the PCIe connection.
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message-1463053333408256082

2026-01-20T06:11:36.901+00:00 β€” Andrew Wingate (@anfroholic)

Content

Gotcha, thanks. I *correctly* assumed they weren't quite sized for the task, but figured I'd ask anyways.
Cool to see the toolchain exists!
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message-1463053487305785469

2026-01-20T06:12:13.593+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I mean, the designs you are doing on wafer.space probably are pretty reasonable to fit on the Arty / Netv2 / ULX3S sized FPGAs.
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2026-01-20T06:12:35.338+00:00 β€” Andrew Wingate (@anfroholic)

Content

Oh! Amazing!!
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message-1463071134361587765

2026-01-20T07:22:20.979+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I'm guessing the NiteFury II mentioned @ https://docs.fires.im/en/latest/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs.html is probably Ultrascale+ based rather than Series 7 like the original Nitefury?
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message-1463129198599077979

2026-01-20T11:13:04.572+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Reply/reference

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Seems to work with FireSim
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message-1463277372223524965

2026-01-20T21:01:51.917+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Does this indicate the NeTV2 I have is a 100T ? 0x13631093 is the IDCODE for a Xilinx Artix-7 FPGA
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message-1463281370951319726

2026-01-20T21:17:45.288+00:00 β€” carlfk

Content

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message-1463281778679615602

2026-01-20T21:19:22.498+00:00 β€” carlfk

Content

I was going to frame it and hang it on the wall.
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message-1463283226721124383

2026-01-20T21:25:07.738+00:00 β€” carlfk

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https://github.com/AlphamaxMedia/netv2-mainboard/blob/master/hdmi_m2m_jumper-v2.PrjPcb#L92  DocumentPath=C:\Program Files (x86)\Altium\Altium Designer  grumble :p

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message-1463284079775449272

2026-01-20T21:28:31.122+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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@Tim 'mithro' Ansell can probably get sources fully uploaded by Bunny and we can get it all converted to KiCAD and make more , I have found the SQRL Acorn quite affordable due to crypto craze. Just need to reverse engineer and open it.
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message-1463284597688369257

2026-01-20T21:30:34.602+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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According to AI - The JTAG IDCODE 0x13631093 decodes specifically to a Xilinx Artix-7 XC7A100T FPGA.

I'm guessing you have one of the special "dev" NeTV2 which had the 100T rather than the 35T part?
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message-1463284806463914084

2026-01-20T21:31:24.378+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I believe KiCAD can open Altium Designer files these days?
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message-1463284924609073325

2026-01-20T21:31:52.546+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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We should put it on fpgas.online instead πŸ™‚
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message-1463287295586340884

2026-01-20T21:41:17.831+00:00 β€” carlfk

Reply/reference

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Where is the jtag header?
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message-1463295723758944336

2026-01-20T22:14:47.264+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

@carlfk

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message-1463296258474250262

2026-01-20T22:16:54.75+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

We need an RPi hat that attaches a dirty JTAG to those pins, passes through power and Rx TX and may be interrupts , not sure what those do. And also has a PCIe ribbon cable M2 thingie or just an oculink connector at the edge.
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message-1463296419728330876

2026-01-20T22:17:33.196+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

But it will be specific to the NETV2
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message-1463296463231651852

2026-01-20T22:17:43.568+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Not sure how many of those are out in the wild.
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message-1463296916967133266

2026-01-20T22:19:31.747+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I suspect the Pci-leech gateware I am loading is for a 35T precompiled and I am loading on a 100T so it is barfing. I have to setup litex and Vivado and all that jazz to compile gateware for the 100T and do a hello world and see.
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message-1463297074744266886

2026-01-20T22:20:09.364+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I wish OpenOCD had the cross-walk to tell me the FPGA type without giving me a hex.
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message-1463297189773181135

2026-01-20T22:20:36.789+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Would a 35T gateware run on a 100T ?
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message-1463303404439736433

2026-01-20T22:45:18.481+00:00 β€” carlfk

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what is dirty JTAG ?
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message-1463303649747927164

2026-01-20T22:46:16.967+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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https://github.com/dirtyjtag/DirtyJTAG

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message-1463304200594260092

2026-01-20T22:48:28.299+00:00 β€” carlfk

Content

ah - runs on the pico https://github.com/phdussud/pico-dirtyJtag

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2026-01-20T22:49:40.02+00:00 β€” carlfk

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more on this tomorrow - I need to get to PS1 to tell them we have lots of money.  (I'm the treasurer and we have lots of money)
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message-1463394963013374098

2026-01-21T04:49:07.746+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Sketch of the mess to simplify or something. Feel like NeTV2 need a custom pi hat

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2026-01-21T05:27:51.019+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Rebuilding NeTV2 gateware to target the 100T is hard, a lot of the submodules pointed to here are gone : https://github.com/AlphamaxMedia/netv2-fpga

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2026-01-21T05:29:03.436+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Wonder if I can get a pre-built stock gateware for 100T or get that repo maintained for 2026. Last commit from Bunnie points towards the shifting sands of sourcing toolchains at the bleeding edge
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message-1463417136553660531

2026-01-21T06:17:14.33+00:00 β€” ewen (@ewenmcneill)

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Bunnie's on Discord, in the baochip Discord (his current project -- https://www.crowdsupply.com/baochip/dabao) and a few others.
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message-1463417230216921282

2026-01-21T06:17:36.661+00:00 β€” ewen (@ewenmcneill)

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I'd guess he still has a checkout of the dependencies, and probably could rebuild it for the 100T variant.
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message-1463417587525484564

2026-01-21T06:19:01.85+00:00 β€” ewen (@ewenmcneill)

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This post from Bunnie has an invite link for the baochip Discord if you're interested -- https://social.treehouse.systems/@bunnie/115716761132172776

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message-1463435505931784206

2026-01-21T07:30:13.931+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Not sure I can ask for things πŸ˜•
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message-1463438785202356308

2026-01-21T07:43:15.77+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@bunnie is right here too....

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message-1463439483461701643

2026-01-21T07:46:02.248+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@Tisham Dhar (CSIRO EASI) - I probably have 35T versions of the NeTV2 too....
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message-1463497207927017502

2026-01-21T11:35:24.833+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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@bunnie would it be possible to update the netv-fpga repo compile the gateware fixing the sub module linkage etc.
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message-1463566306812100765

2026-01-21T16:09:59.291+00:00 β€” bunnie (@bunnievorpal)

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this is a good question. unfortunately litex has been a moving target and i haven't been able to keep up with it on NeTV
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message-1463566449548464290

2026-01-21T16:10:33.322+00:00 β€” bunnie (@bunnievorpal)

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the best bet is...i need to get back from traveling (currently not at home) and then I have to access my archive machine and dig up the virtual machine I used to build the NeTv2 firmwares
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message-1463566524445888575

2026-01-21T16:10:51.179+00:00 β€” bunnie (@bunnievorpal)

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i stopped schlepping that around years ago since the project had been pretty dormant and it took like 40 gigs on my hard drive
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message-1463566731476992113

2026-01-21T16:11:40.539+00:00 β€” bunnie (@bunnievorpal)

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if i can resurrect the VM it' should have a snapshot of everything as it was back then and may be able to build some things modulo the fact that i've totally forgotten how to use it and hopefully i even remember the password to log into it
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message-1463567156628291772

2026-01-21T16:13:21.903+00:00 β€” bunnie (@bunnievorpal)

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might be a few days before i can try this...i'm kind of compressed until chinese new year. how urgent is it to get a 100T firmware
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message-1463657669175804055

2026-01-21T22:13:01.776+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@Tisham Dhar (CSIRO EASI) - It should be pretty trivial to get the latest LitePCIe going on the NeTV2 once you have a working Vivado environment.
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message-1463658117580722237

2026-01-21T22:14:48.684+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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I will get the Vivado going , then come back here. Last time AMD site would not let me register and download Vivado.
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message-1463658563757936881

2026-01-21T22:16:35.061+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@Tisham Dhar (CSIRO EASI) - Yeah, know that feeling. It would be nice if f4pga was able to do LitePCIe -- https://github.com/openxc7 *might* be able to do it -- but I wouldn't start with that.

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message-1463659198972821505

2026-01-21T22:19:06.508+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Overall though it points to a distribution challenge with FPGA / Litex toolchains. I am sure you are working on a solution.
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message-1463659574690189363

2026-01-21T22:20:36.086+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I remember I proposed docker instead of VM's long time ago, but at that time they were not hardware exposure friendly and images would be too big. Which is what we are trying to solve with FPGAs online, instead of distribution of toolchains we can let users come to a pre-installed stack.
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message-1463659865166712895

2026-01-21T22:21:45.341+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Which for context is what I do in my day job, maintain science coding environments for astronomers and earth observation people.
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message-1463672035602333786

2026-01-21T23:10:06.999+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@Tisham Dhar (CSIRO EASI) - https://bit.ly/edda-conda-eda-spec

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message-1463672231027671062

2026-01-21T23:10:53.592+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - https://docs.google.com/document/d/10_MqFjTIYVVuOJlusJydsp4KOcmrrHk03__7ME5thOI/edit?tab=t.0

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message-1463672448707854427

2026-01-21T23:11:45.491+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@Tisham Dhar (CSIRO EASI) - https://docs.google.com/document/d/1fWV259IbgnenwjRswE9dqCMBfyg8NC2Ily3pGQcw5ck/edit?tab=t.0#heading=h.pocyih7al6a4

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message-1463672538390462514

2026-01-21T23:12:06.873+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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I think packaging and distribution is still one of the unsolved problems in computer science πŸ™‚
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message-1463672642086109266

2026-01-21T23:12:31.596+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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https://github.com/YosysHQ/oss-cad-suite-build

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message-1463771814516756635

2026-01-22T05:46:36.146+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - I just randomly found a PicoEVB in one of my boxes - https://www.crowdsupply.com/rhs-research/picoevb

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2026-01-22T06:23:36.546+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Why does it have so many ufl ?
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message-1463781345334530181

2026-01-22T06:24:28.47+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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I have been trawling Ali and found these : https://a.aliexpress.com/_mrgWC0h
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message-1463781429623132272

2026-01-22T06:24:48.566+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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https://a.aliexpress.com/_m0qC88D
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message-1463783092186648608

2026-01-22T06:31:24.952+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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I don't think you want an ECP3 board
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message-1463785161882861599

2026-01-22T06:39:38.406+00:00 β€” carlfk

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https://kicanvas.org/?repo=https%3A%2F%2Fgithub.com%2FCarlFK%2Fpj%2Fblob%2Fmain%2Fproject%2Fpj.kicad_pro
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message-1463785353596108820

2026-01-22T06:40:24.114+00:00 β€” carlfk

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I suspect I can hack my design to do what you sketched
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message-1463785473385168968

2026-01-22T06:40:52.674+00:00 β€” carlfk

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https://github.com/CarlFK/pj

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message-1463786316331356358

2026-01-22T06:44:13.648+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

The Xilinix one is interesting, it is for cheating at games
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message-1463787217255399435

2026-01-22T06:47:48.445+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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https://www.reddit.com/r/FPGA/comments/1im47cm/are_the_captain_dma_75t_boards_only_for_cheating/

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message-1463788345040572483

2026-01-22T06:52:17.33+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Not in a rush if the netv-fpga repo is updated such that it points to the right submodules I can take it from there. Hopefully that doesn't require dusting off your Vivado VM.
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message-1463851752452395090

2026-01-22T11:04:14.835+00:00 β€” bunnie (@bunnievorpal)

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I can't even register and get it now. I think they might just be blocking everything now....
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message-1463852175099822151

2026-01-22T11:05:55.602+00:00 β€” bunnie (@bunnievorpal)

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I think what happened is Litex restructured its repos in a fundamental way so the submodules are dangling due to that. what I might be able to do is just vendor in a copy of the stuff "detaching" it from the history, since it sort of doesn't matter because they broke the chain of commits by restructuring the repo
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message-1463852284776550401

2026-01-22T11:06:21.751+00:00 β€” bunnie (@bunnievorpal)

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like i think they actually deleted some repos and paths so there's nothing to even refer to
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message-1463863394783465555

2026-01-22T11:50:30.583+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Repo rot and Tool chain rot
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message-1464033961540845815

2026-01-22T23:08:16.867+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - Did we ever explore things like this -> https://52pi.com/collections/sales/products/52pi-19-inch-2u-rack-mount-for-raspberry-pi5-4b-with-10-pcie-nvme-expansion-board-supports-m-2-nvme-ssds ?

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message-1464034145041649865

2026-01-22T23:09:00.617+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - Was this the board you were showing me? https://52pi.com/collections/sales/products/deskpi-super6c-raspberry-pi-cm4-cluster-mini-itx-board-kit-6-rpi-cm4-supported ?

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message-1464034530766880891

2026-01-22T23:10:32.581+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

They also have https://52pi.com/collections/sales/products/rs01-1u-rack-mount-for-raspberry-pi5-4b-with-four-rs-p11-expansion-board-for-rs-p22-raspberry-pi5

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message-1464034693136650381

2026-01-22T23:11:11.293+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

No, I have a Turing Pi, same idea, shared power and ethernet backplane and custom BMC
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message-1464035103050301585

2026-01-22T23:12:49.024+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

https://turingpi.com/product/turing-pi-2-5/

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message-1464035504801583144

2026-01-22T23:14:24.809+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Either way the M2 is great for adding our FPGA's on
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message-1464035859006492964

2026-01-22T23:15:49.258+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I have ordered one of the game hacking 75T's with preloaded firmware (Pci-leech) , will see if it shows up on lspci off the bat.
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message-1464038395562164514

2026-01-22T23:25:54.02+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - I was pondering https://www.amazon.com/erounder-Raspberry-Female-Computer-Accessories/dp/B08H26LY71/ref=sr_1_51

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message-1464039055103758459

2026-01-22T23:28:31.267+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Hmm they are not super useful since Pi-5 GPIO drive for FPGA access is stunted we are better served with cheap dirtyJTAG's, they will be useful for stacking pi4's and more flexible layout, but without the PCI-e , do we really want pi-4's.
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message-1464049284692578507

2026-01-23T00:09:10.191+00:00 β€” Mary Marsh (@marymarsh52975440)

Content

@everyone

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message-1464055434884415508

2026-01-23T00:33:36.511+00:00 β€” carlfk

Reply/reference

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Content

no - but I don't think it helps, and might be worse than the current thing
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message-1464055661208932455

2026-01-23T00:34:30.471+00:00 β€” carlfk

Content

the FPGA board and camera need to be mounted somewhere - adding onto that pi holder seems harder than the little bundle of pi+camera+fpga board
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message-1464056129918206127

2026-01-23T00:36:22.22+00:00 β€” carlfk

Content

never mind harder - routing the usb and eathernet is impracticable - they would have to go over the top, and the dongle cables aren't long enough
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message-1464064067592261827

2026-01-23T01:07:54.709+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Now I am down the game hacking with FPGA rabbit hole and the whole ecosystem there : https://captaindma.com/product/captain-dma-100t-7th/

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message-1464064147611189421

2026-01-23T01:08:13.787+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Should release the NeTV2 to that crowd
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message-1464155232920666154

2026-01-23T07:10:10.217+00:00 β€” bunnie (@bunnievorpal)

Content

(just dropping a note here that someone should @bunnie me if i don't get back to this thread by middle/late next week, my head's L1 cache is full so this might get written to swap shortly and I'll need a tickle to bring this back into my working set)

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message-1464261035639705601

2026-01-23T14:10:35.551+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

So turns out I have to be outside the CSIRO network to download Vivado from AMD, I have it downloaded installed and now synthing 100T bitstream, turns out the pre-built one I was loading was indeed for 35T and failed to launch. OpenOCD performed the board-scan and did not stop me from loading the wrong bitstream πŸ™‚
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message-1464261166137348230

2026-01-23T14:11:06.664+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Receipts : Vivado% source vivado_build.tcl -notrace
-------------------------------------------------------
 STARTING SYNTHESIS STEP.
-------------------------------------------------------
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'pcie_7x_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'bram_pcie_cfgspace'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_66_66'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_41_41_clk2_tlptapcfgspace'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_55_55_clk2_tlptapcfgspace'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_68_34'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_32_32_clk2'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_64_64'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_64_64_clk1_fifocmd'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_34_34'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_256_32_clk2_comtx'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_32_32_clk1_comtx'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_64_64_clk2_comrx'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz'...
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message-1464261617511567440

2026-01-23T14:12:54.28+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

There are warnings like this, which I assume are a bad thing, will see if synth results work : INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinix/2025.2/data/ip'.
WARNING: [IP_Flow 19-2162] IP 'bram_pcie_cfgspace' is locked:
* IP definition 'Block Memory Generator (8.4)' for IP 'bram_pcie_cfgspace' (customized with software release 2020.2) has a different revision in the IP Catalog. * Current project part 'xc7a100tfgg484-2' and the part 'xc7a35tfgg484-2' used to customize the IP 'bram_pcie_cfgspace' do not match.
WARNING: [IP_Flow 19-2162] IP 'fifo_41_41_clk2_tlptapcfgspace' is locked:
* IP definition 'FIFO Generator (13.2)' for IP 'fifo_41_41_clk2_tlptapcfgspace' (customized with software release 2020.2) has a different revision in the IP Catalog. * Current project part 'xc7a100tfgg484-2' and the part 'xc7a35tfgg484-2' used to customize the IP 'fifo_41_41_clk2_tlptapcfgspace' do not match.
WARNING: [IP_Flow 19-2162] IP 'fifo_55_55_clk2_tlptapcfgspace' is locked:
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message-1464266135452258508

2026-01-23T14:30:51.441+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

AND DONE !! k8s@node10:~ $ lspci
0001:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21)
0001:01:00.0 Ethernet controller: Xilinx Corporation Device 0666 (rev 02)<- Devil Device ?
0002:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21)
0002:01:00.0 Ethernet controller: Raspberry Pi Ltd RP1 PCIe 2.0 South Bridge
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message-1464266291866239110

2026-01-23T14:31:28.733+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Time to give it a crack with litepcie
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message-1464396993865715979

2026-01-23T23:10:50.518+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - Great progress!
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message-1464397286598770924

2026-01-23T23:12:00.311+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

This weekend I am playing with the Blackhole from Tenstorrent and recovering from the heat and COVID. Remind me next weekend where the goal posts are.
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message-1464397960409518185

2026-01-23T23:14:40.96+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

How is the BlackHole connected to your computers?
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message-1464426246611144745

2026-01-24T01:07:04.916+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

PCIe over thunderbolt
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message-1464761049243979909

2026-01-24T23:17:28.084+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I have discovered and used this file with installed Litex toolchain. I am going to try the synthesised bitstream and see what I get : https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/kosagi_netv2.py it also produces a driver. Need to read up on what it exactly does in the kernel. Because JTAG loader and synthesis toolchains are on different machines , I have to create a bin file and copy it over. I will also add the working 100T pci-leech bin file to the wiki where I got the pre-built 35T one from. Stuck on my tenstorrent card , so I have dropped that from my working set while I rustle up some help

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    "timestamp": null,
    "title": "litex-boards/litex_boards/targets/kosagi_netv2.py at master Β· lite...",
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message-1464859627111055370

2026-01-25T05:49:10.879+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

@Tim 'mithro' Ansell @bunnie you can leave off the VM dusting Litex has kept the NeTV2 support maintained, at least upto 2 years ago and I can build from their end with this command `python3 -m litex_boards.targets.kosagi_netv2 --build --with-pcie --variant a7-100 --with-ethernet --driver --with-sdcard`

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message-1464859886973227200

2026-01-25T05:50:12.835+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Bitstream when loaded shows up with this Xilinix device on PCI-e Bus of Raspberry pi 5:
0001:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21)
0001:01:00.0 Memory controller: Xilinx Corporation Device 7024
0002:00:00.0 PCI bridge: Broadcom Inc. and subsidiaries BCM2712 PCIe Bridge (rev 21)
0002:01:00.0 Ethernet controller: Raspberry Pi Ltd RP1 PCIe 2.0 South Bridge
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message-1464862330461487216

2026-01-25T05:59:55.408+00:00 β€” bunnie (@bunnievorpal)

Content

oh wow. what? I had no idea that Litex was maintaining a port. That's pretty awesome.

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message-1464862379987959865

2026-01-25T06:00:07.216+00:00 β€” bunnie (@bunnievorpal)

Content

Thank you florent
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message-1465124514773078160

2026-01-25T23:21:45.019+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - So I have the tweed gateway box plugged in now and can access it's BMC. The only problem is that I currently have a single IPv4 IP address.
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message-1465187801489473677

2026-01-26T03:33:13.748+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Looks like I can connect to the machine using the IPv6 address
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message-1465451774834901143

2026-01-26T21:02:09.898+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I was hoping to get tweed up and running but I ended up fighting with vlans and stuff
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message-1465457671636516948

2026-01-26T21:25:35.805+00:00 β€” carlfk

Content

it might be a good time to rebuild the box - there is a new version of Debian and RaspiOS and figure out how to support more than just Arty which I think is all the ansible stuff sets up
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message-1465463617917812818

2026-01-26T21:49:13.509+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - How are the two sites handled again?
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message-1465463927130427542

2026-01-26T21:50:27.231+00:00 β€” carlfk

Content

both dns point to the same IP, nginx did a reditect
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message-1465479541408399514

2026-01-26T22:52:29.965+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I got a one of the DMA game hacking cards off Amazon (a 75T) it comes with a built in CH347 UART + JTAG interface. So can upload things to it via newer openOCD , did upload Pci-leech and that works. Will see if I can register it as a board under Litex and make it do something. Next weekend will document the NeTV2 status in Litex Wiki. CH347 seems to be the easiest / cheapest UART + JTAG in the current setup.  Dirty JTAG's work too I guess. I have some Raspi's Pico's floating around looking for a purpose in life.
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message-1465807089250209916

2026-01-27T20:34:03.456+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - Do you have a link to the DMA game hacking cards?
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message-1465807201015955611

2026-01-27T20:34:30.103+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I also have a box of about 30 x CH347 UARTs here.
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message-1465811474177065114

2026-01-27T20:51:28.904+00:00 β€” carlfk

Reply/reference

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guessing https://captaindma.com/product/captain-dma-75t/

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message-1465813722629935314

2026-01-27T21:00:24.977+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I bought an unbranded hardware on Amazon
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message-1465814099966431355

2026-01-27T21:01:54.941+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

https://www.amazon.com.au/Synpinya-Blender-High-Performance-Direct-Memory/dp/B0FQJ92MX1/

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message-1465814151468154926

2026-01-27T21:02:07.22+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Available on AliExpress as well
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message-1465814426161774654

2026-01-27T21:03:12.712+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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I will take a few and develop a recipe with Raspberry Pi 5 and NeTV2 then you can use that stack to wire up all the boards.
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message-1465817398308241499

2026-01-27T21:15:01.327+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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Content

No DDR memory on that board?
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message-1465817803763351754

2026-01-27T21:16:37.995+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

Guess if you have a decent PCIe link going, you can just use the host's memory....
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message-1465823778432094463

2026-01-27T21:40:22.467+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

It is a super simple card ch347, FPGA, spi flash and ftdi for output if things back to host. It captures game frames and does stuff automatically (target lock for FPS(.
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message-1465827611421708411

2026-01-27T21:55:36.323+00:00 β€” ⠝⠼⠁⠏⠑⠂⠓⠑⠗⠁⠇⠙⠕⠋β ₯β ƒ (@in1pe)

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Content

For what they're meant for x4 is already pretty good
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message-1465827922865684606

2026-01-27T21:56:50.577+00:00 β€” ⠝⠼⠁⠏⠑⠂⠓⠑⠗⠁⠇⠙⠕⠋β ₯β ƒ (@in1pe)

Content

Though I think they generally use USB / Eth to exfiltrate the data
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message-1465828082534322322

2026-01-27T21:57:28.645+00:00 β€” ⠝⠼⠁⠏⠑⠂⠓⠑⠗⠁⠇⠙⠕⠋β ₯β ƒ (@in1pe)

Content

Anticheats will prematurely blacklist drivers and prevent the pages from getting mmio mapped if it looks off
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message-1466284590292275274

2026-01-29T04:11:28.576+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Did you end up writing up instructions on how to use the stuff in the Pici supplies to mount RPis?
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message-1466285209472209189

2026-01-29T04:13:56.2+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I think I should be using these

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message-1466478040837263525

2026-01-29T17:00:10.78+00:00 β€” carlfk

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https://github.com/CarlFK/pici/wiki/Card-Assembly-Procedure

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message-1466478147447951484

2026-01-29T17:00:36.198+00:00 β€” carlfk

Content

that bag of holes is "secure with 4 donuts"
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message-1466478919514325038

2026-01-29T17:03:40.273+00:00 β€” carlfk

Content

There should be 4 assembled ... cards?  sets?  bundles.
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message-1466479095658447072

2026-01-29T17:04:22.269+00:00 β€” carlfk

Content

get those on line, and figue out if you want to add more Arty or add new stuf like NeTV2 or fomu
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message-1466498939271381087

2026-01-29T18:23:13.355+00:00 β€” carlfk

Content

also: Pi5 will need a heat sink and fan - the cpu based video encoding heats it up enough to trip some shutdown thing
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message-1466631774183358589

2026-01-30T03:11:03.666+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Thanks past Carl for writing that up!
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message-1466652390617911605

2026-01-30T04:32:59.007+00:00 β€” carlfk

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well... I'm curious if someone can make sense of it.
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message-1466652603919106048

2026-01-30T04:33:49.862+00:00 β€” carlfk

Content

it's good once you have done it a few times and can't remember what order to do things in
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message-1466652652623630397

2026-01-30T04:34:01.474+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I think I've almost got tweed reconfigured, going to get you a pull request with the changes needed

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message-1466726767296516258

2026-01-30T09:28:31.789+00:00 β€” bunnie (@bunnievorpal)

Content

I'm just circling back to this thread - it looks like the NeTV2 bitrot issue was resolved, so I don't need to dust off the old VM and try to figure that out any more, correct?
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message-1466761946622857246

2026-01-30T11:48:19.194+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Yep Litex works fine and you can make a post somewhere to that effect. I will be testing the 35T this week.

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message-1466762390166048799

2026-01-30T11:50:04.943+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

This CH347 in mode 3 does UART + jtag

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message-1466774037710508083

2026-01-30T12:36:21.934+00:00 β€” bunnie (@bunnievorpal)

Content

I'll try to catch up on some PRs etc on the repo then, thanks for working through this!
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message-1466873070684864786

2026-01-30T19:09:53.235+00:00 β€” carlfk

Content

@Tim 'mithro' Ansell you changed "hardcoded 10.21.0.1"  which looks like it should work fine, but I am wondering why?
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message-1466940375066218719

2026-01-30T23:37:19.85+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - The AI decided it wanted to πŸ˜›
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message-1466940876747047026

2026-01-30T23:39:19.46+00:00 β€” carlfk

Content

that makes things harder to keep track of, so no.
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message-1466941050374459475

2026-01-30T23:40:00.856+00:00 β€” carlfk

Content

please don't make me spend time on AI stuff you have't scrutinized

Reactions

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message-1467209730685538427

2026-01-31T17:27:39.234+00:00 β€” carlfk

Reply/reference

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I hate to ask.. and it bothers me that we are having this conversation - is any of your PR  needed?
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message-1467263745771307162

2026-01-31T21:02:17.434+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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The description seems reasonable to me:

    cmdline.txt and fstab had hardcoded 10.21.0.1 NFS server IPs.
    Convert to Jinja2 templates using {{ eth_local_address }} and
    {{ nfs_root }} so they work across sites with different IPs
    (e.g. welland at 10.31.0.3, PS1 at 10.21.0.1).

The IP address range 10.31.X.X is what I'm using for the fpgas.online in my network.
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message-1467271695474884872

2026-01-31T21:33:52.791+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Can you `ssh -6 root@tweed.welland.mithis.com` ?
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message-1467279672378134815

2026-01-31T22:05:34.633+00:00 β€” carlfk

Reply/reference

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ssh: connect to host tweed.welland.mithis.com port 22: Network is unreachable
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message-1467279753982775490

2026-01-31T22:05:54.089+00:00 β€” carlfk

Content

carl@x1:~$ host tweed.welland.mithis.com
tweed.welland.mithis.com has address 87.121.95.37
tweed.welland.mithis.com has IPv6 address 2404:e80:a137:3100::2
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message-1467279808844267723

2026-01-31T22:06:07.169+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Did you use the `-6` ?
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message-1467279836237271060

2026-01-31T22:06:13.7+00:00 β€” carlfk

Content

yup
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message-1467279864200433664

2026-01-31T22:06:20.367+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Can you ping6 that address then?
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message-1467279942827118899

2026-01-31T22:06:39.113+00:00 β€” carlfk

Content

carl@x1:~$ ping6 2404:e80:a137:3100::2
ping6: connect: Network is unreachable
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message-1467280014591529000

2026-01-31T22:06:56.223+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Can you try a `ping6 www.google.com` ?
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message-1467280065346801664

2026-01-31T22:07:08.324+00:00 β€” carlfk

Content

I have no idea and I would be surprised if I have v6 here on my home lan
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message-1467280108665704773

2026-01-31T22:07:18.652+00:00 β€” carlfk

Content

carl@x1:~$ ping6 www.google.com
ping6: connect: Network is unreachable
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message-1467280230510100522

2026-01-31T22:07:47.702+00:00 β€” carlfk

Content

my router is long overdue for an overhaul - maybe this is the bump I need to do something
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message-1467280477768519939

2026-01-31T22:08:46.653+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

Does PS1 have IPv6 setup?
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message-1467290823925432482

2026-01-31T22:49:53.369+00:00 β€” carlfk

Content

I think so.  cchecking...
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message-1467328920532553908

2026-02-01T01:21:16.308+00:00 β€” carlfk

Content

well.. my boxes aren't configed for v6.  but I suspect I can dhcp6 or something
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message-1467413992736690248

2026-02-01T06:59:19.102+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Reply/reference

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@bunnie I am wiring up the CH347 to the NeTV2, will make a wiring diagram as part of making it work with Raspberry Pi 5, does the netv2 have an on board JTAG chip / programming port ? On the JTAG port attached to the Raspberry Pi is the RST pin equivalent of SRST on JTAG ?
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message-1467414555872460951

2026-02-01T07:01:33.364+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Attachments

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message-1467432361196261388

2026-02-01T08:12:18.484+00:00 β€” bunnie (@bunnievorpal)

Content

the ⁨`RES`⁩ pin next to GND goes to PROGRAM_B on the FPGA
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message-1467432405316010066

2026-02-01T08:12:29.003+00:00 β€” bunnie (@bunnievorpal)

Content

in other words, holding that low will fully reset the FPGA and cause it to reload its bitstream
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message-1467432477231546410

2026-02-01T08:12:46.149+00:00 β€” bunnie (@bunnievorpal)

Content

it's not a jtag reset
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message-1467432507413762144

2026-02-01T08:12:53.345+00:00 β€” bunnie (@bunnievorpal)

Content

it's a full system reset
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message-1467756463677112372

2026-02-02T05:40:10.537+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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The IP address changes are needed due to changes in my networking.
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message-1467756858084425885

2026-02-02T05:41:44.571+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@bunnie - I notice the boards have that USB connector and chip, is that just a UART or could that be used to program things too? @Tisham Dhar (CSIRO EASI)  Does that USB exist on the 35t boards too?
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message-1467757198808711290

2026-02-02T05:43:05.806+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Yea the 35T has an FTDI chip and a USB connector, I was wondering if that was an on-board JTAG
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message-1467757389678907423

2026-02-02T05:43:51.313+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I haven't tested the CH347 with 35T yet. Was just confirming the wiring
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message-1467758597592186902

2026-02-02T05:48:39.302+00:00 β€” bunnie (@bunnievorpal)

Content

you mean the microUSB connector to the right of the HDMI connector? it's just a pair of FPGA pins brought out to a microUSB.
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message-1467758711513681922

2026-02-02T05:49:06.463+00:00 β€” bunnie (@bunnievorpal)

Content

i think the idea is that if you wanted to add e.g. a valentyUSB core to it you could do so
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message-1467793670827802825

2026-02-02T08:08:01.413+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

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message-1467793740633473156

2026-02-02T08:08:18.056+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I mean this one on the 35T
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message-1468400756645302352

2026-02-04T00:20:21.951+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Tried flashing the NeTV2 with my CH347T, no joy, raspberry pi does pick it up as a JTAG+UART, so that's a win. Could I please get a definitive wiring diagram from the CH347 to the NeTV2 JTAG port.
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message-1468401033855238164

2026-02-04T00:21:28.043+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

The images above should have all the footprints and pinouts. My instinct on how JTAG wiring works seems off and the Captain DMA boards which using CH347 JTAG don't have open designs.
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message-1468429176141910187

2026-02-04T02:13:17.687+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - I would expect that if OpenOCD is able to do things like read the FPGA ID and then program the SPI flashing gateware to write to the spi flash you have things connected correctly.
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message-1468429255003344916

2026-02-04T02:13:36.489+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - It might also be worth trying with the Xilinx JTAG adapter first too.
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message-1468484845696061543

2026-02-04T05:54:30.343+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

The programmer is not so much an issue as wiring it up correctly.
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message-1468484957000302734

2026-02-04T05:54:56.88+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

The FPGA if fetched is not correct indicating I haven't mapped it nicely
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message-1469049334942404711

2026-02-05T19:17:35.067+00:00 β€” carlfk

Reply/reference

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https://github.com/CarlFK/pici/wiki/ServerSetup  that image, you made the first version.  maybe that version. Any idea where the source is?

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message-1469074719872647321

2026-02-05T20:58:27.306+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - That was a Google Drawing - I believe it is in the folder @ https://drive.google.com/drive/folders/103OYiqZFsTi16W23VrjE-Wm-A9bftEVj?usp=drive_link

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message-1469081113589977220

2026-02-05T21:23:51.687+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - Did you ever see this diagram -> https://docs.google.com/drawings/d/1N9guhJIMGBHqsPUN32olwNP8XzjwhM52Qibt6FMoyq0/edit ?

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message-1469081696598102253

2026-02-05T21:26:10.687+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Doesn't look like that diagram ended up in that folder...
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message-1469081978622968033

2026-02-05T21:27:17.927+00:00 β€” carlfk

Content

agreeed. it was made long before fpgas.online was regeisted
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message-1469082274975973629

2026-02-05T21:28:28.583+00:00 β€” carlfk

Content

search your drive for "Independent" - and page though the 100 hits :p
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message-1469082448116842597

2026-02-05T21:29:09.863+00:00 β€” carlfk

Content

really this was to give you a starting point for explaing your IP address needs
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message-1469655153857659067

2026-02-07T11:24:53.552+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

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message-1469655473257971764

2026-02-07T11:26:09.703+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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The GPIO for programming in that diagram is not feasible. I am trying to replace it with CH347 over USB
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message-1469882279542263880

2026-02-08T02:27:24.535+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - I was really talking about all the other connections
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message-1469992819451232307

2026-02-08T09:46:39.303+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

All other connections seem to work and should be part of the build.
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message-1471994679883993180

2026-02-13T22:21:20.023+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk -

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message-1471995440072359957

2026-02-13T22:24:21.266+00:00 β€” carlfk

Content

\o/
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message-1471996413767585876

2026-02-13T22:28:13.413+00:00 β€” carlfk

Content

did you make the font smaler or something?  There seems to be more chars in the shell terminal
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message-1472009688580358361

2026-02-13T23:20:58.375+00:00 β€” carlfk

Content

@Tim 'mithro' Ansell now we get to play Why doesn't it boot?
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message-1472009860257157172

2026-02-13T23:21:39.306+00:00 β€” carlfk

Content

https://welland.fpgas.online/fpgas/pi25.html  the Pi did a dhcp request, evidance is the server responce:
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message-1472009923452993606

2026-02-13T23:21:54.373+00:00 β€” carlfk

Content

4:38:26 PM: dnsmasq: dhcp old b8:27:eb:47:9f:d1 10.31.0.125 pi25 rpi-47-9f-d1
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message-1472012670285774930

2026-02-13T23:32:49.269+00:00 β€” carlfk

Content

I'm ssh to tweed.  I can guess the setup, but a diagram might be nice
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message-1472075791536754780

2026-02-14T03:43:38.548+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I wouldn't touch tweed at the moment, I'm trying to get the AI to summarize the changes it made
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message-1472320746826105086

2026-02-14T19:57:00.44+00:00 β€” carlfk

Reply/reference

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@Tim 'mithro' Ansell have it make digrams untill it matches how you connected the wires :p
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message-1472320857534890034

2026-02-14T19:57:26.835+00:00 β€” carlfk

Content

I'm a little affraid you have 2 dhcp servers on the same ... subnet?  lan?  whatever you don't want
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message-1472370455724822600

2026-02-14T23:14:31.965+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I think I have fixed that with vlans, but there are some complications.
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message-1472370788098113741

2026-02-14T23:15:51.209+00:00 β€” carlfk

Content

I think AI broke it beyond repair
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message-1472371329314590816

2026-02-14T23:18:00.245+00:00 β€” carlfk

Content

https://github.com/CarlFK/pici/blob/main/ansible/roles/pxe/templates/pibs.conf.j2

Embeds

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message-1472371355566604288

2026-02-14T23:18:06.504+00:00 β€” carlfk

Content

# 4th IP octet = 100+index x.y.z.103
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message-1472371665617948704

2026-02-14T23:19:20.426+00:00 β€” carlfk

Content

dhcp-range=10.31.0.128,10.31.0.254,255.255.0.0,12h
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message-1472371735520219188

2026-02-14T23:19:37.092+00:00 β€” carlfk

Content

100 to 127 are ... I have no idea what happens.
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message-1472428960984993792

2026-02-15T03:07:00.706+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I'm going to rework my home network so that the fpgas and IPs stay at 10.31.X.X rather than having to move to 10.41.X.X which should reduce the curn in the pici ansible
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message-1472429244847230976

2026-02-15T03:08:08.384+00:00 β€” carlfk

Content

im still curious what you are trying to do
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message-1472429460451233964

2026-02-15T03:08:59.788+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

Oh, wait it looks like pici uses 10.21.X.X ?
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message-1472429921271021740

2026-02-15T03:10:49.656+00:00 β€” carlfk

Reply/reference

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correct
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message-1472430797658128545

2026-02-15T03:14:18.603+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I'm trying to fit an "isolated network" of the fpgas.online hardware into my home network which is also trying isolate the supermicro BMC/coreboot hardware, the IoT network, the guest network and such. The goal is to prevent accidental exposure of my servers to devices which random people can connect too.
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message-1472431328510083259

2026-02-15T03:16:25.168+00:00 β€” carlfk

Content

the PIs and everyting else on the same PoE switch?
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message-1472431588825628807

2026-02-15T03:17:27.232+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

Internet --> ten64.welland.mithis.com (gateway machine) --> Random networking hardware --> tweed --> PoE switch --> RPis
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message-1472431686108188935

2026-02-15T03:17:50.426+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - And unlike in the US, I only have one public static IPv4 address rather than a small number of them.
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message-1472432279329702050

2026-02-15T03:20:11.861+00:00 β€” carlfk

Content

I suspect it will be easier to put tweed in place of ten64
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message-1472432787029098496

2026-02-15T03:22:12.906+00:00 β€” carlfk

Content

but if you have figured out how to tunnel to tweed, good.
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message-1472433596382974004

2026-02-15T03:25:25.871+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I can't do that because I need ten64 for my home network. As I said, unlike in Sunnyvale where I could give tweed a public IPv4 address I can't do that here.
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message-1472433801677373526

2026-02-15T03:26:14.817+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I also have the problem that tweed and the fpgas are a *long* way away from the internet ingress point, so there is a bunch of networking equipment between the gateway and tweed.
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message-1472434751444091014

2026-02-15T03:30:01.259+00:00 β€” carlfk

Content

long = too long for a run of cat5?
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message-1472434890199928973

2026-02-15T03:30:34.341+00:00 β€” carlfk

Content

im not really sure what the real limit is
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message-1472435209369686100

2026-02-15T03:31:50.437+00:00 β€” carlfk

Content

is outgoing byte count something to wory about?
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message-1472435342731771904

2026-02-15T03:32:22.233+00:00 β€” carlfk

Content

the home page of videos are not scaled server side - I send the full res and the player is shurnk
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message-1472441778614571171

2026-02-15T03:57:56.667+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

The site has 1Gbs down / 100Mbit up
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message-1472441885539962921

2026-02-15T03:58:22.16+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I think a cat6 cable might just reach but it'll be a while before I can run that cable.
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message-1472698818133758084

2026-02-15T20:59:19.664+00:00 β€” carlfk

Content

@Tim 'mithro' Ansell how easy can you hook up 2 TT boards (different runs) to anything I can ssh to.  tweed or a arty pi.  or whatever.  something I can text how to address differenrt boards
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message-1472698981585912011

2026-02-15T20:59:58.634+00:00 β€” carlfk

Content

the one board I have online can us /dev/serial/by-id/usb-MicroPython_Board_in_FS_mode_de640cb1d3975a26-if00
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message-1472699168496554199

2026-02-15T21:00:43.197+00:00 β€” carlfk

Content

I'm wondering how unique  de640cb1d3975a26
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message-1472735368733261985

2026-02-15T23:24:34.006+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk If you remind me on Wednesday, it should be pretty easy in theory.

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message-1472736050488152269

2026-02-15T23:27:16.549+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I"m up at Monarto setting things for my parents until late tomorrow.
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message-1472736098516992197

2026-02-15T23:27:28+00:00 β€” carlfk

Content

@Tim 'mithro' Ansell I need help - I think git sub-modules is the answer.
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message-1472736199650181222

2026-02-15T23:27:52.112+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

git submodules is an answer, it is rarely a good answer despite how much we use it πŸ˜›

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message-1472736245234008267

2026-02-15T23:28:02.98+00:00 β€” carlfk

Content

to boot Kianv o tt6, I need this stuff https://github.com/CarlFK/tt-commander-app/blob/feature/cli_bl910/src/ttcontrol/cli/boot_kianv_ulinux.sh

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message-1472736529125343379

2026-02-15T23:29:10.665+00:00 β€” carlfk

Content

part of the problem is the Arty fpga thing expanded to TT, and kinda just the 1 Kianv thing
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message-1472740553883123867

2026-02-15T23:45:10.242+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - My plan is that when @Matt Venn and friends finish the TT FPGA emulation board, then we will have a bunch of those in the pool.
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message-1472740678885834763

2026-02-15T23:45:40.045+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - I'm not game to do the vlan rename to fix the IP address stuff while I'm remote πŸ˜›
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message-1472742210733867168

2026-02-15T23:51:45.266+00:00 β€” carlfk

Content

@Tim 'mithro' Ansell im still stuck on how to get little_term.py on or close to the rp2040
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message-1472742321551573042

2026-02-15T23:52:11.687+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

`little_term.py` meaning `litex_term.py` or?
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message-1472743574096576572

2026-02-15T23:57:10.317+00:00 β€” carlfk

Content

https://github.com/CarlFK/tt-commander-app/blob/feature/cli_bl910/src/ttcontrol/cli/little_term.py

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message-1472743967396331530

2026-02-15T23:58:44.087+00:00 β€” carlfk

Content

your ssh client -network- Pi -usb serial- RP2040 -uart serial- TT06 / 910 (KianV Linux)
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message-1472744069305470996

2026-02-15T23:59:08.384+00:00 β€” carlfk

Content

little_term.py runs on RP2040 to connect  Pi -usb serial- to -uart serial- TT06
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message-1472745011895472321

2026-02-16T00:02:53.115+00:00 β€” carlfk

Content

`mpremote fs cp little_term.py :` is the final step to install it, but none of the steps are automated.
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message-1472745176639213578

2026-02-16T00:03:32.393+00:00 β€” carlfk

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I'm trying to make it part of https://github.com/CarlFK/pici/wiki/Install

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message-1472772958706471073

2026-02-16T01:53:56.154+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I think your text diagram is a little bit hard to understand?

Is this what you mean?
`<something> <-????-> ssh client <- network -> RPi <- usb serial -> RP2040 <- UART serial -> TT06 Chip (Running 910 - KianV Linux)`
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message-1472773192010567781

2026-02-16T01:54:51.778+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

BTW I have been learning about conserver which seems to be a tool for sharing serial ports over the network and supports things like multiple connections, logging the output and such.....
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message-1472773479337299980

2026-02-16T01:56:00.282+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I've recently started getting it working with the BMC serial over lan ports and also the USB-serial adapter on a RPi Zero which is connected to the consoles on my netgear network switches
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message-1472784065814859947

2026-02-16T02:38:04.295+00:00 β€” carlfk

Reply/reference

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Content

yes - as long as you understand what little_term.py does
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message-1472784455704903766

2026-02-16T02:39:37.252+00:00 β€” carlfk

Reply/reference

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Content

What is BMC serial?
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message-1472784696378265650

2026-02-16T02:40:34.633+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

BMC == Board Management Controller -- it's a little Linux computer that is found on server motherboards which allows you to remotely access things like the power buttons, virtual vga screen, virtual serial port, etc....
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message-1472786533978345616

2026-02-16T02:47:52.751+00:00 β€” carlfk

Reply/reference

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ok - I undersatnd BMC - how does serial fit in?
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message-1472787591064457321

2026-02-16T02:52:04.78+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

The BMC lets you connect to the computer's serial port so you can see things like very early BIOS messages or if the linux running on the system is configured correctly even a console. Provides a way to get access to the machine when SSH isn't working or similar. I wanted computers like tweed to output dmesg messages to their serial port and log them so I could see things like kernal panics and such, hence why I was looking at conserver.

But it seems like conserver could be useful for just generally providing remote access to usb serial ports in an RPi as it deals with the problem of multiple devices trying to access the serial port at once (IE you could be connected with something like cu at the same time you connect little_term and another python script)....
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message-1472788609609371842

2026-02-16T02:56:07.62+00:00 β€” carlfk

Content

I'm skeptical :p - the only time I have that problem is when I forget I alreaday have something conected.
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message-1472789054188687390

2026-02-16T02:57:53.616+00:00 β€” carlfk

Content

for early dmesg messages - do you know about https://www.kernel.org/doc/Documentation/networking/netconsole.txt
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message-1472789233226748087

2026-02-16T02:58:36.302+00:00 β€” carlfk

Content

pass a kernel parameter append ... netconsole=@192.156.1.5/eth0,@192.168.1.3/00:08:02:a0πŸ†Žcf
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message-1472789386709172397

2026-02-16T02:59:12.895+00:00 β€” carlfk

Content

very early it smashes that ip config and starts spewing udp
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message-1472791416953372724

2026-02-16T03:07:16.943+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I did in the past but had forgotten about that....
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message-1472791991841718405

2026-02-16T03:09:34.007+00:00 β€” carlfk

Content

I https://github.com/CarlFK/pici/blob/main/ansible/roles/fixpi/files/boot/ncc.py

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message-1472792102789447782

2026-02-16T03:10:00.459+00:00 β€” carlfk

Content

that beeps when it recieves, which is often when the box is crashing
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message-1472839247970177153

2026-02-16T06:17:20.746+00:00 β€” Matt Venn (@mattvenn)

Content

Fpga boards are now in the tt shop
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message-1473438164461817980

2026-02-17T21:57:13.565+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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Now there are less FPGA boards in your shop πŸ™‚

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message-1473796975521562634

2026-02-18T21:43:00.788+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I setup a couple more of the Tiny Tapeout boards on RPis here for you
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message-1473797029158322198

2026-02-18T21:43:13.576+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - But I had the realisation this morning that I was doing the vlans slightly wrong
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message-1473797293986545737

2026-02-18T21:44:16.716+00:00 β€” carlfk

Content

I'm not sure what to do wiht this
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message-1473797350215520356

2026-02-18T21:44:30.122+00:00 β€” carlfk

Content

a diagram of what you have done would probably help
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message-1473801013310918707

2026-02-18T21:59:03.472+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Don't worry about it, give me about an hour and I should have it all fixed up
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message-1473809941214134353

2026-02-18T22:34:32.05+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Basically, the connection between ten64 (the gateway) and tweed's uplink port should be a *different* vlan to tweed's local port and the RPis so I end up with:

  [tfpgas.ten64] <-- tfpga vlan on switches --> [eth-uplink.tweed : eth-local.tweed] <-- fpga vlan on S3300-1 --> [RPis]
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message-1473811589298651207

2026-02-18T22:41:04.984+00:00 β€” carlfk

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S3300-1 is a switch?
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message-1473812351722586143

2026-02-18T22:44:06.76+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

Yes.
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message-1473815110190502072

2026-02-18T22:55:04.43+00:00 β€” carlfk

Content

A picture would answer these questions
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message-1473815279535653076

2026-02-18T22:55:44.805+00:00 β€” carlfk

Content

is  "tfpga vlan on switches" include the - ":fpga vlan on S3300-1"  ?
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message-1473815616556372251

2026-02-18T22:57:05.157+00:00 β€” carlfk

Content

the PoE control code can and does have "turn off all the PoE on all the ports" which might brick the thing until pull the power cord and maybe poke the reset hole
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message-1473824455024316476

2026-02-18T23:32:12.412+00:00 β€” carlfk

Content

https://github.com/CarlFK/pici/blob/main/ansible/roles/site/files/pib/snmp_switch/scripts/allpoeoff.sh

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message-1473825665290862847

2026-02-18T23:37:00.962+00:00 β€” carlfk

Content

there is /etc/environment ... pi_ports="2 3 5 7 9 11 13 21 23 "  which is only the ports in ansible inventory but thats only good/valid for what is stable, not experimenting with new things, like adding a TT setup to the fpga/arty setup
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message-1473827644369010729

2026-02-18T23:44:52.811+00:00 β€” carlfk

Content

also in /etc/environment  is `SNMP_SWITCH_AUTHKEY=` which I think needs an export for `source /etc/environment`  but adding export to that file will break EnvironmentFile=/etc/environment
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message-1473827655483916320

2026-02-18T23:44:55.461+00:00 β€” carlfk

Content

https://github.com/CarlFK/pici/blob/main/ansible/roles/site/templates/daphne.service.j2#L10C1-L10C33

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message-1473827778939060329

2026-02-18T23:45:24.895+00:00 β€” carlfk

Content

I could use some help with that.
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message-1473830982661574656

2026-02-18T23:58:08.722+00:00 β€” carlfk

Content

https://github.com/CarlFK/pici/issues/51

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message-1474688694739931217

2026-02-21T08:46:23.217+00:00 β€” carlfk

Content

I just added a Ping button to help figure out if a pi is alive
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message-1474688706513207493

2026-02-21T08:46:26.024+00:00 β€” carlfk

Content

https://github.com/CarlFK/pici/blob/main/ansible/roles/site/files/pib/pistat/src/pistat/views.py#L67

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message-1474688777803796596

2026-02-21T08:46:43.021+00:00 β€” carlfk

Content

https://ps1.fpgas.online/fpgas/pi21.html
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message-1474689029273292956

2026-02-21T08:47:42.976+00:00 β€” carlfk

Content

4:52:28 PM: piview: Raspberry_Pi_5_Model_B_Rev_1
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message-1474689088136151121

2026-02-21T08:47:57.01+00:00 β€” carlfk

Content

it might still be over heating and turning itself off
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message-1474951913664679977

2026-02-22T02:12:19.499+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - I was able to program the NeTV2 FPGA on a RPi5 using the GPIO headers.
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message-1474954564196368415

2026-02-22T02:22:51.435+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Same ones or different ones ?
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message-1474954644810891368

2026-02-22T02:23:10.655+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

OpeOCD linuxgpiod driver ?
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message-1475244966962790540

2026-02-22T21:36:48.85+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - Initially I was using OpenOCD with the gpiod driver (which was quite slow but still worked), but it looks like Claude has managed to create a new driver using the PIO found in the RP1 chip which is faster than the original broadcom bitbanging driver - https://github.com/mithro/rp1-jtag

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message-1475245932118282280

2026-02-22T21:40:38.961+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

There is no drivers openOCD, push that to git and I will have a go with the NeTV2 I have here
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message-1475246036124700704

2026-02-22T21:41:03.758+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I will vendor it into OpenOCD tree and compile it there.
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message-1475246455882256466

2026-02-22T21:42:43.836+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

Claude hasn't finished the OpenOCD integration, but it has finished the openFPGAloader version
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message-1475246750041116733

2026-02-22T21:43:53.969+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - I could use some testing firmware to verify things beyond just reading the Xilinx ID and loading the spiflash proxy.
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message-1475257894759829624

2026-02-22T22:28:11.077+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - Did you do that write up building LiteX firmware for the NeTV2 anywhere?
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message-1475271571244581025

2026-02-22T23:22:31.805+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I chucked it in my blog
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message-1475284638200107202

2026-02-23T00:14:27.21+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Install LiteX following the standard setup, then:

cd litex-boards/litex_boards/targets

# Build for XC7A35T variant with Ethernet
./kosagi_netv2.py --variant=a7-35 --with-ethernet --build

# Or for the 100T variant with PCIe
./kosagi_netv2.py --variant=a7-100 --with-pcie --build
The target supports:

DDR3 SDRAM: Using the K4B2G1646F module with LiteDRAM
Ethernet: RMII PHY via LiteEth
PCIe: x4 Gen2 via LitePCIe
SD Card: Both SPI mode and native SDIO
LED Chaser: For the obligatory blinky demo
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message-1475305689747427531

2026-02-23T01:38:06.29+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

I probably have the compiled bitstreams for Litex and PCI Leech floating around will find them in a few minutes after lunch.
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message-1475335267710664704

2026-02-23T03:35:38.226+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

@Tim 'mithro' Ansell  if you have a 35T then the bitstream is at the bottom of this page : https://github.com/ufrisk/pcileech-fpga/blob/master/NeTV2/readme.md

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message-1475336133733777479

2026-02-23T03:39:04.702+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

100T bitstream

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message-1475388252218331136

2026-02-23T07:06:10.717+00:00 β€” carlfk

Reply/reference

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Content

blog url?
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message-1475393765488201860

2026-02-23T07:28:05.183+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Complete with code snippets : https://whatnicklife.blogspot.com/2026/01/loading-fpga-bitstreams-with-openocd.html?m=0

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message-1475616310347042896

2026-02-23T22:12:24.012+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike - According to Claude you have done a bunch of work with the RP1 in the RPi5
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message-1475616592380432444

2026-02-23T22:13:31.254+00:00 β€” RebelMike (@rebelmike)

Content

I did some stuff trying to hack it when it first came out
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message-1475616737503350985

2026-02-23T22:14:05.854+00:00 β€” RebelMike (@rebelmike)

Content

There's piolib now though so you don't need to find an exploit just to use the PIOs πŸ˜…
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message-1476332673378025533

2026-02-25T21:38:58.268+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike - I have a crazy idea of having the RPi5 emulate larger (IE megabyte sized) spiflash/psram with the PIO for use both with Tiny Tapeout and BMC motherboard development -- kinda of a more advanced version of your emulation on the RP2040.

It looks like originally it was quite hard to get >10 Megabyte/second transfers between the RPi5 and PIO device but it looks like ~20->40 Megabyte/seconds might be possible now.

 * https://github.com/mithro/rp1-jtag
 * https://github.com/mithro/rpi5-rp1-pio-bench

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message-1476333226330034186

2026-02-25T21:41:10.102+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@Tisham Dhar (CSIRO EASI) - I should have debs and static versions of openFPGAloader with the rpi1-jtag support being built now

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message-1476334583413739562

2026-02-25T21:46:33.656+00:00 β€” tnt (@246tnt)

Content

I'm not sure what kind of latency you'd manage to get given there is PCIe in the middle ...
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message-1476334706877399205

2026-02-25T21:47:03.092+00:00 β€” RebelMike (@rebelmike)

Content

I suspect getting deterministic performance over the PCIe bus would be tricky. I would have thought a RP2350 with PSRAM attached (maybe to GPIO instead of through XIP) would be preferable
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message-1476335030459433102

2026-02-25T21:48:20.24+00:00 β€” RebelMike (@rebelmike)

Content

Although at that point why not just actually attach the PSRAM to the project. I guess you could support slightly different protocols, although never at a high clock speed
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message-1476335716895293583

2026-02-25T21:51:03.899+00:00 β€” RebelMike (@rebelmike)

Content

One thing I think Pi 5 could be great at that I haven’t seen (though I haven’t looked recently) is a cheap logic analyser. PIO should be able to sample pins at 200MHz and you have reasonably fast access to GBs of memory
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message-1476339076289265879

2026-02-25T22:04:24.841+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike / @tnt - I'll see what claude is able to do here if I put some hardware in the loop and let it iterate.
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message-1476339109181263884

2026-02-25T22:04:32.683+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I ***also*** have the crazy idea of using the RP1 PIO to do a C code LUNA type stack where you can to USB1/USB1.1/UTMI/ULPI on the GPIO pins.
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message-1476340400225779803

2026-02-25T22:09:40.492+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I don't think the USB idea would be very useful but it might be fun to try anyway....
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message-1476344765653057688

2026-02-25T22:27:01.291+00:00 β€” RebelMike (@rebelmike)

Content

For USB there's https://github.com/sekigon-gonnoc/Pico-PIO-USB which only needs one PIO so might work - probably mainly depends on whether there's any latency issues.

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message-1476345328944021757

2026-02-25T22:29:15.59+00:00 β€” RebelMike (@rebelmike)

Content

As far as I'm aware there's no facility for running code on the RP1's spare ARM core - but when it became clear Raspberry Pi weren't realy interested in making it possible for the community to do stuff in this area I kind of lost interest in it so I don't know about any more recent work
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message-1476348176540762124

2026-02-25T22:40:34.51+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@RebelMike - It appears that cleverca22 has been doing your logic analyser stuff https://github.com/cleverca22/libsigrok/commit/e3783bac8176e7454863b37723ab6d8a3f99731a

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message-1476351656169050163

2026-02-25T22:54:24.118+00:00 β€” RebelMike (@rebelmike)

Content

Cool!
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message-1476449038847971440

2026-02-26T05:21:21.958+00:00 β€” urish

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Content

How about using an FPGA for that?
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message-1476449202153193614

2026-02-26T05:22:00.893+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@urish - You mean like spispy? πŸ˜›
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message-1476449487194034258

2026-02-26T05:23:08.852+00:00 β€” urish

Content

I think so
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message-1476450053899026452

2026-02-26T05:25:23.965+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

That is what I'm planning on using at the moment

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message-1476630438016581642

2026-02-26T17:22:10.89+00:00 β€” carlfk

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@clever helped me with fpga.online pi net boot
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message-1476631064175968368

2026-02-26T17:24:40.178+00:00 β€” carlfk

Content

which lead to https://kicanvas.org/?github=https%3A%2F%2Fgithub.com%2FCarlFK%2Fpimo%2Ftree%2Fmain%2Fproject
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message-1476676960598884546

2026-02-26T20:27:02.738+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - I was going to tell you to invite @clever to this channel but it turns out he is already here!
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message-1476677016647500043

2026-02-26T20:27:16.101+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - I think the corporate world would call this "synergy" πŸ˜›
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message-1477148253144486131

2026-02-28T03:39:47.637+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

@Tim 'mithro' Ansell  rpi-pio-jtag talking to NeTV2 35T ->

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message-1477148336728444998

2026-02-28T03:40:07.565+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

OpenFPGALoader is patched and built , however it is saying empty on detect
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message-1477150289671880805

2026-02-28T03:47:53.183+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

Never mind , setting pins makes it work
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message-1477150345242087546

2026-02-28T03:48:06.432+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Making a PR
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2026-02-28T03:48:33.249+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

Content

k8s@node10:~/openFPGALoader $  cd /home/k8s/openFPGALoader && sudo ./build/openFPGALoader -c rp1pio --detect 2>&1
empty
rp1pio: using default pins TCK=4 TMS=17 TDI=27 TDO=22
index 0:
        idcode 0x362d093
        manufacturer xilinx
        family artix a7 35t
        model  xc7a35
        irlength 6
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message-1477153529184649368

2026-02-28T04:00:45.543+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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https://github.com/mithro/rp1-jtag/pull/4

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message-1477153716967706657

2026-02-28T04:01:30.314+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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Lemme know if you are working on the OpenOCD implementation. I have Copilot hopping on that. I cannot test it under lspci yet since I dont have a power supply.
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message-1477255217450844231

2026-02-28T10:44:49.915+00:00 β€” Tisham Dhar (CSIRO EASI) (@tishamdhar)

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OpenOCD works too : https://github.com/mithro/rp1-jtag/pull/5

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message-1480348320135123128

2026-03-08T23:35:43.062+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

I should have 4 * Tiny Tapeout FPGA dev boards available for anyone to play with on https://fpgas.online in the next couple of days. Sadly it seems the USB-C PoE adapters I have are borked in some way (they supply power but block ethernet link) but I have some higher quality ones arriving tomorrow.
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message-1480348443925942313

2026-03-08T23:36:12.576+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - Did you see that behaviour like that with those adapters at all?
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message-1480348794741854229

2026-03-08T23:37:36.217+00:00 β€” carlfk

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maybe?
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message-1480348836244357301

2026-03-08T23:37:46.112+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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I decided to buy a whole bunch of these adapters -> https://www.waveshare.com/poe-splitter-type-c.htm

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message-1480349017669107865

2026-03-08T23:38:29.367+00:00 β€” carlfk

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I've had various problems with all the things.  so trying to pin down exactly what any one problem is gets tedious
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message-1481742001056649229

2026-03-12T19:53:42.487+00:00 β€” carlfk

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@Tim 'mithro' Ansell TT boards or something in TT boxes arrived  - havn't had time to open
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message-1481790421364637736

2026-03-12T23:06:06.788+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - They are the Tiny Tapeout FPGA Emulation boards
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message-1481790491237285969

2026-03-12T23:06:23.447+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - Basically has the same FPGA as the Fomu and lets you pretend to an a Tiny Tapeout ASIC
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message-1481790578172756035

2026-03-12T23:06:44.174+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - I have an AI working on generating you some test designs like your arty loopback thing
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message-1481790731696738464

2026-03-12T23:07:20.777+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - https://github.com/fpgas-online/fpgas.online-test-designs

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message-1482248399586590810

2026-03-14T05:25:57.305+00:00 β€” carlfk

Reply/reference

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Content

Ill get one of the board on ps1s setup in ... 12ish hours
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message-1482496271821308025

2026-03-14T21:50:54.651+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - No hurry, I have 4 of those boards in the one here at welland
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message-1482496681856602132

2026-03-14T21:52:32.411+00:00 β€” carlfk

Reply/reference

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good.  hook one up to a pi and get a script running on the pi,  which will likely need some things installed like vu
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message-1482496750206845153

2026-03-14T21:52:48.707+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Yeap!
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message-1482496826522210364

2026-03-14T21:53:06.902+00:00 β€” carlfk

Content

you can install a few things into ramdisk - but that gets anoying after a bit
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message-1482496855689662575

2026-03-14T21:53:13.856+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - At some point we should chat about how we want to proceed with the current pici repo.
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message-1482496999688507653

2026-03-14T21:53:48.188+00:00 β€” carlfk

Content

yup - I think I opened an issue about how to .. um.. spemthing about the TT boards
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message-1482497127291818178

2026-03-14T21:54:18.611+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

https://github.com/fpgas-online/todo/issues

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message-1482497257050996808

2026-03-14T21:54:49.548+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - BTW I discovered this thing call "lldp" which is basically a protocol switches use to tell each other what ports they are connected to
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message-1482497369953144895

2026-03-14T21:55:16.466+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - If you install it on the rpi's the switch will then get information about which rpi is connected to which physical port.
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message-1482498180787470417

2026-03-14T21:58:29.784+00:00 β€” carlfk

Content

if I run it on the pi, will it report what port it is hooked to?
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message-1482498401902788710

2026-03-14T21:59:22.502+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - Actually yes, it goes both directions
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message-1482498513920331908

2026-03-14T21:59:49.209+00:00 β€” carlfk

Content

neat
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message-1482500081830727784

2026-03-14T22:06:03.028+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - BTW Did the Acorn + compute boards ever get deployed?
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message-1482507303482560673

2026-03-14T22:34:44.804+00:00 β€” carlfk

Reply/reference

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were those the 4 things in a 1U box?
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message-1482510061031915630

2026-03-14T22:45:42.255+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Yeah
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message-1482510162106519653

2026-03-14T22:46:06.353+00:00 β€” carlfk

Content

yes.  they are hooked to the same PoE swtich at the pi/arty
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message-1482510319497646090

2026-03-14T22:46:43.878+00:00 β€” carlfk

Content

not sure what ports.  might be a way to figure it out looking at the switch's UI
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message-1482545927704150149

2026-03-15T01:08:13.536+00:00 β€” beardothaweirdo (@wspitts2)

Content

If you guys are still having trouble with openocd running on RPI we got it working to our jtag taps (which are standard) as well as to ibex and I can share the instructions for our pi zero wireless ones.
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message-1482546387207065690

2026-03-15T01:10:03.09+00:00 β€” beardothaweirdo (@wspitts2)

Content

We also extended openocd to handle daisy chained JTAG taps. I have to look back at our notes from last year.
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message-1482549066335256618

2026-03-15T01:20:41.844+00:00 β€” beardothaweirdo (@wspitts2)

Content

This allows you to connect any number of JTAG taps together in the design. The openocd driver as it sat last year didn't allow this (at least as we had tried) but the JTAG standard does. It is nice when you have a multimodule hardware design with multiple design specific taps and want to put some in bypass and interrogate the isolated one.
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message-1483661936699641908

2026-03-18T03:02:50.815+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I've been trying to get the AI to document the hardware connectivity and such for the devices @ https://github.com/fpgas-online/fpgas.online-test-designs/tree/main/docs/hardware

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message-1483703196085129288

2026-03-18T05:46:47.819+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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We are mainly using openfpgaloader and I have Claude working on adding support for rp1-pio accelerated programming. It already works using the libgpio driver but is rather slow - https://github.com/fpgas-online/fpgas.online-test-designs/blob/main/docs/hardware/netv2.md#jtag-via-rpi-gpio

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message-1491279049400516690

2026-04-08T03:30:32.002+00:00 β€” carlfk

Content

Im still in disbelief that this works to install packages into the pi: videoteam@val2:~$ sudo chroot /srv/nfs/rpi/trixie/root apt install libcamera-tools
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message-1491279294767300750

2026-04-08T03:31:30.502+00:00 β€” carlfk

Content

val2 is x86, I can't just run arm code.  it's not right.
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message-1491420580304523348

2026-04-08T12:52:55.599+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - https://github.com/fpgas-online/rpi-qemu

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message-1491512904242036807

2026-04-08T18:59:47.341+00:00 β€” carlfk

Content

Temperature monitoring ?!   we are back into the supernatural :p
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message-1491599632621506660

2026-04-09T00:44:24.998+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - I think I'm close to having the CI system able to build the tftp/nfsroot server and verify a virtual pi is able to tftp boot and run from the nfs mount.
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message-1491600187578257449

2026-04-09T00:46:37.31+00:00 β€” carlfk

Content

what is the test for "did the pi boot" ?
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message-1491600808624656434

2026-04-09T00:49:05.379+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - That is what the rpi-qemu work above was for. It builds the x86 system in QEMU and then connects the virtual QEMU RPi to the x86 network and verifies that the RPi PXEboots, mounts the nfsroot and then starts the fpgas.online stuff.
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message-1491601208962580570

2026-04-09T00:50:40.827+00:00 β€” carlfk

Content

I understand what it does.  I am curious how you implemented "verifies"
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message-1492585562501152850

2026-04-11T18:02:08.999+00:00 β€” carlfk

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looooook!!! https://www.reddit.com/r/FPGA/comments/1shbhyv/free_access_to_fpgas/

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message-1492716172968329396

2026-04-12T02:41:08.961+00:00 β€” Essen (@essen__)

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You are famous now πŸ’ͺ
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message-1492716343630233731

2026-04-12T02:41:49.65+00:00 β€” carlfk

Content

so much fame
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message-1492716579165704343

2026-04-12T02:42:45.806+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - My last name has two ls πŸ™‚
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message-1492716645775442040

2026-04-12T02:43:01.687+00:00 β€” carlfk

Content

I edit
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message-1492734896219881522

2026-04-12T03:55:32.932+00:00 β€” Essen (@essen__)

Content

Backstage if you guys are interested. Overwhelmingly positive:

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message-1493433879514583090

2026-04-14T02:13:03.536+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

@carlfk - In theory I now have running in GitHub Actions the Ansible scripts building the x86 host machine with nfsroot and such and then testing that a RPi is able to PXEboot and nfsmount+overlayfs from that host machine. https://github.com/fpgas-online/fpgas.online-infra

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message-1493434422693859368

2026-04-14T02:15:13.04+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Content

Claude and myself came up with the following kind of interesting approach:
> The server uses systemd-nspawn with qemu-user-static ARM syscall emulation to create a chroot environment from the Pi NFS root, runs sshd inside it, and Ansible connects via SSH as if it were a real Pi. This ensures all packages, services, and configuration are pre-installed before any Pi boots.

Kinda like the chroot approach you were playing with but works more naturally with ansible.
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message-1493445011860361408

2026-04-14T02:57:17.694+00:00 β€” Tim 'mithro' Ansell (@mithro_)

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@carlfk - Another group kind of interested in the fpgas.online stuff https://github.com/chili-chips-ba/openCologne-PCIE/issues/1#issuecomment-4240999492

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message-1499324365370560622

2026-04-30T08:19:44.804+00:00 β€” carlfk

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post looks ilke it is getting some traction - I hink there are 10+"likes" great.
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message-1499324497935863941

2026-04-30T08:20:16.41+00:00 β€” carlfk

Content

except comment # 2 says  Guys, did you know that Claude ✴️, Anthropic #ai coding agent, was extensively used to create the fpga.online code base‼️   https://www.linkedin.com/feed/update/urn:li:activity:7449678757650518016/?dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287455437480092393472%2Curn%3Ali%3Aactivity%3A7449678757650518016%29

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message-1516472340987514880

2026-06-16T15:59:40.785+00:00 β€” Hoffmann (@georgehoffmann428)

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message-1522364674471886990

2026-07-02T22:13:42.562+00:00 β€” cartertu160rner

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