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#🖱️-usb

23 Discord messages from 📐 - Designing/usb/channel.md.

Category: 📐 - Designing Channel ID: 1508725695805919245

Messages: 23

message-1508725866614624286

2026-05-26T06:57:57.372+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Greg - could you explain more about your USB stuff with Luna here?
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message-1508726004456226888

2026-05-26T06:58:30.236+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@tnt - I have already forgotten the state of your USB core on gf180mcu
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message-1508726627620622336

2026-05-26T07:00:58.81+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Lofty - Have you had a chance to test your UTMI (or was it ULPI) interface yet?
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message-1508726714560286740

2026-05-26T07:01:19.538+00:00 — Lofty (@ravenslofty)

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Content

not yet (it was ULPI)
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message-1508732973971931276

2026-05-26T07:26:11.898+00:00 — RebelMike (@rebelmike)

Content

There’s https://tinytapeout.com/chips/ttgf0p2/tt_um_urish_usb_cdc on the run 1 Tiny Tapeout. I might grab that for the next TinyQV

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message-1508752818494767215

2026-05-26T08:45:03.201+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@urish - I think you showed that your USB-CDC design was working on the GF180MCU shuttle?
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message-1508754073149771806

2026-05-26T08:50:02.334+00:00 — tnt (@246tnt)

Content

I tested it. Although it's based off the tinyfpga code, so not sure exactly how "spec compliant" it is, I never ran test suites on it to validate behavior in the various edge cases.
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message-1508755866323652738

2026-05-26T08:57:09.86+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Greg has been getting some stuff going @ https://github.com/gregdavill/tinyfpga-boot/actions

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message-1508756404817756190

2026-05-26T08:59:18.247+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Attachments

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message-1508759051725705216

2026-05-26T09:09:49.319+00:00 — namibj

Content

Hmmm, I should get started pre-layout-SPICE plus then drawing the MCML cells (of proportions approximately matching what the simulations suggest to be ideal) for what I had planned to get into my ttsky26a tile (an MCML partial positive feedback 2-delay-cell VCO (no inductor) plus between a mere PA to launch the clock directly and a an actual serializer launching a PRBS-31 stream to allow estimating/prediction/measuring what TX equalizer parameters would be needed).

I do for now at least still have hope to squeeze a (if it had TX equalization done, at least) USB 3.0 SS (the 5Gbit/s stuff) compliant signal out of it on W.S.
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message-1508759294579835033

2026-05-26T09:10:47.22+00:00 — namibj

Content

I'm assuming we'd expect Run2 chips to hit testbenches at least a week before the GDS deadline for Run3?
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message-1508771012341399663

2026-05-26T09:57:20.952+00:00 — Lofty (@ravenslofty)

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Content

Um, did you mean to post this in #🖱️-usb
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message-1508774056738947103

2026-05-26T10:09:26.793+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

He did say "hope to squeeze a USB 3.0 Super Speed compliant signal out of it on wafer.space"
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message-1508774148552523886

2026-05-26T10:09:48.683+00:00 — Tim 'mithro' Ansell (@mithro_)

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I have yet to plan things that far ahead 😛
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message-1508781706151198790

2026-05-26T10:39:50.555+00:00 — Greg (@greg.hashtag.9468)

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Content

I probably need to rename this at some point. Since with the luna backend it's supporting FS/HS(ULPI), and already builds for ECP5 and iCE40 targets. not just the tinyfpga bx.
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message-1508790644817268826

2026-05-26T11:15:21.699+00:00 — namibj

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Content

USB 3.0 5 Gbit/s SS, PCIe 2.0, and 5GBASE-KR (which is just a 10 Gbit/s SFP+ port's PHY but for backplane (think: where PCIe would have been a normal/expected sight) which is then called 10GBASE-KR, just clocked at half with adjusted error counter thresholds/timeouts) are the 5GBaud high speed standards I hope to be feasible on gf180mcuD with at least "usable" (if not spec-compliant) link margin, to connect to modern computers.

I'd expect PCIe to be the hardest to pull off (it's quite complicated), 5GBASE-KR to suffer from relatively expensive switch ports to get one's that'll do that speed (most only do 1G/10G[/25G]) but possibly lowest-overhead and lowest required buffer size (SRAM space usage!), and SS to be at most risk of sad trade-offs between SRAM allocation and feasible goodput.

With luck and prayers at least TX for 10GBASE-KR should be possible though and would allow cheap exfiltration of bulk data from a W.S die.
We'd know more after my SPICE trials that are looking for feasible frequency performance of the core buffer cell (needed for VCO and clock tree) and especially after that has hit layout (w/ PEX, to do post-layout SPICE of at least a VCO core and it's clock extraction/take-off clock tree buffers.
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message-1508790988716376104

2026-05-26T11:16:43.691+00:00 — namibj

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Oh I thought you at least would have an expectation and probably a "yes, per current expectations, ofc conditional on Run3 even happening".
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message-1508791025274196039

2026-05-26T11:16:52.407+00:00 — Lofty (@ravenslofty)

Content

I feel these might be possible on gf180bcd; gf180mcuD might be a stretch
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message-1508824197223288993

2026-05-26T13:28:41.216+00:00 — Tim 'mithro' Ansell (@mithro_)

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I think my goal is something like atleast 6-8 weeks between people getting back silicon and the next run closing

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message-1508824310910025818

2026-05-26T13:29:08.321+00:00 — Tim 'mithro' Ansell (@mithro_)

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Possibly! But I'm not going to stop people from trying 🙂
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message-1532878550892286062

2026-07-31T22:32:06.039+00:00 — rahulbhagwat

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is gf180bcd a bicmos pdk? (looks like it's proprietary, plans of open sourcing from gf?)
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message-1532879175764021409

2026-07-31T22:34:35.02+00:00 — Lofty (@ravenslofty)

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**b**ipolar-**c**mos-**d**mos

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message-1532880998176522341

2026-07-31T22:41:49.517+00:00 — namibj

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Further work has since shown that 10GBASE-R probably works on gf180mcuD; TX is basically just missing drawing up the actual clock tree, sizing the output multiplexer and output PA drivers, and figuring out the correct working phasing of the datapath from the 1.25GBit/s latches through the last MUX2 into the 2.5 GBit/s latches and then the output multiplexer itself.

Nothing major though.
I just didn't get to finish/polish/tune those parts in time for the Run2 deadline.

It's currently getting ported to IHP SG13cmos5L but will be back to gf180mcuD on, by current estimates, Run4 silicon.

My Run3 contributions will be for muxed e-test and maybe a couple isolated critical blocks that'll be needed for making a great transceiver on Run4 (verifying/adjusting models/quantifying oscillator noise to correctly set PLL bandwidths/etc.).
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