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Thread: Yosys Issue

41 Discord messages from 📐 - Designing/📝-project-template/threads/yosys-issue.md.

Category: 📐 - Designing Parent channel: #📝-project-template Thread ID: 1509285266941153461

Messages: 41

message-1509289387740102656

2026-05-27T20:17:11.278+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1509289394022907985

2026-05-27T20:17:12.776+00:00 — Leo Moser (mole99) (@mole99)

Content

Dang, this really is an issue in Yosys then. After updating Yosys to 0.64 I saw similar issues in the LibreLane CI: https://github.com/librelane/librelane/pull/916
I dismissed them for now and didn't merge, hoping that the recent 0.65 release would rectify things, but it doesn't.
If you are able to create a Yosys-only reproducible, you could submit an issue upstream. If not, I'll try to create one tomorrow or simply explain the issue, perhaps someone has an idea what's going on.

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message-1509289463325393097

2026-05-27T20:17:29.299+00:00 — Leo Moser (mole99) (@mole99)

Content

Changed the channel name: Yosys Issue
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message-1509289649556815902

2026-05-27T20:18:13.7+00:00 — RebelMike (@rebelmike)

Content

The yosys version that the build is using is 0.64:
` Yosys 0.64 (git sha1 d8dab5b32666564eca8e18f412973853ce006e61, clang++ 21.1.2 -fPIC -O3)`
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message-1509289819627458770

2026-05-27T20:18:54.248+00:00 — RebelMike (@rebelmike)

Content

Or did you try it with 0.65 and that didn't fix it?
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message-1509290410231726211

2026-05-27T20:21:15.059+00:00 — Leo Moser (mole99) (@mole99)

Content

I tried 0.65 with the LibreLane CI: https://github.com/fossi-foundation/nix-eda/pull/69

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message-1509290757213786264

2026-05-27T20:22:37.786+00:00 — Leo Moser (mole99) (@mole99)

Content

I could also update the wafer.space branch to nix-eda with Yosys 0.65, but it probably wouldn't help :)
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message-1509291252615745566

2026-05-27T20:24:35.899+00:00 — RebelMike (@rebelmike)

Content

Fair enough, I guess we need to roll back to 0.63 until it is fixed, and work out how to report the issue.

In config.yaml if I set the DESIGN_NAME to `uart_tx` and remove chip_top and chip_core I still get the issue, so that is getting towards a small repro.  But I'm not quite sure how to then wrap that up into something I can report to yosys
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message-1509292793108103301

2026-05-27T20:30:43.181+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, I'll try overriding the Yosys version with 0.63 in the project template for now.
I think LibreLane should be able to create a standalone reproducible, as it does for OpenROAD. Maybe pyosys complicates things, but we'll see.
The easiest way would be to write a small Yosys script that reads the Verilog and reproduces the issue, but I'm not sure it will be that easy :)
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message-1509293198332399776

2026-05-27T20:32:19.794+00:00 — Leo Moser (mole99) (@mole99)

Content

In any case, thanks Mike, for giving this a try and identifying the issue!
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message-1509293715666243635

2026-05-27T20:34:23.136+00:00 — RebelMike (@rebelmike)

Content

Ah - this may not be so hard to repro 😄
```
yosys> read_verilog src/uart_tx.v

1. Executing Verilog-2005 frontend: src/uart_tx.v
Parsing Verilog input from `src/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

yosys> check

2. Executing CHECK pass (checking for obvious problems).
Checking module uart_tx...
Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.tx_en is used but has no driver.
Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [3] is used but has no driver.
Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [2] is used but has no driver.
Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [1] is used but has no driver.
Warning: Wire uart_tx.\next_fsm_state$func$src/uart_tx.v:128$1.$result [0] is used but has no driver.
Found and reported 5 problems.
```

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message-1509294825428484156

2026-05-27T20:38:47.724+00:00 — RebelMike (@rebelmike)

Content

I'll raise a yosys issue
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message-1509295197442277557

2026-05-27T20:40:16.419+00:00 — Leo Moser (mole99) (@mole99)

Content

Awesome!
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message-1509297301959475460

2026-05-27T20:48:38.175+00:00 — RebelMike (@rebelmike)

Content

https://github.com/YosysHQ/yosys/issues/5911

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message-1509297980438741064

2026-05-27T20:51:19.937+00:00 — RebelMike (@rebelmike)

Content

I tried to help them isolate by grabbing a couple of OSS CAD suite builds, it was present in a 0.63+ build, but not a 0.62+ (but I think OSS CAD suite might build off the dev branch so possibly the release 0.63 is ok)

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message-1509443993811943535

2026-05-28T06:31:32.238+00:00 — Leo Moser (mole99) (@mole99)

Content

I've pushed an update to the project template that overrides Yosys with version 0.62: https://github.com/wafer-space/gf180mcu-project-template/pull/60/changes/9f23d7e3dad93aba1b9c8d15c748cc486014628a
However, before merging the PR I hope that the issue will be fixed upstream.
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message-1509452380662403112

2026-05-28T07:04:51.819+00:00 — Leo Moser (mole99) (@mole99)

Content

Well, something else fails with this older version. So we might just have to wait for a fix :)

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message-1509633450376691902

2026-05-28T19:04:22.203+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) I see you got CI working on the PR now ?
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message-1509635676939751515

2026-05-28T19:13:13.057+00:00 — Leo Moser (mole99) (@mole99)

Content

Yeah, it was already working before since the template does not trigger the regression in Yosys. When I backported Yosys to 0.62 something else broke, so I dropped that commit and am now waiting on a proper fix.
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message-1509646426374668288

2026-05-28T19:55:55.922+00:00 — RebelMike (@rebelmike)

Content

Yosys 0.63 looks to be working for me - that might be worth a try
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message-1509648805010604143

2026-05-28T20:05:23.033+00:00 — tnt (@246tnt)

Content

@RebelMike Which versions of oss cad did you try  that was 0.63+?
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message-1509649273329811556

2026-05-28T20:07:14.689+00:00 — RebelMike (@rebelmike)

Content

20260331
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message-1509650810873843712

2026-05-28T20:13:21.268+00:00 — RebelMike (@rebelmike)

Content

Ah hah, 20260307 fails
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message-1509651023554154527

2026-05-28T20:14:11.975+00:00 — RebelMike (@rebelmike)

Content

So regression very early in dev after 0.63 release
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message-1509651746761347163

2026-05-28T20:17:04.401+00:00 — tnt (@246tnt)

Content

What's the reported hash ?
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message-1509653004653953175

2026-05-28T20:22:04.306+00:00 — RebelMike (@rebelmike)

Content

Yosys 0.63+87 (git sha1 2f1cdc2df, clang++ 18.1.8 -fPIC -O3)
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message-1509653239975514293

2026-05-28T20:23:00.411+00:00 — tnt (@246tnt)

Content

```
commit e9442194f27140e3e80cb3bf407c3259d562c449
Author: likeamahoney <likeamahoney@gmail.com>
Date:   Fri Feb 27 20:42:40 2026 +0300

    support automatic lifetime qualifier on procedural variables
```
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message-1509653282078064680

2026-05-28T20:23:10.449+00:00 — tnt (@246tnt)

Content

this sounds like a possible culprit ?
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message-1509656323657044159

2026-05-28T20:35:15.618+00:00 — tnt (@246tnt)

Content

```
0.62+119        04113eb95       bad     20260304
0.62+117        1d3f9b790       works   20260302
```

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message-1509663342036258886

2026-05-28T21:03:08.93+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) You coul dtry reverting that
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message-1509676427912544346

2026-05-28T21:55:08.846+00:00 — tnt (@246tnt)

Content

Confirmed. I reverted this on `master` and that fixed the issue.
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message-1509682854135726150

2026-05-28T22:20:40.977+00:00 — RebelMike (@rebelmike)

Content

Thank you!  Hopefully Leo can confirm if reverting that fixes the various other failures that Librelane CI picked up: https://github.com/librelane/librelane/actions/runs/26505823629

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message-1509809349244092446

2026-05-29T06:43:19.761+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks for pinpointing the faulty commit!
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message-1509809672948023427

2026-05-29T06:44:36.938+00:00 — Leo Moser (mole99) (@mole99)

Content

Let's see if this works:

- https://github.com/fossi-foundation/nix-eda/pull/70
- https://github.com/librelane/librelane/pull/916

I also noticed a slight fmax regression as well, so I'll have to adjust the target frequency for some designs. But what can you do...
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message-1509816660658487296

2026-05-29T07:12:22.938+00:00 — tnt (@246tnt)

Content

Not done yet, but looking so far ...
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message-1509836462282117172

2026-05-29T08:31:04.013+00:00 — Leo Moser (mole99) (@mole99)

Content

It seems that does the trick. Had to fix `CLOCK_PERIOD` slightly for two designs. `full_chip_sky130` now has issues which are likely due to a magic update, but I think those are valid issues. Looking into it.
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message-1509839111421296770

2026-05-29T08:41:35.617+00:00 — Leo Moser (mole99) (@mole99)

Content

If this runs through I can properly rebase everything and finally update nix-eda in LibreLane again.

https://github.com/librelane/librelane/pull/916/changes/d867039ca70d301a784f5b65e206076372d635b0
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message-1509839927616082053

2026-05-29T08:44:50.213+00:00 — Leo Moser (mole99) (@mole99)

Content

The issue with `full_chip_sky130` was in the power ports. The sky130 pads have a separate port for the bondpad. But LibreLane would short all of the global connections for it. Until now I somehow managed to convince magic to short them during extraction as well. Not sure if this was actually buggy behavior or not? With a recent magic update this does not work anymore, so I've properly implemented power/ground busses in LibreLane.
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message-1509840044213534750

2026-05-29T08:45:18.012+00:00 — Leo Moser (mole99) (@mole99)

Content

Attachments

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message-1509840109825032273

2026-05-29T08:45:33.655+00:00 — Leo Moser (mole99) (@mole99)

Content

LVS now looks like this. Instead of a single `VCCD_PAD` there is now `VCCD_PAD[0]` and `VCCD_PAD[1]`, as it should be.
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message-1509880409511432323

2026-05-29T11:25:41.849+00:00 — Leo Moser (mole99) (@mole99)

Content

Merged, and I've updated the template: https://github.com/wafer-space/gf180mcu-project-template/pull/60
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