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Thread: Template update

10 Discord messages from πŸ“ - Designing/πŸ“-project-template/threads/template-update.md.

Category: πŸ“ - Designing Parent channel: #πŸ“-project-template Thread ID: 1526579676183662662

Messages: 10

message-1526579929158914048

2026-07-14T13:23:37.595+00:00 β€” RebelMike (@rebelmike)

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message-1526579932665217205

2026-07-14T13:23:38.431+00:00 β€” RebelMike (@rebelmike)

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Awesome, thanks Leo - that makes the update nice and easy to apply πŸ™‚

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message-1526589640209993789

2026-07-14T14:02:12.89+00:00 β€” namibj

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Notably, the `buf_8` (and the identical in all ways that matter, `clkbuf_8`) had a gate finger (spanning both pmos and nmos) in place of what probably should have been a diffusion break; result was that the 3 active fingers on the input (depends on if high or low; the cell is electrically symmetric between nmos and pmos) fed a diode-connected finger of the 8 output fingers (they all share the same gate) and e.g. on input low resulted in about 2.7V (TT default temperature) across an nmos finger with a little over 300ΞΌA through that finger; a side effect should be that the actual output fingers don't properly turn their complement (in that condition, the pmos fingers) off at least on some PVT corners, which causes further but probably overall less significant power dissipation.

TL;DR: an accidentally placed gate in `buf_8` and `clkbuf_8` caused 1 mW static power consumption (and possibly somewhat impaired output logic levels, I'd particularly worry about reduced output-high levels).

Many chips would probably just "melt" from the power wastage.
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message-1526642411508334695

2026-07-14T17:31:54.548+00:00 β€” Tim Edwards (@rtimothyedwards_19428)

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Fortunately on my SRAM test chip I went for a `buf_12`.  But I expect that my original SoC design on Run 1 is toast (or is a toaster).

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message-1526655254215524474

2026-07-14T18:22:56.488+00:00 β€” namibj

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I'll try to simulate the old broken buffer behavior on very low supply voltage around next week or thereabouts; there's a chance it's operable at least if you don't have any deliberate power gating transistors in your design that would rely on sufficiently strong gate drive for sufficiently tame voltage drop.
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message-1527051476789235983

2026-07-15T20:37:23.311+00:00 β€” Tim Edwards (@rtimothyedwards_19428)

Content

Well, I did a count of the `buff_8` on `gf180mcu_ocd_openframe` (my PicoRV32 test chip with all 3.3V components) and it uses `buff_8` 2,498 times, so that is potentially a lot of current.
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message-1527052739455094784

2026-07-15T20:42:24.354+00:00 β€” Tim Edwards (@rtimothyedwards_19428)

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I assume that the buffer is _functional_ or else `lctime` would have produced garbage output in the .lib file for it.  The amount of current is going to be the issue.  I estimate somewhere between a half an amp and an amp total.
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message-1527055896084086945

2026-07-15T20:54:56.953+00:00 β€” namibj

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It does _buffer,_ on tt 3v3 default spice temperature it has an output high of like 2.71 V.
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message-1527056573116190860

2026-07-15T20:57:38.37+00:00 β€” namibj

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The pertinent question will be how the STA holds up as you drop voltage and clock.
Does it reach a point where it won't try to melt the die (2.5W is "manageable") and still doesn't experience hold violations?
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message-1527056905665515611

2026-07-15T20:58:57.656+00:00 β€” namibj

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(I'm thinking that maybe at like 1.2V or something the static power stops needing a heatsink and the chip can run at still like 1% nominal clock speed or such.)
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