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Thread: pure digital, no hard macros, no SRAM

88 Discord messages from 📐 - Designing/📝-project-template/threads/pure-digital-no-hard-macros-no-sram.md.

Category: 📐 - Designing Parent channel: #📝-project-template Thread ID: 1445210755434549288

Messages: 88

message-1445211099262746694

2025-12-02T00:32:56.788+00:00 — bailey (@bailey8889)

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message-1445211103092150292

2025-12-02T00:32:57.701+00:00 — bailey (@bailey8889)

Content

Ok, so it's just a big design then. Can you tell which rule it's stuck on by looking at the current log file?
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message-1445211200714706994

2025-12-02T00:33:20.976+00:00 — Lofty (@ravenslofty)

Content

```
2025-12-01 13:25:53 +0000: Memory Usage (1206676K) : Starting deriving base layers.
2025-12-01 13:28:27 +0000: Memory Usage (2314588K) : Construct connectivity for the design.
2025-12-01 13:28:28 +0000: Memory Usage (2314588K) : Connectivity rules enabled, Netlist object will be generated.
Chip' - Stage 68 - Design Rule Check (KLayout) ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━╸━━━━━ 67/77 11:58:20
```
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message-1445211282889379991

2025-12-02T00:33:40.568+00:00 — bailey (@bailey8889)

Content

Is it thrashing? How's your memory usage?
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message-1445211343023112315

2025-12-02T00:33:54.905+00:00 — Lofty (@ravenslofty)

Content

57.1 GiB free memory
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message-1445211386794737755

2025-12-02T00:34:05.341+00:00 — Lofty (@ravenslofty)

Content

4.17GiB used by klayout
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message-1445211529392689173

2025-12-02T00:34:39.339+00:00 — Lofty (@ravenslofty)

Content

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message-1445212932463136949

2025-12-02T00:40:13.857+00:00 — bailey (@bailey8889)

Content

If you do a
```
find openlane/<block>/runs/<timestamp>
```
you should see a lot of files generated at each step. If you look in the directory for klayout-drc (not sure of the name), there should be a real time log showing how much time was spent on each rule. Depending on the output buffering, you may be able to tell which rule is currently being checked.
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message-1445213295484338198

2025-12-02T00:41:40.408+00:00 — Lofty (@ravenslofty)

Content

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message-1445225188353511547

2025-12-02T01:28:55.889+00:00 — bailey (@bailey8889)

Content

@Lofty So that looks like it's been running for about 2 min. Maybe the step after that is where it's stuck. Might be helpful to look at the log after it completes.

Is there a openlane configuration variable to do `deep` vs `flat` drc? All the configuration variables (including defaults) are in the `openlane/<block>/runs/<timestamp>/resolved.json` file.
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message-1445225425260384368

2025-12-02T01:29:52.372+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

(I killed the run, because I didn't have any reason to believe it would complete after another twelve hours of runtime)
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message-1445225659298222130

2025-12-02T01:30:48.171+00:00 — bailey (@bailey8889)

Content

@Lofty do you have any old runs still around in a different timestamp directory that completed?
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message-1445225776369897566

2025-12-02T01:31:16.083+00:00 — Lofty (@ravenslofty)

Content

not anymore, no
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message-1445225989725491371

2025-12-02T01:32:06.951+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

also, I should maybe point out the timezone there. it wasn't running for 2 minutes.
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message-1445228043474833438

2025-12-02T01:40:16.603+00:00 — bailey (@bailey8889)

Content

@Lofty Not sure what you mean about timezone.
Start time `2025-12-01 13:24:36`
Last enty `2025-12-01 13:25:41`
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message-1445228137003745290

2025-12-02T01:40:38.902+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

yes, and it is currently `2025-12-02 01:40`

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message-1445228682045292667

2025-12-02T01:42:48.85+00:00 — bailey (@bailey8889)

Content

Ok, either the last few log entries were buffered or it prints after completion and it was stuck somewhere. Probably need a complete log to know for sure.
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message-1445228740731994153

2025-12-02T01:43:02.842+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

that *was* the complete log
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message-1445229151110824058

2025-12-02T01:44:40.684+00:00 — bailey (@bailey8889)

Content

Sorry, I mean a log file after klayout-drc has completely finished.
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message-1445229607719534605

2025-12-02T01:46:29.548+00:00 — Lofty (@ravenslofty)

Content

like, even in stdout there were no rules mentioned; I genuinely don't think it made it far enough to get stuck on a rule
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message-1445232280619454464

2025-12-02T01:57:06.817+00:00 — bailey (@bailey8889)

Content

You may be correct. I have seen log files that are piped or tee'd get buffered though.
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message-1445307123230576700

2025-12-02T06:54:30.686+00:00 — Trevor Peyton (@trev5514)

Content

Are you on macOS? I've been running into the same issue
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message-1445367658429026387

2025-12-02T10:55:03.402+00:00 — Lofty (@ravenslofty)

Reply/reference

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WSL
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message-1445368028425621586

2025-12-02T10:56:31.616+00:00 — Lofty (@ravenslofty)

Content

well, I re-ran the flow overnight, and...it's stuck on klayout again
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message-1445382005184528446

2025-12-02T11:52:03.935+00:00 — Leo Moser (mole99) (@mole99)

Content

@Lofty Did you came this far?
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message-1445382016601292893

2025-12-02T11:52:06.657+00:00 — Leo Moser (mole99) (@mole99)

Content

Attachments

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message-1445382040114692096

2025-12-02T11:52:12.263+00:00 — Lofty (@ravenslofty)

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yes.
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message-1445382056451375196

2025-12-02T11:52:16.158+00:00 — Lofty (@ravenslofty)

Content

and then it hangs.
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message-1445382099363172433

2025-12-02T11:52:26.389+00:00 — Leo Moser (mole99) (@mole99)

Content

Alright, let's wait for a while.
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message-1445397439170215946

2025-12-02T12:53:23.684+00:00 — Lofty (@ravenslofty)

Reply/reference

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It's been an hour. Any luck?
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message-1445397966063009873

2025-12-02T12:55:29.305+00:00 — Leo Moser (mole99) (@mole99)

Content

It's still generating the netlist object. For KianV this took 1-2h iirc. Since your design is all combinatorial I would assume it to take even longer.
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message-1445398457929171079

2025-12-02T12:57:26.575+00:00 — Leo Moser (mole99) (@mole99)

Content

However, you can try something else on your end: Go to `gf180mcu/gf180mcuD/libs.tech/librelane` and open `config.tcl`.
Set `conn_drc` to false: `dict set ::env(KLAYOUT_DRC_OPTIONS) conn_drc false`
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message-1445398872594579530

2025-12-02T12:59:05.439+00:00 — Leo Moser (mole99) (@mole99)

Content

This will skip generating the netlist object. But this also means KLayout needs to consider the worst case for connectivity rules. Still, worth a try.
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message-1445404041646440489

2025-12-02T13:19:37.837+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

okay, we have rules being executed now; this is great

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message-1445443840277221468

2025-12-02T15:57:46.57+00:00 — Trevor Peyton (@trev5514)

Reply/reference

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Content

FYI mine took 8+ hours and it didn't change from that step... I'll try that option
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message-1445444036340224080

2025-12-02T15:58:33.315+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

You can try disabling `conn_drc` as well. But then you might get false positive DRC errors.
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message-1445444041205485588

2025-12-02T15:58:34.475+00:00 — Lofty (@ravenslofty)

Content

```
[15:53:43] VERBOSE  Running 'Checker.KLayoutDRC' at 'librelane/runs/RUN_2025-12-02_01-03-17/65-checker-klayoutdrc'…                                                  step.py:1138
[15:53:43] ERROR    16 KLayout DRC errors found. - deferred                                                                                                        checker.py:124
```
urgh
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message-1445444091755233422

2025-12-02T15:58:46.527+00:00 — Leo Moser (mole99) (@mole99)

Content

Nice, we can work with that.
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message-1445444422648070226

2025-12-02T16:00:05.418+00:00 — Lofty (@ravenslofty)

Content

um, they seem to all be `NW.2b_MV` violations?
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message-1445445126674710638

2025-12-02T16:02:53.271+00:00 — Lofty (@ravenslofty)

Content

"Min. Nwell Space (Outside DNWELL) [Different potential]"
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message-1445445368807690380

2025-12-02T16:03:51+00:00 — Leo Moser (mole99) (@mole99)

Content

As expected, since Klayout does not have any connectivity information it needs to assume the worse.
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message-1445445532515565728

2025-12-02T16:04:30.031+00:00 — Leo Moser (mole99) (@mole99)

Content

Can you open the violations in the KLayout Marker Browser and send me a screenshot where they are located?
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message-1445446307790458942

2025-12-02T16:07:34.871+00:00 — Lofty (@ravenslofty)

Content

um, where's the marker database file to open?
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message-1445446715619545128

2025-12-02T16:09:12.105+00:00 — Lofty (@ravenslofty)

Content

I think I found it, but it's giving me stuff like this
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message-1445446719549472898

2025-12-02T16:09:13.042+00:00 — Lofty (@ravenslofty)

Content

https://fieldprogrammable.gay/files/5fa95bf6-ce10-487c-ac4b-327d6a770f3a.png

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message-1445447222899769474

2025-12-02T16:11:13.05+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

^
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message-1445450481873846383

2025-12-02T16:24:10.05+00:00 — Leo Moser (mole99) (@mole99)

Content

Is this with just the Nwell layer enabled?
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message-1445452178645848065

2025-12-02T16:30:54.592+00:00 — bailey (@bailey8889)

Content

@lofty, turn on only nwel and then set the display levels to 0 - 20 (or hit the `+` key until all the cell frames disappear)
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message-1445454964959744050

2025-12-02T16:41:58.901+00:00 — Lofty (@ravenslofty)

Content

https://fieldprogrammable.gay/files/1be1a3b6-04d2-4074-a2b8-3acb36408573.png
um, like this?

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message-1445456042921295958

2025-12-02T16:46:15.907+00:00 — Lofty (@ravenslofty)

Content

it seems like the DRC rules are generating pairs of errors for this
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message-1445456088991269028

2025-12-02T16:46:26.891+00:00 — Lofty (@ravenslofty)

Content

so there are only like 8 actual conflicts?
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message-1445456802006438029

2025-12-02T16:49:16.887+00:00 — Lofty (@ravenslofty)

Content

https://fieldprogrammable.gay/files/a664e04a-50dd-4b95-8ba4-4e808309e917.png
https://fieldprogrammable.gay/files/8fe28588-7e40-46bb-a3f7-9886b62a5712.png
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message-1445456908973772880

2025-12-02T16:49:42.39+00:00 — Lofty (@ravenslofty)

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https://fieldprogrammable.gay/files/25dab0b6-a805-45d3-9dce-f6da62b0346f.png
https://fieldprogrammable.gay/files/af3b0b74-f785-4add-8416-b2ea3e45f585.png
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https://fieldprogrammable.gay/files/8c8630f9-3ed3-40a4-9bb0-06d2384e10fa.png

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message-1445457019095093248

2025-12-02T16:50:08.645+00:00 — Lofty (@ravenslofty)

Content

cc @bailey @Leo Moser (mole99)
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message-1445489370319818833

2025-12-02T18:58:41.778+00:00 — Leo Moser (mole99) (@mole99)

Content

@Lofty Sorry, I was afk.

The next step is to make sure all devices use the "Dualgate" layer. These are the thick oxide transistors for 5V/6V. This should be the case anyways if you use the foundry provided I/O cells and standard cells. If so, it means we can actually use rule NW.2a (equi-potential).
Now, just take a measurement between the edges and check that the spacing is >= 0.74um.

I'll do the same before adding your design to the shuttle, but this way you can already be sure these are false positives :)
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message-1445489664541724714

2025-12-02T18:59:51.926+00:00 — Leo Moser (mole99) (@mole99)

Content

FYI KLayout was not stuck, it just took a looong time:
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message-1445489674603856014

2025-12-02T18:59:54.325+00:00 — Leo Moser (mole99) (@mole99)

Content

Attachments

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message-1445489733688889374

2025-12-02T19:00:08.412+00:00 — Leo Moser (mole99) (@mole99)

Content

This will make for a good test case for Matthias.
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message-1445515675992068096

2025-12-02T20:43:13.539+00:00 — Leo Moser (mole99) (@mole99)

Content

Attachments

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message-1445515831701147878

2025-12-02T20:43:50.663+00:00 — Leo Moser (mole99) (@mole99)

Content

Almost 9 hours, but we're done. The magic DRC errors are CO.3 and can be ignored.
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message-1445515912051560478

2025-12-02T20:44:09.82+00:00 — Leo Moser (mole99) (@mole99)

Content

@Lofty Your design is DRC clean 🎉
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message-1445517149664841911

2025-12-02T20:49:04.89+00:00 — Lofty (@ravenslofty)

Reply/reference

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hurray; too bad that GDS has hold violations and I have spent the past several hours building a new GDS >.<
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message-1445518455028580434

2025-12-02T20:54:16.113+00:00 — Lofty (@ravenslofty)

Content

all the same, I don't think I have much to worry about there.
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message-1445519056705945650

2025-12-02T20:56:39.564+00:00 — Lofty (@ravenslofty)

Content

maybe I really do need a CPU upgrade though, if it takes me 12 hours to fail to achieve what you can complete in 9...
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message-1445676865762361394

2025-12-03T07:23:44.175+00:00 — Leo Moser (mole99) (@mole99)

Content

At least you know that there isn't anything special DRC-wise about your design. So the next iteration will very likely also be DRC clean.

I'm using a Ryzen 9 9900X and I'm running it natively on Linux. It may be that the emulation through WSL2 may cause you to lose some performance.
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message-1446539141138354197

2025-12-05T16:30:06.645+00:00 — Lofty (@ravenslofty)

Content

well, now I have very slow antenna checking ^^;
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message-1446539216598208607

2025-12-05T16:30:24.636+00:00 — Lofty (@ravenslofty)

Content

it's stuck on `2025-12-05 15:21:23 +0000: Memory Usage (3550244K) : Executing rule ANT.16_i_ANT.5`
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message-1446540537053315175

2025-12-05T16:35:39.457+00:00 — Leo Moser (mole99) (@mole99)

Content

You can jump to the latest tag of the PDK: https://github.com/wafer-space/gf180mcu/releases/tag/1.4.3
There have been two more changes that should speed up the antenna check, however, don't expect miracles.
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message-1446648364291588237

2025-12-05T23:44:07.474+00:00 — Lofty (@ravenslofty)

Content

now I'm getting what seems to be an LVS failure?
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message-1446648872335310982

2025-12-05T23:46:08.601+00:00 — Lofty (@ravenslofty)

Content

um, @bailey you seem to be the person to talk to about LVS?
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message-1446649184991182989

2025-12-05T23:47:23.144+00:00 — Lofty (@ravenslofty)

Content

```
Circuit 1 contains 137698 devices, Circuit 2 contains 140300 devices. *** MISMATCH ***
Circuit 1 contains 133045 nets,    Circuit 2 contains 138947 nets. *** MISMATCH ***
```
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message-1446649643764154540

2025-12-05T23:49:12.524+00:00 — Lofty (@ravenslofty)

Content

oh. am I running into Magic issues because I have `autoname` on?
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message-1446663023124287549

2025-12-06T00:42:22.412+00:00 — bailey (@bailey8889)

Reply/reference

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@Lofty I have seen errors due to autoname. I've used klayout to manually removed them from the gds without having to rerun.

From the limited information above, I'm guessing that there are unconnected power rails for some standard cell rows. Most probably between or at the edges where there's not enough room to intersect with power rails.

If you share the cell list from the `lvs.report` that precedes the mismatch counts above, I might be able to suggest something else.
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message-1446663477379858473

2025-12-06T00:44:10.715+00:00 — Lofty (@ravenslofty)

Content

Attachments

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message-1446665494374646050

2025-12-06T00:52:11.604+00:00 — bailey (@bailey8889)

Content

@Lofty this one `lvs.netgen.rpt` has more information.
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message-1446665571025293383

2025-12-06T00:52:29.879+00:00 — Lofty (@ravenslofty)

Content

Attachments

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message-1446667345824186402

2025-12-06T00:59:33.024+00:00 — bailey (@bailey8889)

Content

... and how about the `lvs_config.json` file. Looks like the standard cell spice may not be loaded.

Do you know what command is being used to run LVS?
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message-1446667947547299992

2025-12-06T01:01:56.486+00:00 — Lofty (@ravenslofty)

Reply/reference

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um, I don't have a file by that name?
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message-1446668555461459988

2025-12-06T01:04:21.424+00:00 — bailey (@bailey8889)

Content

@Lofty ok. I'm not yet familiar with the wafer.space LVS setup. Is it run as part of precheck or a github action or is there a command to run LVS locally?
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message-1446668642501656707

2025-12-06T01:04:42.176+00:00 — Lofty (@ravenslofty)

Content

it's librelane
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message-1446668852288163901

2025-12-06T01:05:32.193+00:00 — Lofty (@ravenslofty)

Content

<https://github.com/librelane/librelane/blob/main/librelane/scripts/netgen/setup.tcl>
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message-1446669037256970271

2025-12-06T01:06:16.293+00:00 — Lofty (@ravenslofty)

Content

<https://github.com/librelane/librelane/blob/main/librelane/steps/netgen.py#L127>
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message-1446673863537590324

2025-12-06T01:25:26.968+00:00 — bailey (@bailey8889)

Content

@Lofty thanks, that explains a lot.

Looks like the verilog and layout are out of sync. I'm seeing mismatches in standard cell counts that should not happen.
```
gf180mcu_fd_sc_mcu9t5v0__oai21_1 (12908)   |gf180mcu_fd_sc_mcu9t5v0__oai21_1 (13137) *
gf180mcu_fd_sc_mcu9t5v0__mux2_1 (10908)    |gf180mcu_fd_sc_mcu9t5v0__mux2_1 (10942) **
```
The layout is the abstract extracted spice `runs/eco/29-magic-spiceextraction/chip_top.spice`, but unfortunately, I can't find what verilog netlist is being used.

I'll create a PR that records that file in the log file.
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message-1446676015370862733

2025-12-06T01:34:00.005+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

I did eco in some hold buffers, but...they should be in there? Hmm
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message-1446681515844046989

2025-12-06T01:55:51.42+00:00 — bailey (@bailey8889)

Content

Here's the PR with the change. https://github.com/librelane/librelane/pull/831

If you wanted to make the change locally, you could verify whether or not the expected top level verilog netlist is being used.

Embeds

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    "color": "#1E2327",
    "description": "Currently, the top level verilog file name is not displayed in the netgen log.\nHere&amp;#39;s a sample\nReading SPICE netlist file &amp;#39;/home/&amp;lt;user&amp;gt;/gf180mcu-chess/gf180mcu/gf180mc...",
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    "timestamp": null,
    "title": "Display top verilog file name in LVS log. by d-m-bailey · Pull Req...",
    "url": "https://github.com/librelane/librelane/pull/831"
  }
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message-1446759526102597692

2025-12-06T07:05:50.515+00:00 — Lofty (@ravenslofty)

Reply/reference

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Content

```
Circuit 1 contains 140296 devices, Circuit 2 contains 140296 devices.
Circuit 1 contains 138946 nets,    Circuit 2 contains 138946 nets.

Final result:
Circuits match uniquely.
```
the issue is indeed Magic; this is using 8.3.578 which includes the 512-character maximum name length fix

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message-1446759912641400944

2025-12-06T07:07:22.673+00:00 — Lofty (@ravenslofty)

Content

(@Leo Moser (mole99) maybe the flake.nix should be updated?)
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message-1446818125696991245

2025-12-06T10:58:41.747+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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I'm on it!
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