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Thread: @mole99 I just updated my project with

12 Discord messages from 📐 - Designing/📝-project-template/threads/mole99-i-just-updated-my-project-with.md.

Category: 📐 - Designing Parent channel: #📝-project-template Thread ID: 1428383834310705192

Messages: 12

message-1428390851196883035

2025-10-16T14:35:17.144+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1428390857937256604

2025-10-16T14:35:18.751+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, I rebased leo/gf180mcu on top of the latest dev branch. The OpenROAD version, however, is still the same, so I wouldn't expect any changes regarding GPL.
For now, the best way forward with GPL is to set `PL_TIME_DRIVEN: False`.

Could you post your STA error? Even better if you could share your repository with the latest changes. Is it still https://github.com/AvalonSemiconductors/ws-submission-2025?
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message-1428649443766571076

2025-10-17T07:42:50.417+00:00 — Tholin (@tholin)

Content

I updated the repo
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message-1428649935317766225

2025-10-17T07:44:47.612+00:00 — Tholin (@tholin)

Content

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message-1428662706940149780

2025-10-17T08:35:32.604+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks for uploading the changes to your repo. I was able to reproduce the failure and trace it back to my latest changes to the `pdk_compat` code in LibreLane. `pdk_compat` migrates old PDK variables to newer formats, however, for gf180mcu a number of variables were simply overwritten instead of checking whether they already existed. This makes it impossible to update the PDK variables to the newer format.
Therefore, I added some logic that checks whether the new variables already exist before setting their values.

This worked fine, except for `SYNTH_CLK_DRIVING_CELL`, which it is not a new variable, but its format changed. As this variables already existed in the PDK in the old format, it was not set to the new value, which led to the issue you saw.

As the project template uses a custom SDC file, this issue did not appear there.
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message-1428662739991265432

2025-10-17T08:35:40.484+00:00 — Leo Moser (mole99) (@mole99)

Content

I've updated the leo/gf180mcu branch as well as the template project. With the latest changes and this config.yaml I was able to build your project:

```
meta:
  version: 2
  flow: Classic
  substituting_steps:
    KLayout.DRC: null
    Checker.KLayoutDRC: null

# DO CHANGE
DESIGN_NAME: user_project_example
VERILOG_FILES: dir::src/user_project_example.v
CLOCK_PERIOD: 20
DIE_AREA: [0, 0, 250, 250]
RUN_MAGIC_DRC: true
# Valid values are AREA 0-3 and DELAY 0-4
# DELAY 4 = fastest, but largest area
# AREA 3 = slowest, but smallest area
SYNTH_STRATEGY: DELAY 0

# DO NOT CHANGE
RUN_CTS: true
MAX_FANOUT_CONSTRAINT: 4
CLOCK_PORT: clk_i
VDD_NETS: ["VDD"]
GND_NETS: ["VSS"]
VERILOG_POWER_DEFINE: "USE_POWER_PINS"
RT_MAX_LAYER: Metal4
FP_PIN_ORDER_CFG: dir::pin_order.cfg
FP_PDN_MULTILAYER: false
FP_SIZING: absolute
PL_TIME_DRIVEN: False
```
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message-1428662783930663054

2025-10-17T08:35:50.96+00:00 — Leo Moser (mole99) (@mole99)

Content

Note that if you wish to use KLayout DRC in LibreLane, you need the PDK fork of wafer.space, since the changes haven't been upstreamed yet.
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message-1428662850917761035

2025-10-17T08:36:06.931+00:00 — Leo Moser (mole99) (@mole99)

Content

Btw. in your update from upstream you missed:

```
CLOCK_NET: clk_pad/Y
```

in librelane/config.yaml
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message-1428663125845999747

2025-10-17T08:37:12.479+00:00 — Tholin (@tholin)

Content

No, I have it. Did it not end up in the commit?

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message-1428663300664856708

2025-10-17T08:37:54.159+00:00 — Leo Moser (mole99) (@mole99)

Content

All good! I missed it while looking at the diff in GitHub.
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message-1428663668614234162

2025-10-17T08:39:21.885+00:00 — Leo Moser (mole99) (@mole99)

Content

Regarding `SYNTH_STRATEGY`, from the LibreLane docs: "Please note that there is no way to know which strategy is the best before trying them."
So it really depends on the design you implement.
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message-1428666469721444404

2025-10-17T08:50:29.721+00:00 — Tholin (@tholin)

Content

I find DELAY does work to enhance max clock rate greatly, though the difference in DELAY 3 and DELAY 4 is negligible.
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