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Thread: I've setup a new system following the

10 Discord messages from 📐 - Designing/📝-project-template/threads/ive-setup-a-new-system-following-the.md.

Category: 📐 - Designing Parent channel: #📝-project-template Thread ID: 1435507284083216394

Messages: 10

message-1435533621879636008

2025-11-05T07:38:06.381+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1435533626405031936

2025-11-05T07:38:07.46+00:00 — Leo Moser (mole99) (@mole99)

Content

Hi @Greg, the KLayout DRC errors are expected and need to be fixed on our side.

- DPF.4 and DCF.4 relate to dummy fill.
- NW.2b_MV relates to min. nwell spacing and is triggered by some of the I/O and the SRAM. I think this is a faulty rule implementation.
- DF.12 relates to the seal ring. It seems that the rule implementation might be missing a marker layer.

I plan to take a closer look at these issues throughout today.

Cap/slew warnings are not ideal, but can be mostly ignored. They might lead to higher power consumption due to higher crossbar currents. Unfortunately, OpenROAD does not fix all of them. They could be further reduced by ECOs.

The setup violations are due to the design and the selected clock period. The example design (counter) is simply too small for this large of a core area. If your design is larger, OpenROAD will place the standard cells to distribute the wire delays more effectively. You might also need to tweak the target clock period.

I will also soon update the example design to demonstrate how to properly instantiate SRAM macros and get them through the complete flow.
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message-1435543076188979212

2025-11-05T08:15:40.464+00:00 — Greg (@greg.hashtag.9468)

Content

Thanks! that all makes sense, I'll continue to merge my design into this template and track your upstream changes as needed. 👍
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message-1435557561511186472

2025-11-05T09:13:14.034+00:00 — Leo Moser (mole99) (@mole99)

Content

Perfect! Looking forward to more feedback 👍
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message-1435794261885980734

2025-11-06T00:53:47.801+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Greg - Did you have any success?
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message-1435808646096490527

2025-11-06T01:50:57.264+00:00 — Greg (@greg.hashtag.9468)

Content

The flow from the template completed.
Olof has done a new small wrapper since I did the GF180MPW1 serv project, so I'll combine that and the SRAM macro over the weekend.
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message-1435940681246969856

2025-11-06T10:35:36.897+00:00 — Leo Moser (mole99) (@mole99)

Content

@Greg The issues you mentioned are now fixed in the project template. The template has also been updated to include two SRAM macros, so it should be straightforward to add more.

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message-1436311236303257725

2025-11-07T11:08:04.107+00:00 — Greg (@greg.hashtag.9468)

Content

Working for me 👍  Just need a way to get data into the SRAM. A memory mapped SPI would work pretty well I think

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message-1436316844804935871

2025-11-07T11:30:21.278+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, even better with some cache 😉
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message-1436325461503377408

2025-11-07T12:04:35.659+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Greg - Yay! 🙂
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