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Thread: Huh ... I'd like to know about those

37 Discord messages from πŸ“ - Designing/πŸ“-project-template/threads/huh-id-like-to-know-about-those.md.

Category: πŸ“ - Designing Parent channel: #πŸ“-project-template Thread ID: 1509177279438393545

Messages: 37

message-1509178623406637076

2026-05-27T12:57:03.003+00:00 β€” Leo Moser (mole99) (@mole99)

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message-1509178630570381342

2026-05-27T12:57:04.711+00:00 β€” Leo Moser (mole99) (@mole99)

Content

It will mainly be about the logos: besides the QR code, we will also add a readable ID, which will look like this:
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message-1509178646919905300

2026-05-27T12:57:08.609+00:00 β€” Leo Moser (mole99) (@mole99)

Content

Attachments

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message-1509179003498397788

2026-05-27T12:58:33.624+00:00 β€” Leo Moser (mole99) (@mole99)

Content

And for the bonding, it was suggested that the opposite corner should be empty to make it is easier to differentiate. The wafer.space logo will likely be moved in the top left corner. So only the bottom right corner can be used for a user logo.
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message-1509179385071140884

2026-05-27T13:00:04.598+00:00 β€” tnt (@246tnt)

Content

Ok, we have a custom bonding setup anyway ( and the changes discussed in #πŸ“¦-cob would make TT incompatible anyway ) so that shouldn't be an issue.
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message-1509182163172724736

2026-05-27T13:11:06.949+00:00 β€” namibj

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Oh, custom bonding?
Can I read enough on it two weeks from now to make at least an attempt at respecting the package inductance?
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message-1509182712337141970

2026-05-27T13:13:17.88+00:00 β€” tnt (@246tnt)

Content

Huh no ...
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message-1509183074347258089

2026-05-27T13:14:44.19+00:00 β€” tnt (@246tnt)

Content

The wire we use is the same, posted in some of the picture, the PCB we wirebond to is on the TT github ... feel free to run an EM simulation if you fancy it, but that's not something we will do as it's inconsequential to 99.99% of TT users ...
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message-1509184310203252736

2026-05-27T13:19:38.841+00:00 β€” namibj

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That's enough documentation for me then.
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message-1509189849842974790

2026-05-27T13:41:39.594+00:00 β€” tnt (@246tnt)

Content

Because of the COB process that means you have to use our big standard breakout so I'm not sure it'll be suitable for anything "high speed" in any case.  Processes where you can get the QFN ( sky or ihp ) are more suitable.

I'm hoping TT would also offer "bare chip" bonded to a small COB PCB like the W.S one of run.1. but not sure that will happen, that's not my decision.
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message-1509211935940280391

2026-05-27T15:09:25.33+00:00 β€” namibj

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Huh, are you not doing the same mezzanine plug (just different pinout/bonding diagram) as https://discord.com/channels/1361349522684510449/1361349523724570941/1501331867973193728 ?
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message-1509212284562444498

2026-05-27T15:10:48.448+00:00 β€” namibj

Content

(I couldn't find anything that clearly looked like a COB PCB on the TT GitHub that sounded like it applied; the "best" I could find was `cobbler`?)
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message-1509214369941295236

2026-05-27T15:19:05.641+00:00 β€” namibj

Content

I'd assume TT won't put all 1k dies of the `ttgf0p3`on the fancy breakout boards if there's sufficient interest in some going through the W.S COB "packaging" line, but even if not, I don't _think_ extracting an analog pin pair to HF-appropriate and probing-suitable pads/pins would be too much for @azonenberg 's rework skills.
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message-1509214718638686531

2026-05-27T15:20:28.777+00:00 β€” tnt (@246tnt)

Content

https://github.com/htfab/breakout-ttgf0p2-cob/tree/main
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message-1509214867591008328

2026-05-27T15:21:04.29+00:00 β€” tnt (@246tnt)

Content

We wouldn't put 1k dies on it ... just what we deem necessary and just not do anything with the rest.
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message-1509241976669737183

2026-05-27T17:08:47.598+00:00 β€” namibj

Content

Hmmm, if it's JLC04161H-3313, they should be 50Ξ© single-ended/90~95Ξ© differential.
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message-1509243406713360504

2026-05-27T17:14:28.547+00:00 β€” tnt (@246tnt)

Content

@stuart Do we know what the stackup of the PCBs we use for production is ?
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message-1509247921705451671

2026-05-27T17:32:25.005+00:00 β€” namibj

Content

I don't have to know until in those about 14 days from now.
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message-1509251915165335773

2026-05-27T17:48:17.12+00:00 β€” namibj

Content

_after_ I have a functional design filed, and if I have several days left until the deadline, I would work to tune performance with PEX to the reasonably-accessible outside interface. I'd not need anything detailed I couldn't quick-maths from the bonding diagram and the analog mux structure before then.
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message-1509255505858793684

2026-05-27T18:02:33.208+00:00 β€” stuart (@saladchap)

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Which boards/production?
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message-1509255785925050468

2026-05-27T18:03:39.981+00:00 β€” namibj

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ttgf0p3 COB/"package"
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message-1509255960475074602

2026-05-27T18:04:21.597+00:00 β€” namibj

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I don't need to know any sooner than ~14 days from now.
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message-1509260909913047072

2026-05-27T18:24:01.635+00:00 β€” azonenberg

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I have access to a gold ball bonder at work. Old K&S manual unit
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message-1509261017761316894

2026-05-27T18:24:27.348+00:00 β€” azonenberg

Content

if i can get them to OK me using it for a nonbillable project, I can probably rebond a bare die if i had 1-2 old dies on the same process to dial in the settings on
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message-1509261105887838249

2026-05-27T18:24:48.359+00:00 β€” azonenberg

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(like not remove existing bonds, but doing my own COB from a never-bonded die that breaks out to SMA or something)
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message-1509261161210708039

2026-05-27T18:25:01.549+00:00 β€” namibj

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Give me 15 minutes to get home.
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message-1509262419342528573

2026-05-27T18:30:01.511+00:00 β€” stuart (@saladchap)

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We haven't made any PCBs for these, only 0p2 and 0p1
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message-1509264823672635462

2026-05-27T18:39:34.748+00:00 β€” tnt (@246tnt)

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@stuart Well I'm assuming we use the same 4l stackup every time ?
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message-1509266207281385554

2026-05-27T18:45:04.626+00:00 β€” namibj

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I'm hoping those choices happen with a few days to spare until the GDS deadline for me filing the last tile revision, though.

As said though, no rush from me just trying to get a bit of information going and then go offline for the weekend (3 very long days)
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message-1509287508851167332

2026-05-27T20:09:43.316+00:00 β€” Tim 'mithro' Ansell (@mithro_)

Reply/reference

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@Andrew Wingate - FYI
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message-1509288285699313796

2026-05-27T20:12:48.531+00:00 β€” Andrew Wingate (@anfroholic)

Reply/reference

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Cool!
Also sorry, I think I'm missing some context. Are you in the Chicago area @azonenberg?
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message-1509288602272796703

2026-05-27T20:14:04.008+00:00 β€” azonenberg

Content

No, Seattle
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message-1509293316272033914

2026-05-27T20:32:47.913+00:00 β€” stuart (@saladchap)

Content

For TTGF0p1 and TTGF0p2 we used JLCPCB's standard 1.6mm FR-4 4 layer PCBs with ENIG

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message-1509293684804292648

2026-05-27T20:34:15.778+00:00 β€” stuart (@saladchap)

Content

For the Wafer Space panels we used JLCPCB's 4-layer 0.8mm thick PCB with ENIG, though we are also trying some 2-layer panels at the moment

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message-1509295910612635710

2026-05-27T20:43:06.452+00:00 β€” namibj

Reply/reference

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If it doesn't change the shown cost, I'd suggest clicking the "specify stackup" and just keeping the suggested one, that way it's at least known. I think in some cases there may be more than one choice in the "cheap" tier to pick from, though.

But it confirms my assumptions that it's likely that `JLC04161H-3313`. (It's probably the stackup you got without specifying on the 1.6mm 4L's.)

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message-1509297321802993745

2026-05-27T20:48:42.906+00:00 β€” tnt (@246tnt)

Content

@stuart But production boards shipped to users will be made by Sam right ? What stackup do they use ?
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message-1509300412203798578

2026-05-27T21:00:59.715+00:00 β€” stuart (@saladchap)

Reply/reference

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This very much depends on the qtys we're making and what the priority is. For WS the priority (for now and afaiu at least) has been lowest cost.
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