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Thread: How we can do the same here, excluding

15 Discord messages from 📐 - Designing/📝-project-template/threads/how-we-can-do-the-same-here-excluding.md.

Category: 📐 - Designing Parent channel: #📝-project-template Thread ID: 1441095243041865820

Messages: 15

message-1441095961463230474

2025-11-20T16:00:51.481+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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message-1441095965829496933

2025-11-20T16:00:52.522+00:00 — Leo Moser (mole99) (@mole99)

Content

You need to set [`SYNTH_EXCLUDED_CELL_FILE`](https://librelane.readthedocs.io/en/latest/reference/common_pdk_vars.html) to point to your exclude file.
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message-1441096207098318960

2025-11-20T16:01:50.045+00:00 — Leo Moser (mole99) (@mole99)

Content

You can find the current one in `gf180mcu/gf180mcuD/libs.tech/librelane/gf180mcu_fd_sc_mcu7t5v0/synth_exclude.cells`

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message-1441096516973363392

2025-11-20T16:03:03.925+00:00 — asic destroyer (@logic_destroyer)

Content

it is possible to overlay it?
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message-1441096625425612810

2025-11-20T16:03:29.782+00:00 — asic destroyer (@logic_destroyer)

Content

I don't want to touch the gf180mcu repo
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message-1441096694115864706

2025-11-20T16:03:46.159+00:00 — Leo Moser (mole99) (@mole99)

Content

No, unfortunately not. Make a copy of the file in your repository and add the line.

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message-1441097669945589791

2025-11-20T16:07:38.815+00:00 — urish

Content

Yes, that's what I did
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message-1441097736899395726

2025-11-20T16:07:54.778+00:00 — urish

Content

But it'd be really nice to understand the actual issue
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message-1441097789898752164

2025-11-20T16:08:07.414+00:00 — asic destroyer (@logic_destroyer)

Content

But if they are changes in gf180mcu you will not recognize 🙂
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message-1441098018689650728

2025-11-20T16:09:01.962+00:00 — asic destroyer (@logic_destroyer)

Content

Today you know, but not tomorrow 🙂
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message-1441099645307850903

2025-11-20T16:15:29.778+00:00 — Leo Moser (mole99) (@mole99)

Content

Yes, the proper solution is to fix the simulation model of the cell (if that is the issue).
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message-1441100897634750575

2025-11-20T16:20:28.356+00:00 — asic destroyer (@logic_destroyer)

Content

$ cat 06-yosys-synthesis/chip_top.nl.v  | grep gf180mcu_fd_sc_mcu7t5v0__oai21_1 | wc -l
0
lolo
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message-1441109594746388492

2025-11-20T16:55:01.909+00:00 — urish

Reply/reference

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There's a good chance the simulation model is not the issue, since there are many `gf180mcu_fd_sc_mcu7t5v0__oai21_2` instances in the design that does pass the GL tests
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message-1441194124521767074

2025-11-20T22:30:55.378+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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Content

what is the issue then?
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message-1441194555914457129

2025-11-20T22:32:38.23+00:00 — asic destroyer (@logic_destroyer)

Content

yosys?
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