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Thread: CTS error with split voltage IO cells

5 Discord messages from 📐 - Designing/📝-project-template/threads/cts-error-with-split-voltage-io-cells.md.

Category: 📐 - Designing Parent channel: #📝-project-template Thread ID: 1513112664635867288

Messages: 5

message-1513112673695301723

2026-06-07T09:29:33.683+00:00 — RebelMike (@rebelmike)

Content

When trying to use the ocd version of the IO cells, I see this error in CTS:
```
[INFO CTS-0007] Net "clk_PAD2CORE" found for clock "clk_PAD".
[INFO CTS-0122] Clock net "clk_PAD2CORE" is skipped for CTS because it is not connected to any output instance pin or input block terminal.
[WARNING CTS-0083] No clock nets have been found.
[INFO CTS-0008] TritonCTS found 0 clock nets.
[WARNING CTS-0082] No valid clock nets in the design.
```
I've confirmed it happens on the default template too.  There it doesn't cause the build to fail - presumably the tooling can cope without needing a clock tree for a small number of registers, but it's obviously bad, and in a larger design it does cause failures.
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message-1513116323670917251

2026-06-07T09:44:03.905+00:00 — Leo Moser (mole99) (@mole99)

Content

Can confirm, that is not a nice clock tree. (I'm also wondering why I don't see the SPEF delays here.)

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message-1513116488989413526

2026-06-07T09:44:43.32+00:00 — Leo Moser (mole99) (@mole99)

Content

I'll compare the LEF/LIB views of the OCD cells with the foundry ones.
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message-1513119181040779364

2026-06-07T09:55:25.155+00:00 — Leo Moser (mole99) (@mole99)

Content

Found the issue: `PIN Y` in the LEF does not have a direction set, making it `INPUT` by default.

You can edit `libs.ref/gf180mcu_ocd_io/lef/gf180mcu_ocd_io.lef` and add `DIRECTION OUTPUT ;` after line 3432.

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message-1513119322644680815

2026-06-07T09:55:58.916+00:00 — Leo Moser (mole99) (@mole99)

Content

Thanks for the report, Mike! I'll make sure the PDK is updated accordingly.

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