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Thread: 3v3 cell library

6 Discord messages from 📐 - Designing/💻-digital/threads/3v3-cell-library.md.

Category: 📐 - Designing Parent channel: #💻-digital Thread ID: 1509460314155122759

Messages: 6

message-1509460323315355700

2026-05-28T07:36:25.495+00:00 — RebelMike (@rebelmike)

Content

Hi @Tholin, I’m looking to use your cell library in the next run. I was doing an initial port last night and saw there aren’t latch or clock gate cells. This isn’t a show stopper, but especially a latch would be good to have.
Do you have any plans to add them?
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message-1509561262307147828

2026-05-28T14:17:31.226+00:00 — Tholin (@tholin)

Content

There are latch cells in the library, but you have to manually instantiate them as they lack characterization data.
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message-1509561298927747343

2026-05-28T14:17:39.957+00:00 — Tholin (@tholin)

Content

You have to exclude all paths through the latches in STA
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message-1509561369677004820

2026-05-28T14:17:56.825+00:00 — Tholin (@tholin)

Content

You’re on your own for making the timing work
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message-1509638596741566635

2026-05-28T19:24:49.192+00:00 — RebelMike (@rebelmike)

Content

Awesome, thanks - I see them there now.  The way this particular thing is using them timing shouldn't matter.
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message-1513972857619615865

2026-06-09T18:27:37.512+00:00 — RebelMike (@rebelmike)

Content

One thing I've only just spotted on these latches is the output is inverted (at least according to the verilog and the lib, so I assume it really is).
That was surprising to me!
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