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287 Discord messages from 📐 - Designing/digital/channel.md.

Category: 📐 - Designing Channel ID: 1409664140196188251

Messages: 287

message-1427950812977696831

2025-10-15T09:26:43.857+00:00 — carlfk

Content

@Tim 'mithro' Ansell where is your path to open source serdes slides/talk/something
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message-1427966034777866340

2025-10-15T10:27:13.017+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

You mean https://bit.ly/open-pipe-talk ?

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message-1428191794029527072

2025-10-16T01:24:18.217+00:00 — Andrew Wingate (@anfroholic)

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Content

Yeah, this was the one. Is there video of this somewhere?
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message-1428197793494990922

2025-10-16T01:48:08.601+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Sadly, not....

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message-1428369602106359928

2025-10-16T13:10:50.966+00:00 — HardWall (@hardwall)

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Content

That must be the longest power point for a presentation I have seen in my life. :)))
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message-1428511903545823302

2025-10-16T22:36:18.273+00:00 — Andrew Wingate (@anfroholic)

Reply/reference

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Tim is great like this. At his SuperCon talk he said there were 115 slides in his 26min talk.
Keep it up Tim!!

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message-1428511919391637587

2025-10-16T22:36:22.051+00:00 — Andrew Wingate (@anfroholic)

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https://www.youtube.com/watch?v=EHePto95qoE

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message-1428672798892626004

2025-10-17T09:15:38.713+00:00 — Tim 'mithro' Ansell (@mithro_)

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Content

I have https://bit.ly/tim-silicon-2024 which links to some of my other silicon presentations

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message-1433539419972833300

2025-10-30T19:33:51.596+00:00 — Tholin (@tholin)

Content

For some reason, I can’t  run cocotb anymore? Even in projects where it used to work, on two different systems and inside the iic-osic-tools container. Its all broken.
It instantly quits with the message `/bin/sh: line 1: /cmds.f: Permission denied` when trying to build target `/sim.vpp`
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message-1433557331370836150

2025-10-30T20:45:02.006+00:00 — Tholin (@tholin)

Content

Yeah, apparently there was an update and I had to edit all my makefiles.
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message-1433557486908211241

2025-10-30T20:45:39.089+00:00 — Tholin (@tholin)

Content

I get console spam before my tests run, though

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message-1433718258678239396

2025-10-31T07:24:30.066+00:00 — Leo Moser (mole99) (@mole99)

Content

@Tholin You can use the Nix setup in the template which comes with cocotb 2.0.

Yes, that is to be expected given that iverilog does not support that feature. This is only important, however, if you run SDF-backannotated simulations.
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message-1434036786891587655

2025-11-01T04:30:13.11+00:00 — Tholin (@tholin)

Content

So, about the fab SRAM macros: they have their VDD/VSS power straps on the Metal3 layer in the form of horizontal strips. However, the vertical Metal4 strips in chip_top’s power grid will not connect to them. Why?

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message-1434040464729706557

2025-11-01T04:44:49.975+00:00 — Tholin (@tholin)

Content

Also, the SRAM macros have DRC errors.
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message-1434063240937209897

2025-11-01T06:15:20.246+00:00 — tnt (@246tnt)

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Are you sure they do ?  AFAIR Magic thinks they do because the tech file doesn't know about sram rules. But if you checks they are all false positive
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message-1434099538993610854

2025-11-01T08:39:34.377+00:00 — RebelMike (@rebelmike)

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I believe the SRAM macro in https://github.com/MichaelBell/ttgf0p2-tinyQV/actions/runs/18697252507 is connected correctly, though would appreciate a double check on that!

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message-1434099964790968361

2025-11-01T08:41:15.895+00:00 — RebelMike (@rebelmike)

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However, that project is a bit stalled, both because of the DRC errors (which should be ignorable), and because when I increased the utilisation I started getting LVS errors.
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message-1434112175190052884

2025-11-01T09:29:47.081+00:00 — tnt (@246tnt)

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It's connected through power but only on the end. The only reason I can think of for that is that the LEF only defines the end zone as pins for connections.
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message-1434112203144822794

2025-11-01T09:29:53.746+00:00 — tnt (@246tnt)

Content

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message-1434112720692842506

2025-11-01T09:31:57.139+00:00 — tnt (@246tnt)

Content

It's also connected in the center control zone. So maybe they wanted to avoid random vias in the SRAM core zone, maybe it can distord metal a bit or cause some stress that they didn't want to risk given the tighter rules they use in there.
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message-1434126597874647142

2025-11-01T10:27:05.717+00:00 — RebelMike (@rebelmike)

Content

Yeah, I had to be fairly precise aligning the met4 stripes to get the connections to align with the pins.
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message-1434554098409148537

2025-11-02T14:45:49.787+00:00 — Tholin (@tholin)

Content

Any reason why only those end zones are valid pins? Could the LEF be updated to label the whole horizontal strips?
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message-1434585508750819479

2025-11-02T16:50:38.596+00:00 — tnt (@246tnt)

Content

As stated above, the only reason I can think of is avoid any disturbance in the sram core area ...
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message-1439008444035236022

2025-11-14T21:45:48.542+00:00 — RebelMike (@rebelmike)

Content

I'm trying to do a quick port of TinyQV to the wafer space template.  I've hit the problem that a lot of the verilog has declaration after use, which isn't supported by iverilog 13.  Is there an easy way to get iverilog 12 in the nix environment to get the tests passing?  I tried simply commenting out the iverilog line in the nix.flake (in the hope of picking up the version from the system) but that didn't seem to help (or possibly I need to do something to pick up the change - I am new to nix)
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message-1439014385812115669

2025-11-14T22:09:25.172+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Leo Moser (mole99) ^
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message-1439201953564459069

2025-11-15T10:34:44.809+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

The template uses iverilog from nix-eda: https://github.com/fossi-foundation/nix-eda/blob/main/nix/iverilog.nix
We can simply override the version and hash using an overlay:

```diff
diff --git a/flake.nix b/flake.nix
index 637792a..4e53bc1 100644
--- a/flake.nix
+++ b/flake.nix
@@ -31,7 +31,18 @@
       system:
         import nixpkgs {
           inherit system;
-          overlays = [nix-eda.overlays.default devshell.overlays.default librelane.overlays.default];
+          overlays = [nix-eda.overlays.default devshell.overlays.default librelane.overlays.default (final: prev: {
+              iverilog = (prev.iverilog.override {
+                version = "12.0";
+                rev = null;
+                sha256 = "sha256-J9hedSmC6mFVcoDnXBtaTXigxrSCFa2AhhFd77ueo7I=";
+              }).overrideAttrs {
+                env = {
+                  NIX_CFLAGS_COMPILE = "-Wno-error=format-security";
+                };
+              };
+            })
+          ];
         }
     );
```

(I also had to add a cflag in order for it to compile.)
The first time you enable the Nix shell, iverilog will be built, after that, it is cached.
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message-1439211511489761422

2025-11-15T11:12:43.596+00:00 — RebelMike (@rebelmike)

Reply/reference

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Content

Thank you! I’ll give that a try

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message-1439297498152702025

2025-11-15T16:54:24.414+00:00 — tnt (@246tnt)

Content

@Leo Moser (mole99) AFAICT for the PAD_xxx config you need exact names you can't use regexps 😢
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message-1439299861479428167

2025-11-15T17:03:47.875+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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You mean in the LibreLane pad ring config? Yeah, that would be a nice feature. I'll see if I can add it in https://github.com/librelane/librelane/pull/806. I'm quite busy at the moment, though 😅
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message-1439379609614287011

2025-11-15T22:20:41.312+00:00 — BreakingTaps (@polyfractal)

Content

the SRAM verilog macros in the PDK are fully functional, right? Debugging an issue in my code and want to verify that they do, infact, work as intended 🙂

(I've successfully stored and retrieved, but when writing to same address twice there are problems. Fairly sure it's my fault elsewhere though)
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message-1439450501266673776

2025-11-16T03:02:23.199+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Yes, I believe @Tholin has demonstrated them working?
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message-1439450607441281075

2025-11-16T03:02:48.513+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

https://www.crowdsupply.com/wafer-space/gf180mcu-run-1/updates/tholin-feature

Embeds

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message-1439634281860436090

2025-11-16T15:12:39.907+00:00 — BreakingTaps (@polyfractal)

Content

aha, missed that. thanks! most definitely a me-problem then 🙂
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message-1442464395820138567

2025-11-24T10:38:31.656+00:00 — LukeW (@luke_w)

Content

Are you still having trouble with the RAM @BreakingTaps? If you post some waves then I can have a squint at them
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message-1442464485389500446

2025-11-24T10:38:53.011+00:00 — LukeW (@luke_w)

Content

Ah, that message was older than I thought 😅
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message-1442548772914860032

2025-11-24T16:13:48.723+00:00 — BreakingTaps (@polyfractal)

Content

yah all good now, thanks for checking! was indeed a "me-problem" in my code 🙂

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message-1442562777159041194

2025-11-24T17:09:27.595+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Need advice! I would like to add 16KB of RAM (32 macro x SRAM 512 5V), I have quite a lot of free space, so it should fit. Any gotchas for laying out 32 blocks in a good manner for memory?

*(Z80 design I am working on has a lot of free space, I want to put 16KB of RAM. That particular combinations Z80+16KB RAM is useful for fixing DRAM in old computers)*
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message-1442601943942824047

2025-11-24T19:45:05.684+00:00 — LukeW (@luke_w)

Content

If the bus was wider than 8 bits I'd say keep all the RAMs for the same byte lane in the same row or column, but that doesn't really apply here 😅
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message-1442602458097385503

2025-11-24T19:47:08.268+00:00 — LukeW (@luke_w)

Content

Make sure to leave enough gap in between the RAMs for the tools to insert buffers. Generally pick one pair of orientations (N/S only or W/E only) so that fly-by routing over the top of the RAMs on M4/M5 does a better job of hooking up the address bus. It can be useful to alternate N-S-N-S because iirc the D connections are all on one side of the RAM, and the Q are all on the other side

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message-1442602555686260930

2025-11-24T19:47:31.535+00:00 — LukeW (@luke_w)

Content

oh, and try to leave space in the middle of your RAM array for your design, so it's routing across half the chip (worst case) not the whole chip

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message-1442773613743706184

2025-11-25T07:07:14.954+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Content

Fixing DRAM in old computers? Do you mean emulating DRAM using SRAM or something else?
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message-1442785666336559235

2025-11-25T07:55:08.516+00:00 — ReJ aka Renaldas Zioma (@rzioma)

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Yes. The fix is to use onchip SRAM block connected directly to Z80 instead of external DRAM (which usually were multiple of ICs with high chance of failure during the long lifetime). External DRAM ICs are simply pulled from the mainboard of the computer.

Adding 64KB would be better and more generic, but I can't fit them right now.
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message-1442786485991506022

2025-11-25T07:58:23.937+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

16KB is good enough to fix that common breakage in ZX Spectrum family (allegedly the most sold Z80 home computer). They had 16KB (in 8ICs) of slightly faster memory which would die more often.
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message-1442788509558636607

2025-11-25T08:06:26.393+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

@Tim 'mithro' Ansell I am also adding a couple of companion chips that were common in combination with Z80.
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message-1442790638184566876

2025-11-25T08:14:53.897+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Content

Not yet sure it is worth the additional risk though 🙂
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message-1442797395648970813

2025-11-25T08:41:45.002+00:00 — ReJ aka Renaldas Zioma (@rzioma)

Reply/reference

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Thank you!
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message-1443583289851121715

2025-11-27T12:44:36.781+00:00 — tnt (@246tnt)

Content

Huh ... so as part of testing I wanted to remove the `DualGate` layer from the standar cells to make the transistors 3v3 instead of 5V. Yes, they're gate would be longer than needed because I'm not resizing them, just changing the oxide thickness, hoping for them to get faster basically.
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message-1443583377910267924

2025-11-27T12:44:57.776+00:00 — tnt (@246tnt)

Content

But ... simulation shows they get _slower_ ....
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message-1443583671926915213

2025-11-27T12:46:07.875+00:00 — tnt (@246tnt)

Content

First theory is of course, thinner oxide means more gate capacitance and whatever gain we have from the thinner oxide forming better channel gets overwhelmed by the higher gate capacitance.
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message-1443583747508142151

2025-11-27T12:46:25.895+00:00 — tnt (@246tnt)

Content

I could also have screwed up my simulation somewhere ...
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message-1443584602139660339

2025-11-27T12:49:49.655+00:00 — Tholin (@tholin)

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I'd say its because the gate lengths are still the same
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message-1443586095307559062

2025-11-27T12:55:45.654+00:00 — tnt (@246tnt)

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Well yeah, I know it's because their length is the same, but through what effect.
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message-1443586310144262294

2025-11-27T12:56:36.875+00:00 — tnt (@246tnt)

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At 3.3V Vg and Vds, Ids is higher for 3v3 one (as expected) so it's better at passing current. (same W/L)
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message-1443586415702052864

2025-11-27T12:57:02.042+00:00 — tnt (@246tnt)

Content

Although looking at the curve, it's really not _that_ much better.
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message-1443588635982303312

2025-11-27T13:05:51.398+00:00 — bailey (@bailey8889)

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@tnt For a given gate size, wouldn't lower voltages mean slower circuits?
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message-1443588854668984481

2025-11-27T13:06:43.537+00:00 — tnt (@246tnt)

Content

@bailey I'm changing the transistor type, but both get powered using 3v3 .

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message-1443589003646599271

2025-11-27T13:07:19.056+00:00 — tnt (@246tnt)

Content

Of course if I'm powering the 5V with 5V they go faster 😁

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message-1454559562727165962

2025-12-27T19:40:24.164+00:00 — BreakingTaps (@polyfractal)

Content

given how big GF's SRAM blocks are at the small end (64 words is half the size of 512!), do you think it'd end up being more area-efficient to just use registers/flip flops for small "sram-like" banks? say 16 words / 128 bits?
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message-1454560511696830679

2025-12-27T19:44:10.416+00:00 — BreakingTaps (@polyfractal)

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just criminal 😄

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message-1454562609457270929

2025-12-27T19:52:30.561+00:00 — BreakingTaps (@polyfractal)

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(suppose it's easy enough to try it out heh)
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message-1454575734092730455

2025-12-27T20:44:39.718+00:00 — tnt (@246tnt)

Content

You can just take the are of a FF and multiply it and see how close you are.
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2025-12-27T20:45:22.262+00:00 — tnt (@246tnt)

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For wide shallow  mem, the muxing/addr decode won't be too bad so it's a good first rough estimate.
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message-1454626774779695134

2025-12-28T00:07:28.766+00:00 — BreakingTaps (@polyfractal)

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aha ok. so with some generous assumptions on the overhead plumbing, a 16x8 might looks something like this (albeit witih flexibility to smoosh into odd corners due to being not a macro block)

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message-1454691750437191752

2025-12-28T04:25:40.17+00:00 — Greg (@greg.hashtag.9468)

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Have you seen: https://github.com/AUCOHL/DFFRAM
Their approach is to create a macro block containing standard cells for different memory configurations. This can be more dense than just having a large FF based RAM along with your RTL, and in theory speeds up synth/PnR. I'd suspect the final QoR ends up slightly worse.

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message-1454691970017660929

2025-12-28T04:26:32.522+00:00 — Greg (@greg.hashtag.9468)

Content

Might be handy for size comparisions
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2025-12-28T17:52:17.253+00:00 — BreakingTaps (@polyfractal)

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oh awesome, I had not seen that. cheers for the link!
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message-1455387744519065691

2025-12-30T02:31:18.09+00:00 — Tim 'mithro' Ansell (@mithro_)

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@BreakingTaps - https://docs.google.com/spreadsheets/d/1fW5ecBsLSec4hXBMaOjMUHQGslm4y-QUILgrxqS8MpA/edit?gid=0#gid=0

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message-1455387905722679440

2025-12-30T02:31:56.524+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - I believe @Tim Edwards's 3v3 SRAM is quite a bit smaller?
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message-1455390134244606082

2025-12-30T02:40:47.845+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@BreakingTaps :  One reason the GF SRAMs don't scale well is that they all contain the same 10-bit address decoder and sense amps designed for a 128-row array.

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message-1455608224815382560

2025-12-30T17:07:24.689+00:00 — BreakingTaps (@polyfractal)

Content

oof 😄
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message-1455665497084531075

2025-12-30T20:54:59.462+00:00 — BreakingTaps (@polyfractal)

Content

generated a few latch and dff banks using dffram, neat project! latches were consistently 10-15% smaller than dff, and as expected they are all quite a bit bigger than the foundry optimized banks. Not really a fair comparison, will probably run some tests comparing it against a dumb register array since that's a lot closer to the use case

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message-1465456700017606761

2026-01-26T21:21:44.153+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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@BreakingTaps - That is super cool! Can you publish that somewhere publically?
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message-1465457575330840819

2026-01-26T21:25:12.844+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@BreakingTaps - I would expect the latch version to be more like 30-40% smaller than the DFF version but maybe they need optmized layouts or something?
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message-1465459372468731989

2026-01-26T21:32:21.315+00:00 — tnt (@246tnt)

Content

@Tim 'mithro' Ansell In latch vs DFF only the storage element is smaller. All the address decoding and enable and muxing logic is the same and it's not small either.
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message-1465459697342742782

2026-01-26T21:33:38.771+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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True. That this is why data is better than random speculation from me 🙂
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message-1468292602112508041

2026-02-03T17:10:35.901+00:00 — BreakingTaps (@polyfractal)

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I'll tidy and throw it up on github this weekend!
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message-1468292936495009794

2026-02-03T17:11:55.624+00:00 — BreakingTaps (@polyfractal)

Content

(should also note that they failed DRC with a ton of violations, so probably not super reliable results)
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message-1468392481161875629

2026-02-03T23:47:28.922+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Will have to figure out how to clean them up.
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message-1468846460597571636

2026-02-05T05:51:26.054+00:00 — EmbeddedKen (@embeddedken)

Content

I'm working on an I/O pad library for 1.8V - 3.6V LVCMOS with adjustable slew and LVDS/CML options.
For LVCMOS 3.3V, seeing half-nanosecond edges with 15pF of load; good for >500Mhz using GF's 3.3V FETs.
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message-1468846716533866558

2026-02-05T05:52:27.074+00:00 — EmbeddedKen (@embeddedken)

Content

Any padrings so far that supported 3.3V I/O?
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message-1468857901308444896

2026-02-05T06:36:53.732+00:00 — Lofty (@ravenslofty)

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as I understand it, the default padring works fine with 3.3V I/O as long as you're also doing 3.3V Vcore
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message-1468905143020818562

2026-02-05T09:44:37.034+00:00 — Leo Moser (mole99) (@mole99)

Content

That's correct, there are even liberty views for ~3.3V.
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message-1470663228974432376

2026-02-10T06:10:37.389+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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What are you working on? LVDS/CML is something that is very interesting to me 🙂 - I would to get us to PCIe eventually.
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message-1470669143538667739

2026-02-10T06:34:07.531+00:00 — EmbeddedKen (@embeddedken)

Reply/reference

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An FPGA with 5V core and 1.8V-3.3V I/O; maybe a test gigabit transceiver for proving out SGMII or PCIe x1 Gen1 physical-layer capability.
I think 2.5 Gbps may be almost within the realm of reach for half-rate architecture; solid PLL and CDR would be the limiting factors.
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message-1470669338913800315

2026-02-10T06:34:54.112+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Have you seen https://bit.ly/open-pipe-talk ?

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message-1470669372220637216

2026-02-10T06:35:02.053+00:00 — EmbeddedKen (@embeddedken)

Content

The associated PIPE interface and Hard IP would be quite a technical challenge; possible greater than PMA development
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message-1470669392818995397

2026-02-10T06:35:06.964+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Also have you seen @Leo Moser (mole99)'s FPGA?
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message-1470669491200327812

2026-02-10T06:35:30.42+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@EmbeddedKen - If you get me the SERDES, I can get you the PIPE and reset of the stack

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message-1470669748080611422

2026-02-10T06:36:31.665+00:00 — EmbeddedKen (@embeddedken)

Content

I do have a PCIe serial logic analyzer for decoding DLLPs and TLPs; which could help with silicon bring-up and have extensive experience debugging PCIe for FPGAs.
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message-1470669900539363483

2026-02-10T06:37:08.014+00:00 — EmbeddedKen (@embeddedken)

Reply/reference

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I'll see what I can do- I'm not an analog wizard; I think PLL/CDR will be the most challenging
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message-1470670046459068557

2026-02-10T06:37:42.804+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@EmbeddedKen - @Mehdi and the openfasoc project where working on high quality PLL and CDR structures for SERDES in the past, I have no idea were they ended up getting too. There is some very out of date stuff in https://bit.ly/goog-analog

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message-1470670236129820683

2026-02-10T06:38:28.025+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Their general approach was to write generators so they could eventually tape out like 50 variants to find the best solution.
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message-1470670321106554941

2026-02-10T06:38:48.285+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@EmbeddedKen - If we could do the slowest USB3 speed, that would be pretty epic.
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message-1470670496281399339

2026-02-10T06:39:30.05+00:00 — EmbeddedKen (@embeddedken)

Content

One of the first PCIe Gen1 devices was on 180nm- which provides some additional hope. 2.5Gbps is definitely pushing the limits of the process node.
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message-1470670589378428990

2026-02-10T06:39:52.246+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

This group is one I know attempting to do some stuff -> https://github.com/chili-chips-ba/openPCIE

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message-1470670704021213357

2026-02-10T06:40:19.579+00:00 — Tim 'mithro' Ansell (@mithro_)

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@EmbeddedKen - https://github.com/mithro/open-pcie-status

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message-1470670828160155813

2026-02-10T06:40:49.176+00:00 — EmbeddedKen (@embeddedken)

Reply/reference

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I thought SuperSpeed started at 5Gbps... that is probably well out of reach.
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message-1470670918157078568

2026-02-10T06:41:10.633+00:00 — EmbeddedKen (@embeddedken)

Content

Awesome info- I'll dive into these
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message-1470671101247094855

2026-02-10T06:41:54.285+00:00 — EmbeddedKen (@embeddedken)

Content

Amazing to think there's others out there working on PIPE 👏
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message-1470674869715992606

2026-02-10T06:56:52.758+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@EmbeddedKen - But yeah, high performance IO would be a great step, even if initially it starts at like 250MHz and then we slowly improve until we can get the 1.5GHz (or is it just 1 GHz, I've forgotten?) needed.
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message-1470676208252616876

2026-02-10T07:02:11.89+00:00 — EmbeddedKen (@embeddedken)

Content

480Mbps for USB2 HS (UTMI)
1.25Gbps for 1000BASE-X/SGMII (GMII)
2.5Gbps for PCIe Gen1 (PIPE)
5.0Gbps for PCIe Gen2 / USB3 SS (PIPE)
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message-1470679411576668250

2026-02-10T07:14:55.622+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Cool! Which tools are you targeting for synthesis and PnR? FABulous uses Yosys and nextpnr.
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message-1470703735016652921

2026-02-10T08:51:34.782+00:00 — tnt (@246tnt)

Content

@EmbeddedKen But the first PCIe was on a true 180nm right ? Here we only have "IO" device, no real 180nm transistors.
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message-1472370729327661108

2026-02-14T23:15:37.197+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

https://docs.google.com/document/d/1ItFfVkK6SQFjOv5kzzwCAq5x_xVZee9zKB7v0VDrYKk/edit?tab=t.0#heading=h.dz6yjd8i5d0

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message-1472371055334264884

2026-02-14T23:16:54.923+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Ahh - I always get confused because SATA is 1.5gbit/s which is the first of these "real" LVDS 8b10b protocols if I understand correctly... https://docs.google.com/document/d/1krIVSZw_FwjG7sroVZ3IIVIHmBZ76r8e4mBtlCwJy6k/edit?tab=t.0#heading=h.cec2048bak8g

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message-1472371330560167937

2026-02-14T23:18:00.542+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

Some very old stuff from 2020 around the time released SKY130 - https://drive.google.com/drive/folders/1A6K2b9VFvGC5VRVsnGBQJYwM-L2GsjAI?usp=drive_link

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message-1472401168008351898

2026-02-15T01:16:34.344+00:00 — EmbeddedKen (@embeddedken)

Content

1000BASE-X/SGMII are LVDS 8b/10b at 1.25Gbps.

Are SATA III devices able to negotiate down to 1.5Gbps? I've heard there's an additional physical-layer feature called "beaconing" that some transceivers have to support SATA.
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message-1480941519497203886

2026-03-10T14:52:52.811+00:00 — Egor Lukyanchenko (@egorxe)

Content

I've finally written some comprehensible documentation for my open-source eFuse OTP memory compiler, which was used to generate eFuse IPs for the Run 1 testchip. In case someone is considering using eFuse in their design during later runs, please [check it out](https://github.com/egorxe/gf180_efuse_compiler). I'm open to any suggestions regarding compiler improvements, and would be happy to assist with eFuse IP integration if needed.

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message-1480948927371939933

2026-03-10T15:22:18.986+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Started a thread.
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message-1481880826475053097

2026-03-13T05:05:21.046+00:00 — beardothaweirdo (@wspitts2)

Reply/reference

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Content

If it is helpful, I have a pretty nice systemverilog testbench I can share when I used to teach a SerDes course. It is integrated into virtuoso, Basically, it drops a random 8 bits out -> 8b10b encoding -> PISO -> channel driver -> channel -> CTLE/AMP/DFE -> slicer -> 10b8b decode ->  compares to the random 8bits that should have been sent and flags it. There is a CDR attached to the slicer. it is not PAM4 but it could be extended to that.
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message-1481881133422612522

2026-03-13T05:06:34.228+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@beardothaweirdo - Any chance you could port to open source tooling? Verilator's systemverilog testbench support has come a long way these days.
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message-1481881721036210277

2026-03-13T05:08:54.326+00:00 — beardothaweirdo (@wspitts2)

Content

Well, it is system verilog, I could share the testbench structure. Basically, I had students design everything from the 8b10b output to the 10b8b input via schematics in FreePDK15 and FreePDK3. I could help stand up the FreePDKs at least from questions and simulations if needed. I upgraded the FreePDK15 to have integration in cadence instead of python wrappers and I did the TCAD to Spice on the models and setup a cadence PDK for schematics (no DRC/LVS).
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message-1481881825902198976

2026-03-13T05:09:19.328+00:00 — beardothaweirdo (@wspitts2)

Content

I can share my systemverilog source
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message-1481881909301612544

2026-03-13T05:09:39.212+00:00 — beardothaweirdo (@wspitts2)

Content

and I can check to make sure that the 8b10b and 10b8b encoding/decoding is shareable (I think I snagged it offline).
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message-1481882112112988313

2026-03-13T05:10:27.566+00:00 — beardothaweirdo (@wspitts2)

Content

The real power in it is that all bits that go down the channel are kept in a memory in the testbench and then they are checked as they come off the final reciever.  I also have some VerilogA and VerilogAMS of all the other components in there as well.
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message-1481882528682872977

2026-03-13T05:12:06.884+00:00 — beardothaweirdo (@wspitts2)

Content

If you can do mixed mode simulation then this is a good testbench for SerDes. I have one with a verilogA PLL and another with a verilogAMS DLL. have a few topologies things as well in there.
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message-1481883395876323450

2026-03-13T05:15:33.639+00:00 — beardothaweirdo (@wspitts2)

Content

I am not sure I will have the time to port it over the next couple of months. I also have something similar for a flipflop.
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message-1481885804803653733

2026-03-13T05:25:07.972+00:00 — beardothaweirdo (@wspitts2)

Content

I have a pile of stuff from the Digital Electronics course I taught for a while. At some point I guess I need to just port it to opensource and put it in the wild. but there are only so many hours in the day and I am spoiled with industry tools.
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message-1481886603486953574

2026-03-13T05:28:18.393+00:00 — beardothaweirdo (@wspitts2)

Content

Oh, I didn't hit reply to you @Tim 'mithro' Ansell
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message-1481906849472315462

2026-03-13T06:48:45.412+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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Maybe find some excited undergrads to do it for you? 😛
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message-1481907387504787516

2026-03-13T06:50:53.689+00:00 — beardothaweirdo (@wspitts2)

Reply/reference

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It was a PhD level class... as far as I know I am the only undergraduate I know that had ever taken in when Dr. Franzon was teaching the course. It was how I got into his research group as an undergraduate.
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message-1484230082729082963

2026-03-19T16:40:27.384+00:00 — Matt G. (Mobius) (@mguthaus)

Reply/reference

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I just put this together for cocotb AMS with standard spice rather than VerilogA/VerilogAMS: https://github.com/VLSIDA/cocotbext-ams

Embeds

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message-1484230756137046096

2026-03-19T16:43:07.937+00:00 — beardothaweirdo (@wspitts2)

Reply/reference

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Cool, I will take a look! There are both veriloga and verilogams can it handle both? I assume it handles system verilog and verilog too.
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message-1484230889490612406

2026-03-19T16:43:39.731+00:00 — Matt G. (Mobius) (@mguthaus)

Reply/reference

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No, it cannot handle either verilogA nor verilogAMS.
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message-1484231003768750161

2026-03-19T16:44:06.977+00:00 — Matt G. (Mobius) (@mguthaus)

Reply/reference

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It's intended as spice + (System) Verilog
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message-1484231177253421129

2026-03-19T16:44:48.339+00:00 — Matt G. (Mobius) (@mguthaus)

Reply/reference

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Are you aware of any open tools for VerilogA/VerilogAMS verification against spice?
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message-1484231293079388261

2026-03-19T16:45:15.954+00:00 — Matt G. (Mobius) (@mguthaus)

Content

I'm not sure I like this discord threading. (I don't usually use discord)
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message-1484232477861089492

2026-03-19T16:49:58.428+00:00 — beardothaweirdo (@wspitts2)

Content

Verilog-A → OpenVAF → ngspice
Digital → Verilator

Is one possible, no vams though just verilogA which is workable (you can just break verilogams into a verilogA and verilog file, but that is not as closely coupled @Matt G. (Mobius)
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message-1484232670094557194

2026-03-19T16:50:44.26+00:00 — beardothaweirdo (@wspitts2)

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Gnucap Verilog-AMS is an attempt that is out there. Maybe we can improve it to support. Not opposed to writing a proposal for it either.
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message-1484233073779409017

2026-03-19T16:52:20.506+00:00 — beardothaweirdo (@wspitts2)

Reply/reference

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Lol you and me both, it is easier than some, worse than others, but long gone it seems are the days of emacs, irc, bbs, and vim users... Le sigh...
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message-1484238974368223263

2026-03-19T17:15:47.316+00:00 — nmz787

Reply/reference

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I'm still on libera IRC, there's even some discord servers I'm in with a bot that bridges the two

Reactions

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message-1484258429160787968

2026-03-19T18:33:05.7+00:00 — Matt G. (Mobius) (@mguthaus)

Reply/reference

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I am as well, but no bridge.
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message-1484271774932668518

2026-03-19T19:26:07.58+00:00 — Thomas Dexter (@tdextrous)

Reply/reference

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One thing with respect to the verilog-a -> OpenVAF flow is that the Verilog-a syntax support is very minimal. I believe this was intended to support device models that are in Verilog-a first and foremost, and less so about supporting behavior models e.g. for vcos or other analog blocks. So a lot of the models you might find on designer's guide won't work with this flow to my knowledge.
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message-1484308035454111965

2026-03-19T21:50:12.762+00:00 — beardothaweirdo (@wspitts2)

Reply/reference

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Well that is disheartening.
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message-1484310020593029180

2026-03-19T21:58:06.056+00:00 — beardothaweirdo (@wspitts2)

Content

has anybody used Gnucap? @Thomas Dexter
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message-1493868028239151135

2026-04-15T06:58:12.658+00:00 — Ugnas (@ugnas_)

Content

Hi, guys, amazing project! I have been following your progress quietly for some time, and I truly believe you are transforming the IC landscape.
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message-1493868393932132362

2026-04-15T06:59:39.846+00:00 — Ugnas (@ugnas_)

Content

Sorry if it is off-topic. I am a bit digital designer myself but have not touched any wafer or anything in my life yet 😁
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message-1493868638485217401

2026-04-15T07:00:38.152+00:00 — Ugnas (@ugnas_)

Content

I have dreamed about building a SoC myself and a pretty complex one, but honestly do not have an idea how it works in corporate industry.
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message-1493869307556266044

2026-04-15T07:03:17.671+00:00 — Ugnas (@ugnas_)

Content

Are there any companies or individuals capable of developing an H.264 encoder ASIC from an existing IP core without requiring a multi-million-dollar budget? Since you have more experience in this field, could you recommend how to find a smaller, less corporate provider to work with?
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message-1493873120027607142

2026-04-15T07:18:26.635+00:00 — Dory (@dorythecat_v2)

Reply/reference

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For companies, you could try something like chipfoundry, or other manufacturers, who offer this service, though it tends to be pretty expensive. Otherwise, you can always try to go for individuals freelancing or even students in need of a thesis xd
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message-1493873413427826819

2026-04-15T07:19:36.587+00:00 — Ugnas (@ugnas_)

Content

Thanks!
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message-1493873739643748365

2026-04-15T07:20:54.363+00:00 — Ugnas (@ugnas_)

Content

I think is is almost impossible to find someone who freelances in such industry 😁  The community is still too small..
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message-1493874446426050580

2026-04-15T07:23:42.873+00:00 — Dory (@dorythecat_v2)

Reply/reference

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I mean I'm just a student but I've designed chips before for fun so I don't see how getting paid for doing something I enjoy is not a good thing
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message-1493874605683904592

2026-04-15T07:24:20.843+00:00 — Dory (@dorythecat_v2)

Content

If you want some help, if not with the chip itself, with resources so you can learn too how to design your own chips (which, if you have FPGA experience isn't really that hard). I'd be glad to lend a hand :D

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message-1493880340651966524

2026-04-15T07:47:08.166+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I would not start doing H.264, start with something simple like MJPEG or similar
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message-1493880654268731485

2026-04-15T07:48:22.938+00:00 — Ugnas (@ugnas_)

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Yeah, thats understandable encoders are very complex. We already have an IP block purchased for FPGA use, I hope we can reuse that.
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message-1494675024190247054

2026-04-17T12:24:55.486+00:00 — Egor Lukyanchenko (@egorxe)

Reply/reference

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If the license for your FPGA IP core allows porting it to another technology (which usually is not the case), it should be doable. But I doubt that GF180MCU is fast enough for H.264 to encode video at any useful speed.
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message-1496523684826058813

2026-04-22T14:50:50.528+00:00 — azonenberg

Content

also if its a commercial FPGA IP it almost certainly make use of FPGA-specific primitives and might even be an encrypted blob
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message-1496523705549848650

2026-04-22T14:50:55.469+00:00 — azonenberg

Content

good luck getting that working on ASIC
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message-1496877801523904713

2026-04-23T14:17:58.528+00:00 — Tim 'mithro' Ansell (@mithro_)

Reply/reference

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I'm not sure how low resolution H.264 allows, maybe you could do a 64x64 pixel H.264 encoder for ants? 😛
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message-1496879616483266662

2026-04-23T14:25:11.248+00:00 — Egor Lukyanchenko (@egorxe)

Reply/reference

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I'm quite sure there are better codec options for that 🙂 .
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message-1498664837214109718

2026-04-28T12:39:01.038+00:00 — Tholin (@tholin)

Content

This is still a thing that can happen? :flop:

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message-1500052907712843907

2026-05-02T08:34:42.834+00:00 — Zhekar1998 (@zhekar1998)

Content

Hi! If we have some 1024x64 or 1024x32 SRAM Macro?
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message-1500060345224396921

2026-05-02T09:04:16.075+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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You can find the foundry provided SRAMs here: https://github.com/wafer-space/gf180mcu/tree/main/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/gds
They are 8 bits wide, so you'll need to use several in parallel.
There are also community-designed 3.3V SRAMs, but they haven't been verified yet.
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message-1503895856074457241

2026-05-12T23:05:13.122+00:00 — Tholin (@tholin)

Content

Okay, I finally have a reproducible for the whole LVS gets stuck with my SCL issue
Clone the SCL repo at `https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3`
Open a terminal in example_project
`nix-shell`
`make clone-pdk`
`make setup`
`make`
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message-1503896149076082828

2026-05-12T23:06:22.979+00:00 — Tholin (@tholin)

Content

You can disable DRC to make it go faster
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message-1504214744318349445

2026-05-13T20:12:22.004+00:00 — Tim Edwards (@rtimothyedwards_19428)

Content

@Tholin :  Here is a complete set of xschem symbols for your GF 3.3V standard cell library, if you could please add it under `libs.tech/xschem`.

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message-1504640285299179681

2026-05-15T00:23:18.88+00:00 — Tholin (@tholin)

Content

Certainly. Good work.
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message-1507807238935417086

2026-05-23T18:07:39.466+00:00 — Zhekar1998 (@zhekar1998)

Content

Hi everyone.
This is my first public open-silicon review package, so I’d really appreciate ASIC/PD feedback.
I built a compact 3.3V-only GF180 I/O candidate library for wafer.space/open MPW experiments:
- 160um pad depth
- 100 signal pads
- ~17.3mm² usable core area
- local DRC/LVS completed
- LEF/CDL/SPICE/Liberty/IBIS generation
- preliminary ngspice PVT/DC characterization
- config/package generation flow included
The project was developed using an automated agent-in-the-loop exploration flow with manual review and verification.
Main goal: reduce padframe overhead for small GF180 SoCs.
Any comments on architecture, verification flow, pad strategy, or obvious mistakes would be greatly appreciated.
https://github.com/Detronyx-labs/gf180_compact_3v3_io.git

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message-1507861645458800670

2026-05-23T21:43:50.992+00:00 — Zhekar1998 (@zhekar1998)

Content

@Tim Edwards  Hi Tim,
I finally cleaned up and published my GF180MCU 3.3V 12T 2R2W SRAM macro experiment, which borrows from the transistor/layout concepts in your 512x8 reference.
Repo (Apache-2.0): https://github.com/Detronyx-labs/gf180mcu-3v3-12t-2r2w-sram-macro
To be completely honest, this is a fast AI-native / agentic design experiment — put together in about 3–4 days of intense work alongside Codex/LLM to see how far an automated open flow could push a custom multi-port layout. It is definitely not tapeout signoff collateral yet.
If you (or anyone here) have a few minutes to glance at the README, I’d love to get a brutal reality check from actual silicon experts on a few things:
Physical & Escape Routing: Are the 12T bitcell layout and shared M4/M5 escape assumptions physically defensible for GF180, or are we begging for major EM/IR-drop failures during simultaneous 2R/2W operations?
Extraction limitations: My local Magic techfile isn't emitting capacitance coefficients for this flavor, so we’re stuck using an OpenRCX geometry-fallback proxy for timing (which throws warnings). How critical is it to escape open-source PEX fallbacks for a custom multiport memory structure like this?
Prioritization: We have open items for full-macro LVS on row-edge boundaries, Liberty generation, and SNM/read-disturb sweeps. What should we absolute priority-target next to move this closer to tapeout-intent collateral?
Your documentation was a lifesaver for understanding practical GF180 implementation, so any feedback on where this automated flow breaks down in the real world would be awesome.
Thanks!

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message-1507936693326581831

2026-05-24T02:42:03.798+00:00 — namibj

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I've been working with Tim to get full-die PEX into a state that's reasonably considered "functional" for smoke testing with Xyce; a major block to using it for fancier behavioral testing is the need to use a separate digital logic simulator (verilator or so? not sure what exactly tbh.) to find FF/latch states of the entire chip at the desired jump-off point for a transient test run, and associating those to the individual signals in the chip to synthesize `.nodeset` commands that force the chip into that desired starting state with an initial DC-operating-point solution, from where it'd then continue settling a DC solution from that moment on that doesn't have the signals pegged to hard VDD/VSS anymore, followed by a few clocks of progress to let at least a bit of PDN parasitics settle in, before then doing the actual state changes of desired concern.

The extraction into Xyce-compatible PEX with _a lot_ of parasitic resistance and capacitance modeled is already working though; there's just a bit of scaling performance that seems to be left.

If you want I can test extraction on that macro later.
I need for that to work only top-level pins to be labeled; the rest will be flattened in KLayout if it's not already flattened, before I feed it to the PEX.
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message-1507942710643003577

2026-05-24T03:05:58.438+00:00 — namibj

Content

@Zhekar1998 Also if you're willing I'd love to talk a bit about how us two have been doing agentic "PCell" construction:
- you with the 12t-2r2w gf180mcuD sram, using Codex,
- I with so far a base MCML VCO cell but soon also the other base SerDes component cells (XOR2, MUX2, D-latch at least) on sky130A but with a bit of luck I can port that to gf180mcuD (in time to get a base demo VCO clocking an output MUX that's fed with a 16-wide PBRS-31 generator) into Run2), using Jules.
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message-1507949568317198478

2026-05-24T03:33:13.435+00:00 — namibj

Reply/reference

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The gds from `gf180mcu_3v3_12t_2r2w_sram_512x8` seems to short the VSS PDN columns of the top level cell due to misalignment across the VSS colunn and ` c3_r1_rbl` of the 4x4 block.
Please get at least basic LVS verification going before suggesting humans other than you yourself should look at the layout and give their opinions.
Exceptions would apply if without having to open a zipfile I could easily see that you're disclaiming that level of integration LVS to have been done.
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message-1507951942087999588

2026-05-24T03:42:39.386+00:00 — Zhekar1998 (@zhekar1998)

Reply/reference

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Thanks! Its interesting because I do LVS all times in every runs,  I recheck it now
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message-1507953265172545719

2026-05-24T03:47:54.834+00:00 — Zhekar1998 (@zhekar1998)

Content

Yes I find it. sorry I do some mistake in rules
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message-1507953478717276310

2026-05-24T03:48:45.747+00:00 — Zhekar1998 (@zhekar1998)

Content

I'll repear it and double check it by hands today)))
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message-1507953784796614676

2026-05-24T03:49:58.722+00:00 — namibj

Content

I don't know how you do that LVS but I suggest you attempt to do it on a flattened layout to check the hierarchy isn't causing problems.
It's hard to pin-point problems that way, but I'm pretty sure a basic abstracted-transistors (N/P and 3/4 pins) should be very much practical and a reliable check via graph-matching should be not-a-problem.
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message-1507954343238701197

2026-05-24T03:52:11.865+00:00 — namibj

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I have no idea what timezone you're sleep/wake cycle corresponds to; I am as mentioned interested in talking to you (German or English, your choice) about the flow and struggles of this agentic-scripted-cells flow.
Just in case you may be interested, that is.
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message-1507954619454586890

2026-05-24T03:53:17.72+00:00 — Zhekar1998 (@zhekar1998)

Reply/reference

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I'm in GMT +2 but. I will be hapy to speak about this
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message-1507955049223950346

2026-05-24T03:55:00.185+00:00 — namibj

Reply/reference

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oh same great then.
I've got a bit of stuff to do offline but in like 2 hours I'd have time to talk.

Sent you a DM for further discussing of that.

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message-1508132545747751045

2026-05-24T15:40:18.654+00:00 — Zhekar1998 (@zhekar1998)

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I fix it now. Its was mistake with logic of generator script.
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message-1508832799765827737

2026-05-26T14:02:52.222+00:00 — Tim 'mithro' Ansell (@mithro_)

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@Greg - You where interested in this?
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message-1508835057626910750

2026-05-26T14:11:50.538+00:00 — tnt (@246tnt)

Content

It's ... LLM generated garbage ...
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message-1508844058175471757

2026-05-26T14:47:36.436+00:00 — namibj

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I'll see to it; though this weekend including Monday+Tuesday (recovery) I'll be running on fumes, trade fair intense and weather melting.
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message-1508844632170303600

2026-05-26T14:49:53.287+00:00 — tnt (@246tnt)

Content

It'd be faster to start from scratch
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message-1508846148138438716

2026-05-26T14:55:54.722+00:00 — namibj

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I meant I'm gonna talk to them about their methodology in the general endeavor "vibe coding PCell/macro-generator".
I don't like it when people drop _broken_ slop at one's feet and request through whatever phrasing/request that one should code-review the _broken_ slop.

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message-1508854646083424286

2026-05-26T15:29:40.79+00:00 — Zhekar1998 (@zhekar1998)

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To give you the full picture: OpenRAM isn't available for GF180MCU at all, so I had to find a workaround for my project. I didn't just raw-prompt an LLM — I actually ran it in a verification loop with KLayout, Magic, and Netgen-LVS until it passed for my two specific configurations.
That said, I'm still just learning VLSI fundamentals, and I totally understand that an LLM-in-the-loop hack doesn't replace a proper, scalable macro-generator methodology. I’d love to join the discussion on how to build a robust generator the right way from scratch.
I fully understand about this project can have mistakes but, without mistakes its imposible to learn.
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message-1508855036384641064

2026-05-26T15:31:13.845+00:00 — Zhekar1998 (@zhekar1998)

Content

I try to build pipline where LLM will be generate code from big blocks and transistors. but not allways I can find generation mistaces
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message-1508855484554285197

2026-05-26T15:33:00.697+00:00 — Leo Moser (mole99) (@mole99)

Content

Staf will port his [flexmem SRAM generator](https://gitlab.com/Chips4Makers/c4m-flexmem) to gf180mcu for ws-run #2.

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message-1508856229110218892

2026-05-26T15:35:58.213+00:00 — Zhekar1998 (@zhekar1998)

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Oh thanks, I'll check it, Its can be helpfull
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message-1509460314155122759

2026-05-28T07:36:23.311+00:00 — RebelMike (@rebelmike)

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Started a thread.
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message-1511801096606187674

2026-06-03T18:37:49.337+00:00 — namibj

Content

Having an inverter at the output of a logic cell (buffering the internal node) is almost a given, right?
So any custom gates in any static logic family I have to draw I should expect to use an inverter as an output buffer after the actual gate itself, right?
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message-1511804973686456542

2026-06-03T18:53:13.705+00:00 — tnt (@246tnt)

Content

Sometimes you'll find `_0` variants of gates where it's directly the internal output but yeah that's rate and not that useful for general P&R where you'd almost always have an inverter at the output ... except if the cell in question is an inverter or a delay cell .

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message-1512006127766999142

2026-06-04T08:12:32.575+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

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Content

No. CMOS standard cells have NAND2 and AOI amd OAI cells that don't have inverter at the end and these cells will be used quite a lot in the synthesized netlist.
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message-1513203614556885073

2026-06-07T15:30:55.674+00:00 — BreakingTaps (@polyfractal)

Content

I just noticed the SRAM behavioral model has timing constraints (55.6 ns, ~18MHz). Do we know if this is a real limit of the SRAM, or just a quirk of the fab's sram model?
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message-1513277466205098064

2026-06-07T20:24:23.279+00:00 — RebelMike (@rebelmike)

Reply/reference

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That seems close to the 1.8V figures on https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/SRAM/gf180mcu_fd_ip_sram/cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.html
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message-1513277546849112236

2026-06-07T20:24:42.506+00:00 — RebelMike (@rebelmike)

Content

So I assume you can safely ignore at 5V or 3v3
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message-1513281229947142306

2026-06-07T20:39:20.625+00:00 — BreakingTaps (@polyfractal)

Content

aha good catch! Didnt realize the docs had those tables for the sram 👍
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message-1513281248078856233

2026-06-07T20:39:24.948+00:00 — BreakingTaps (@polyfractal)

Content

thanks!
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message-1513300372469448744

2026-06-07T21:55:24.558+00:00 — namibj

Content

Does anyone have t_FO4 on hand by chance?
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message-1514906558050472026

2026-06-12T08:17:49.042+00:00 — Tholin (@tholin)

Content

@RebelMike @Leo Moser (mole99) Overdue update to my SCL: non-inverting latches. So you can use those now and drop any inverters you had to place in your design.
Always remember to gate-level simulate, there should be no more missing cell models now.

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message-1514907040168939620

2026-06-12T08:19:43.988+00:00 — RebelMike (@rebelmike)

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Awesome, thank you!
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message-1514912033764544625

2026-06-12T08:39:34.554+00:00 — Leo Moser (mole99) (@mole99)

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Opened an open_pdks PR to update the hash: https://github.com/RTimothyEdwards/open_pdks/pull/525
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message-1516825766879428760

2026-06-17T15:24:04.084+00:00 — Deepak (@deempak)

Content

Hello everyone  I am trying to tapeout bunnie's Andrew Huang  BIO Core  https://www.crowdsupply.com/baochip/dabao/updates/bio-the-bao-i-o-co-processor   in ws 2 run
It has 2 core in a half height slot,  I started with 2Kb sram each core ( 4Kb total ie 8 macros of (512*8 ) ) but that arrangement is producing a lot of  routing congestion
I =have tried to stagger the columns vertically so they don't overlap in Y:
Column 1 (core 0): X = 442,  Y = 500, 1020, 1540, 2060   (bottom half)
Column 2 (core 1): X = 1060, Y = 2600, 3120, 3640, 4160   (top half)
But that is giving  bad timing paths and congestion.

Only Thing I can think of currently is to move 1Kb sram each core and use ( 8 macros of (256*8))

this is my first time working in backend and SRAM so I would like to know is there possibility to actually fit 4Kb in the slot ?

Sorry if the question is dumb or confusing .

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message-1516842914339225756

2026-06-17T16:32:12.357+00:00 — BreakingTaps (@polyfractal)

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Started a thread.
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message-1518698602955014387

2026-06-22T19:26:03+00:00 — Tholin (@tholin)

Content

Here we go again!

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message-1518698693619089538

2026-06-22T19:26:24.616+00:00 — Tholin (@tholin)

Content

A bit of a problem with the 3.3V SCL: the antenna rules are even stricter for 3.3V!
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message-1518720923652587540

2026-06-22T20:54:44.669+00:00 — BreakingTaps (@polyfractal)

Content

huh interesting, my design is using your 3v3 library and I don't think it ran into any non-user-error antenna violations (I had a few originally because it was trying to cram logic between two closely spaced macros and then no room for diode placement). will double check when I get home, maybe it did and I didn't notice!
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message-1519011198845325382

2026-06-23T16:08:11.668+00:00 — Tholin (@tholin)

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message-1519011218097180842

2026-06-23T16:08:16.258+00:00 — Tholin (@tholin)

Content

Where do I report this?
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message-1519011318819196979

2026-06-23T16:08:40.272+00:00 — Tholin (@tholin)

Content

Its a major issue because the only workaround for it I’ve found so far is it to crank the area of the macro up to way above what is actually necessary
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message-1519011477753823272

2026-06-23T16:09:18.165+00:00 — Tholin (@tholin)

Content

Which is currently having the result that using my SCL yields a *decrease* in density
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message-1519011527745863831

2026-06-23T16:09:30.084+00:00 — Tholin (@tholin)

Content

Just by having to insert lots of blank space to stop this error from happening
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message-1519012848083406930

2026-06-23T16:14:44.877+00:00 — Leo Moser (mole99) (@mole99)

Content

@Tholin You're likely hitting this bug in OpenROAD: https://github.com/The-OpenROAD-Project/OpenROAD/issues/10273

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message-1519013139427889182

2026-06-23T16:15:54.339+00:00 — Leo Moser (mole99) (@mole99)

Content

A workaround in LibreLane is to set `CTS_APPLY_NDR: "none"`. It disables non-default rules for CTS.
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message-1519069123353513984

2026-06-23T19:58:21.947+00:00 — Deepak (@deempak)

Reply/reference

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So I tried to figure a few thing out and it looks like
repair_design is inserting ~12K buffers on clock nets before CTS ie  +28% area explosion
in Stage 31 (OpenROAD.RepairDesignPostGPL) inserts 12K buffers causing a +28.5% area jump.
I then verifed in the openroad with the ODB , that shows only two nets with fanout above 50: clk_PAD2CORE (2,320 loads) and core_clk (980 loads)  both are clock nets. The repair is happening entirely on clock nets that CTS then rebuilds anyway. Zero data path violations exist . What is the correct LibreLane config variable to prevent repair_design from touching clock nets before CTS runs?

Also I noticed this warning [01:21:22] WARNING  [GRT-0281] Net clk_PAD2CORE has a large fanout of 2320 terminals.
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message-1519076867053719704

2026-06-23T20:29:08.189+00:00 — Leo Moser (mole99) (@mole99)

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Have you updated your project template and cloned the latest PDK? There was an issue in the OCD I/O cells that lead to CTS being skipped.
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message-1519079543699406972

2026-06-23T20:39:46.351+00:00 — Deepak (@deempak)

Reply/reference

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hello Yes i am on version 1.5.4 of template and i did run clone-pdk so its up to date.

Actually i am using a ICG Cell in my design so the clk_PAD2Core is input to that and core_clk is out put . So I suspect that .
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message-1519080970324807864

2026-06-23T20:45:26.485+00:00 — RebelMike (@rebelmike)

Content

It's possible that adding them to CLOCK_NET in the config would help.  I have: ```
CLOCK_NET:
- i_chip_core.real_clk_gf180mcu_as_sc_mcu7t3v3__mux2_2_Y/Y
- clk5x_pad/Y
```
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message-1519179629078909128

2026-06-24T03:17:28.565+00:00 — Deepak (@deempak)

Reply/reference

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Hello thank you , the sdc should add these  clock nets as create clock right ? or  clock group
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message-1519234163645878302

2026-06-24T06:54:10.619+00:00 — Deepak (@deempak)

Content

So the congestion seems to be only get blobbed in a small section of the chip rest is just empty  and tht is creating overflow in that local congestion And that ends up begin overflow in the GRT ( or that what i understood atleast)


Is there a way to spread it I have tried with different logic density already form 30 to 50
And sorry fro continues spam here i am bit newbie in Pnr .

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message-1519237258702749877

2026-06-24T07:06:28.538+00:00 — Leo Moser (mole99) (@mole99)

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Content

The variable you are searching for is [PL_TARGET_DENSITY_PCT](https://github.com/wafer-space/gf180mcu-project-template/blob/1db3a3bf89491ed497e21208e82f95734bab98db/librelane/config.yaml#L75). Note that a lower value means a higher spread.

What kind of message do you get during GRT? Normally, you can always continue at least to DRT if `GRT_ALLOW_CONGESTION: true`.
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message-1519239408069513297

2026-06-24T07:15:00.987+00:00 — Deepak (@deempak)

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Yes I have iterated  PL_TARGET_DENSITY_PCT  from 30 to 50 but the results were creating same number of overflows ie is around 18 K
The flow does  go to the Detailed routing as   i have kept GRT_ALLOW_CONGESTION: true  but DRT starts with 90K violations and then just keeps on iterating it did went down to 79K but that took 12h .
Then my system killed the process but I think 12h was too much anyway? Or is that normal


I search on internet and found that maybe adding PAD_CELL might help what is you take on that ?
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message-1519240447656984697

2026-06-24T07:19:08.844+00:00 — Leo Moser (mole99) (@mole99)

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You need to lower the value to spread the cells. For example. try `PL_TARGET_DENSITY_PCT: 20`.
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message-1519241265584148491

2026-06-24T07:22:23.853+00:00 — Deepak (@deempak)

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my design utilisation was 27 % so i thought i should keep above that  if that's not the case i will try 20 now
Thank You much
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message-1519241618325115022

2026-06-24T07:23:47.953+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Content

Increasing the target density means a higher routing congestion. Good luck!

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message-1519280217909366815

2026-06-24T09:57:10.811+00:00 — Deepak (@deempak)

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this worked thank you very much
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message-1519280404090064917

2026-06-24T09:57:55.2+00:00 — Leo Moser (mole99) (@mole99)

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That's great to hear!
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message-1519722886246694912

2026-06-25T15:16:11.167+00:00 — Olle (@osvel)

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Is there a better open-source tool than yosys/abc for retiming?
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message-1519723102152556695

2026-06-25T15:17:02.643+00:00 — Olle (@osvel)

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I don't really understand it i guess, it feels like it doesn't work
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message-1521239998467407892

2026-06-29T19:44:38.907+00:00 — Jason Yang (@.pogeg)

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Content

what problem are you encountering?
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message-1521241383191449703

2026-06-29T19:50:09.051+00:00 — Olle (@osvel)

Content

From a software perspective, I guess I assume retiming to be more powerful than it is.

I was under the impression that this should distribute the implementation (booth or whatever) over multiple cycles (i.e, balance the gates):
```verilog
module IntegerMultiply(
  input         clock,
  input  [31:0] inA,
                inB,
  output [31:0] out
);

  reg [31:0] prod_pipe_r0;
  reg [31:0] prod_pipe_r1;
  reg [31:0] prod_pipe_r2;
  reg [31:0] prod_pipe;
  always @(posedge clock) begin
    prod_pipe_r0 <= (inA * inB);
    prod_pipe_r1 <= prod_pipe_r0;
    prod_pipe_r2 <= prod_pipe_r1;
    prod_pipe <= prod_pipe_r2;
  end
  assign out = prod_pipe;
endmodule
```
This is for an ASIC, using abc (not abc9)
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message-1521248657754685450

2026-06-29T20:19:03.442+00:00 — tnt (@246tnt)

Content

Is retiming even enabled by default in the flow ?
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message-1521269326542536764

2026-06-29T21:41:11.265+00:00 — RebelMike (@rebelmike)

Content

I'm fairly sure retiming doesn't happen in the Librelane flow.  Though interestingly `retime` is passed to ABC.
I found this in a search: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/discussions/1782#discussioncomment-8264228 which suggests ABC only sees combinational logic.  Which is possibly why you always see the error `ABC: Error: The network is combinational.`
But clearly yosys *can* do retiming because it works on some FPGA flows - I guess if you wanted to investigate further you could compare the synth scripts for an FPGA and librelane
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message-1521271913056440571

2026-06-29T21:51:27.938+00:00 — Olle (@osvel)

Content

Interesting. I'm pretty sure I got it to work at least once. I have done so many experiments so I feel a bit lost, but iirc retiming worked well until i added input/output delays in my .sbc file. I'll do some more experiments tomorrow and update.
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message-1521329070275825845

2026-06-30T01:38:35.281+00:00 — Lofty (@ravenslofty)

Reply/reference

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(it doesn't work very well though, because it retimes after mapping LUTs, not during mapping LUTs)
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message-1522328052124614696

2026-07-02T19:48:11.114+00:00 — Deepak (@deempak)

Content

In my design while i was checking out the numbers  I found that  fanout/design repair is  using dlyb_1 as for ordinary buffer is the what's suppose to happen ?

These are being added by the repair_design command in the flow
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message-1522489365903704094

2026-07-03T06:29:11.316+00:00 — Leo Moser (mole99) (@mole99)

Reply/reference

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Unfortunately, OpenROAD does not currently differentiate between data and hold buffers during buffer selection: https://github.com/The-OpenROAD-Project/OpenROAD/issues/10622

While you can disable all delay buffers, this would also mean that they could not be used for hold repair.
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message-1522489490579390545

2026-07-03T06:29:41.041+00:00 — Leo Moser (mole99) (@mole99)

Content

@RebelMike did a workaround for his design where he replaced all setup-repair dlyb with normal buffers iirc.
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message-1522563238020251749

2026-07-03T11:22:43.801+00:00 — RebelMike (@rebelmike)

Content

Yes, I used the foundry cell library for my TT design and it had this issue. I wrote a quick librelane plugin to fix it that’s linked from here https://github.com/librelane/librelane/issues/967
you can see how I injected it into the config here: https://github.com/MichaelBell/ttgf0p3-tinyQV/blob/c02a42568e2f9dcf6b6ba6f78fe7b5f818b97e76/src/config.json#L73 (will need converting to yaml)
And then I think you just need that plugin on the PYTHONPATH and it should work

Embeds

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message-1522889142571110550

2026-07-04T08:57:45.501+00:00 — Deepak (@deempak)

Reply/reference

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Content

ohh ok I tried to disable the delay cells this but the hold timing got bad so
I will check the work around


Btw would it effect the tapeout if the dlyb buffers are used instead of normal buffer ?
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message-1522889605437722644

2026-07-04T08:59:35.857+00:00 — Leo Moser (mole99) (@mole99)

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As long as STA says that you meet your timing requirements, then it should be fine even with dlyb.
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message-1522889815694245958

2026-07-04T09:00:25.986+00:00 — Deepak (@deempak)

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yup the STA is fine , Then i guess i will let it be

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message-1524843942414258308

2026-07-09T18:25:26.102+00:00 — J-Lo (@crockpotveggies)

Content

Anyone here have full SOC designs and having issues with very long synthesis times? Our same design for fpga on vivado takes 15-30 minutes to synth, but on yosys we’re seeing 12+ hours despite enabling multi threading and other usual suspects. Is this a known issue?

I opened a PR with yosys to merge some optimizations and it was rejected because it was “AI assisted” and I must admit the attitude was very disappointing despite providing follow ups, asking questions, etc.
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message-1524856883540787374

2026-07-09T19:16:51.507+00:00 — tnt (@246tnt)

Content

That's usually a sign you have synthesized memories or something like that
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message-1524870010470666372

2026-07-09T20:09:01.211+00:00 — Leo Moser (mole99) (@mole99)

Content

@J-Lo If you haven't read this page yet, you should do so before contributing to Yosys: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/contributing.html
There are also some rules on LLM usage.
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message-1524870188107960362

2026-07-09T20:09:43.563+00:00 — Leo Moser (mole99) (@mole99)

Content

Often you can also speed up synthesis by keeping some parts of your design hierarchical.
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message-1524874006069645355

2026-07-09T20:24:53.836+00:00 — J-Lo (@crockpotveggies)

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Yes we do leverage the keep_hierarchy. I’m aware of the LLM rules but frankly it felt like an aversion not a guardrail. But I’m not keen to focus this discussion on that, I’m trying to understand if our synth times are abnormal and if we need to investigate a problem
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message-1524929309234561034

2026-07-10T00:04:39.138+00:00 — bailey (@bailey8889)

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Just to be clear, you're referring to the actual yosys synthesis step and not the any of the place and routing steps, right?
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message-1525195541640904715

2026-07-10T17:42:33.89+00:00 — J-Lo (@crockpotveggies)

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This is a summary from my team, and because I’m seeing openroad yes it might be PNR

> synthesis/signoff runs were spending huge time in OpenROAD.RepairDesignPostGPL. The dominant cause was a massive high-fanout reset net: i_chip_core.rst_n had about 38,354 terminals, and OpenROAD was serially building buffer trees for it. LibreLane parallelism knobs do not help this step much.
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message-1525199343571959878

2026-07-10T17:57:40.341+00:00 — bailey (@bailey8889)

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Place and route runtimes are highly dependent on routing areas. Placing macros too close together or too close to the edges can result in unroutable designs.
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message-1525199705578143906

2026-07-10T17:59:06.65+00:00 — J-Lo (@crockpotveggies)

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Thanks we do have an SRAM macro in there and I wonder if that’s what’s causing some of our issues. I will note it is routable and we get a GDS, it just takes an obscenely long time to create
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message-1525200022377861403

2026-07-10T18:00:22.181+00:00 — bailey (@bailey8889)

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Do you see any obvious congestion in the gds?
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message-1525202114081456219

2026-07-10T18:08:40.882+00:00 — J-Lo (@crockpotveggies)

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Waiting for a file transfer of the final report but in summary I think you’re on to something, probably to do with the SRAM macro:

>     Dense SRAM macro grid. The current report has 39 SRAM macros consuming 4.48365 mm²; total core payload is 8.23514 / 12.90200 mm², about 64% including macros. In macros_3v3.yaml⁠, SRAM columns at x=1040 and x=1380 are only about 38.7 µm apart after subtracting the 301.3 µm SRAM width.

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message-1525202996814807070

2026-07-10T18:12:11.342+00:00 — J-Lo (@crockpotveggies)

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I’m not sure how solvable this problem is with such a short time until tape out. I think it’s just a challenge posed by the small chip area and requirement to have an SRAM
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message-1525413788700905582

2026-07-11T08:09:48.044+00:00 — Leo Moser (mole99) (@mole99)

Content

Have you had a look at your design through the OpenROAD GUI yet?
If you send a screenshot, people might be able to help you.

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message-1526175407458619414

2026-07-13T10:36:12.106+00:00 — Deepak (@deempak)

Content

Hello  I was just doing final check up on the design and show that rst_n_pad is neither pu or pd is that normal or i can pull it down ? is there a reason for it being so ?
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message-1526176026550468648

2026-07-13T10:38:39.709+00:00 — Deepak (@deempak)

Content

As i have pulled up my cs_n pin for my input spi  in the design so if there is some issue with that i should change that
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message-1526177320292061265

2026-07-13T10:43:48.161+00:00 — RebelMike (@rebelmike)

Content

I don't see why there would be any issue using the pull up/down, it's just not used by default in the template

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message-1526178276727459860

2026-07-13T10:47:36.193+00:00 — Deepak (@deempak)

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Alright then thank you
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message-1526316013908660295

2026-07-13T19:54:55.296+00:00 — Essen (@essen__)

Content

Could a kind soul tell me if I am misunderstanding this ?
The IO pins have an input capacitance (driven from outside the pad) of:
- bidir : 3.635930 (pf)
- input: 3.247814 (pf)
And since the `max_capacitance` STA check does a blanket check of all max capacitance above a 0.2pf threshold they get incorrectly flagged even though this is perfectly handled ?
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message-1526316294465654884

2026-07-13T19:56:02.186+00:00 — RRichmondR (@rrichmondr)

Content

Hello everyone, we got our design routed with synopsys, we will place that gds into the padframe.

We have one question, the exported gds has the std cells as lef (only metals not any comp, active, etc)
is this correct ? or should we see on klayout the std cells with all the parts, comp, active etc
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message-1526320100481699910

2026-07-13T20:11:09.611+00:00 — namibj

Reply/reference

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The latter.

Have you tried scrolling the right of the two number pickers on the left panel ?
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message-1526334033234235464

2026-07-13T21:06:31.438+00:00 — RRichmondR (@rrichmondr)

Content

we tried to increase number, but it doenst show the layers (in the layer viewer on the right the comp, dnwell etc do not appear)
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message-1526338758687985704

2026-07-13T21:25:18.074+00:00 — namibj

Reply/reference

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Ok, just making sure.
It should be easy to get Klayout to fill in the blanks btw.; I just don't know for lack of experience.
I'd suggest trying it's LEF import wizard and making sure all the relevant .GDS with the used cells are provided/listed for the wizard to pull from when materializing the LEF.
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message-1526394961782767727

2026-07-14T01:08:37.936+00:00 — namibj

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message-1526394964169461780

2026-07-14T01:08:38.505+00:00 — namibj

Content

so.... well.... yeah.
Figure if the column multiplexer circuity can also be sufficciently squished, it'd be desirable to tape out at least a smol single block of it to hopefully have the denser (though possibly slightly slower, I think) variant silicon-proven before the Run3 deadline.
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message-1526468766697914499

2026-07-14T06:01:54.399+00:00 — EmbeddedKen (@embeddedken)

Content

In OpenROAD, is there a good way to enforce hierarchical placement within a bounding box?
I'm using plenty of macros, but directing soft placement would be helpful to fix routing congestion.
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message-1526469522385539104

2026-07-14T06:04:54.569+00:00 — EmbeddedKen (@embeddedken)

Content

AI mentions commands like "create_region" "add_to_region" and "report_region", but I haven't found any documentation for these.
Is it an AI hallucination?
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message-1526473475265658981

2026-07-14T06:20:37.009+00:00 — Leo Moser (mole99) (@mole99)

Content

I would suggest to check out the LibreLane step configuration variables: https://librelane.readthedocs.io/en/stable/reference/step_config_vars.html

You can place hard and soft obstructions using `FP_OBSTRUCTIONS` and `PL_SOFT_OBSTRUCTIONS`.
And you can also limit the routing amd PDN generation using `ROUTING_OBSTRUCTIONS` and `PDN_OBSTRUCTIONS`.
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message-1526474140909961267

2026-07-14T06:23:15.711+00:00 — tnt (@246tnt)

Content

AFAIU he wants to manually place/contraint some RTL hierarchy sub level to a given location, so I don't think those will help
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message-1526475357920694292

2026-07-14T06:28:05.869+00:00 — Leo Moser (mole99) (@mole99)

Content

Oh, I missed the *hierarchical*! Yes, I wouldn't know either, unless by using macros as he already does.
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message-1526486649679122563

2026-07-14T07:12:58.034+00:00 — EmbeddedKen (@embeddedken)

Content

For FPGAs, you can often softly hint or enforce cell placement of an instance and all of its children within rectangular or polygonal boundary constraints.
You can usually control whether foreign cells are excluded from place/routing through these blocks.
Xilinx terminology is "pblock", Altera "logic lock"

Normally every time you re-implement the design, each region is replaced/routed; but you can also lock the placement and routing as well, effectively more like a macro here. Would be good if these tools implemented softer hierarchical placement. I bet commercial ASIC tools have a direct equivalent.
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message-1526526755018375233

2026-07-14T09:52:19.892+00:00 — Leo Moser (mole99) (@mole99)

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Started a thread.
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message-1527365136510095421

2026-07-16T17:23:45.616+00:00 — Deepak (@deempak)

Content

How does one find the total number of transistors that are used in  design?
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message-1527367654309101730

2026-07-16T17:33:45.906+00:00 — Essen (@essen__)

Reply/reference

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transistors or cells ?
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message-1527368541094019113

2026-07-16T17:37:17.332+00:00 — Deepak (@deempak)

Content

Transistors 🥲
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message-1527371916669751416

2026-07-16T17:50:42.132+00:00 — Essen (@essen__)

Reply/reference

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Ouf, well you could go count the transistors per cells+macro by looking at the floorplans and then multiply that per each of the cells+macos you have. But that sounds tedious.
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message-1527372170760556728

2026-07-16T17:51:42.712+00:00 — Essen (@essen__)

Content

Maybe the antenna check could inspire a better way of doing this 🤔
Anyways, I don't have any good solutions for you.
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message-1527372889307877596

2026-07-16T17:54:34.027+00:00 — RebelMike (@rebelmike)

Content

The spice for the cells is probably an easier way to count
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message-1527373334684368926

2026-07-16T17:56:20.213+00:00 — RebelMike (@rebelmike)

Content

You/AI could probably write a script to count the number of fets in each cell subcircuit in the spice file for the standard cell library you are using, and then mutliply it by the cell counts.

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message-1527373752034394162

2026-07-16T17:57:59.717+00:00 — Essen (@essen__)

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Right, why did I not think of using the spice circuit equivalence ! Obviously 🙌
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message-1527373957894766744

2026-07-16T17:58:48.798+00:00 — RebelMike (@rebelmike)

Content

Although you might need a similar trick to get the final counts of each cell - yosys logs what it sythnthesized, but then lots of buffers will be added, I'm not sure if there's a final log anywhere or if you'll need to count that from the netlist
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message-1527374029839929474

2026-07-16T17:59:05.951+00:00 — namibj

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Extract LVS; grep count by lines starting with M[digit]
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message-1527374057354297465

2026-07-16T17:59:12.511+00:00 — namibj

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(if flattened)
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message-1527374273856143561

2026-07-16T18:00:04.129+00:00 — namibj

Content

Question will possibly be how it distinguishes fingers

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message-1527377046941073509

2026-07-16T18:11:05.284+00:00 — Deepak (@deempak)

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yeah that seems like a good use of AI 😄
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message-1527377159021400194

2026-07-16T18:11:32.006+00:00 — Deepak (@deempak)

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sure let me try it thank you
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message-1527417597333606431

2026-07-16T20:52:13.251+00:00 — tnt (@246tnt)

Content

But what do you count as a transistor ?  Does a 2 finger nmos count as 1 or 2 ?
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message-1527422187076714537

2026-07-16T21:10:27.531+00:00 — Essen (@essen__)

Content

global placement in action on a 0.5x0.5 slot:

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message-1527476126174285934

2026-07-17T00:44:47.614+00:00 — bailey (@bailey8889)

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CVC-RV will report the total number of devices and number of each device type in the equivalent flattened netlist, but it uses an extracted version that has parallel devices combined. I can help you with the setup if you want.
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message-1527580258159824897

2026-07-17T07:38:34.614+00:00 — Deepak (@deempak)

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aah not sure, i just curious about checking how many fet are even there in my design
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message-1527580380151156856

2026-07-17T07:39:03.699+00:00 — Deepak (@deempak)

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that would be great if  you will can

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message-1527830920781103166

2026-07-18T00:14:37.24+00:00 — Tim 'mithro' Ansell (@mithro_)

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These animations are always fun to look at!

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message-1530682525775822878

2026-07-25T21:05:52.851+00:00 — were491 (@were491.)

Content

fungal growth as my professor would call it

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message-1536400259402571847

2026-08-10T15:46:06.778+00:00 — djsftree

Content

any merit in powering sram vertically ?
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message-1536500569475391498

2026-08-10T22:24:42.563+00:00 — djsftree

Content

https://agentdavo.github.io/GDS3D/sram_article.html
<details> <summary>Other message metadata</summary>
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