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Thread: KianV PCB HelpCenter

21 Discord messages from 📐 - Designing/📦-cob/threads/kianv-pcb-helpcenter.md.

Category: 📐 - Designing Parent channel: #📦-cob Thread ID: 1451249444896112834

Messages: 21

message-1451250767582203925

2025-12-18T16:32:25.927+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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message-1451250772296728788

2025-12-18T16:32:27.051+00:00 — asic destroyer (@logic_destroyer)

Content

@GoranMahovlic
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message-1451254351275360507

2025-12-18T16:46:40.346+00:00 — asic destroyer (@logic_destroyer)

Content

The asic/sdram operates at 30 MHz
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message-1451254404111143097

2025-12-18T16:46:52.943+00:00 — asic destroyer (@logic_destroyer)

Content

isn't critical - I think
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message-1451312213305594037

2025-12-18T20:36:35.729+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@asic destroyer - I've done 720p60 over pin headers for HDMI - that is like 750MHz signals....

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message-1451317944373215374

2025-12-18T20:59:22.122+00:00 — asic destroyer (@logic_destroyer)

Content

Changed the channel name: KianV PCB HelpCenter
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message-1451319104391614634

2025-12-18T21:03:58.692+00:00 — asic destroyer (@logic_destroyer)

Content

@RebelMike   My question was: should I place the SDRAM on the bottom side or on the same side (top)? The connector is giving me a headache, because it forces a lot of distance to the SDRAM and the rat’s nest looks kind of weird. I’m planning a 4-layer board, and my reference is a Machdyne “Kuchen” board.
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message-1451319471431221248

2025-12-18T21:05:26.201+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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message-1451319514062131313

2025-12-18T21:05:36.365+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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message-1451319549051015339

2025-12-18T21:05:44.707+00:00 — asic destroyer (@logic_destroyer)

Reply/reference

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message-1451319917432537111

2025-12-18T21:07:12.536+00:00 — asic destroyer (@logic_destroyer)

Content

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message-1451320013192696040

2025-12-18T21:07:35.367+00:00 — asic destroyer (@logic_destroyer)

Content

@RebelMike I hope it's now clear
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message-1451326102827171861

2025-12-18T21:31:47.249+00:00 — RebelMike (@rebelmike)

Content

I haven't started looking at this connector yet, but I would expect there to be plenty of space for the RAM chip under the board so you don't need to push it out away from the connector
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message-1451326689245134889

2025-12-18T21:34:07.062+00:00 — RebelMike (@rebelmike)

Content

The amount of crossing isn't ideal (I guess in an ideal world we'd have considered the connector pinout and eventual host PCB when choosing the pin assignment for the ASIC, but I certainly didn't do that).  But if you do mostly vertical on one layer and horizontal on another it'll probably work out ok.

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message-1451329136403677458

2025-12-18T21:43:50.51+00:00 — asic destroyer (@logic_destroyer)

Content

Unfortunately I also focused only on the ASIC and only today I realized what the impact on the connector/PCB is… I’ll work with two sides and a 4-layer stackup… Do you have any ideas for the clock frequency generator—can you recommend something? I don’t want an MCU on the board.
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message-1451333473691369532

2025-12-18T22:01:04.6+00:00 — asic destroyer (@logic_destroyer)

Content

I’ll work with the top and bottom side. Thank you.
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message-1451336602843611178

2025-12-18T22:13:30.648+00:00 — RebelMike (@rebelmike)

Content

I'm no expert, but maybe an SN74LVC1GX04 and an appropriate crystal

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message-1451343162722488503

2025-12-18T22:39:34.645+00:00 — asic destroyer (@logic_destroyer)

Content

I forgot to mention that I have 300× CH32V003. We could use one as a clock generator
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message-1451343457732919489

2025-12-18T22:40:44.981+00:00 — asic destroyer (@logic_destroyer)

Content

https://de.aliexpress.com/item/1005005036714708.html
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message-1451345977507057705

2025-12-18T22:50:45.742+00:00 — asic destroyer (@logic_destroyer)

Content

Seems not ideal 🙁
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message-1451346451262083103

2025-12-18T22:52:38.694+00:00 — asic destroyer (@logic_destroyer)

Content

cmos 4-pin xo with socket seems a good solution
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