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Thread: CoB PCB (0.5x0.5 focus) 🧵

42 Discord messages from 📐 - Designing/📦-cob/threads/cob-pcb-05x05-focus.md.

Category: 📐 - Designing Parent channel: #📦-cob Thread ID: 1536016039236604055

Messages: 42

message-1536018773042008064

2026-08-09T14:30:13.342+00:00 — Essen (@essen__)

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message-1536018778230493275

2026-08-09T14:30:14.579+00:00 — Essen (@essen__)

Content

Change from previous PCBs:
- No vias or though holes in enclosed area (under the epoxy glob)
- Made pins on the mezzanine longer, bumped to `0.8` mm to help SMD soldering, we might want to make this even longer. The coordinates of the mezzanine footprint pins have not changed so this change should have no effect for the pick-and-pace.

No changes:
- part positions: mezzanine, die footprint and SMD capacitors are all at exactly the same place

Things we might want to change:
- No fill zone in the encapsulation region

Things I want to change:
- constant bonding wire length from die to finger
- more gradual angle changes in bonder trajectory (seem to not handle abrusc transitions very well, see corners )
- length match signal wire or at least attempt to have them closer in cumulative length.
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message-1536019333887561739

2026-08-09T14:32:27.058+00:00 — tnt (@246tnt)

Content

Watchout elongating pins like that because for automated assembly that means more paste and could end up bridging.
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message-1536020537971703899

2026-08-09T14:37:14.134+00:00 — Essen (@essen__)

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Content

Very good point. 🤔
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message-1536022139960954950

2026-08-09T14:43:36.078+00:00 — Essen (@essen__)

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Content

Think the extra `0.14` mm puts us at risk ?
Because, my thinking is we want more paste to prevent the pins disconnecting from the mezzanine, but also want to prevent shorts.
If the answer is yes, I will revert not questions asked.
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message-1536022309691858945

2026-08-09T14:44:16.545+00:00 — tnt (@246tnt)

Content

I have no idea, I usually just follow the vendor recommended footprint and assume they did their homework 😅
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message-1536022432308134028

2026-08-09T14:44:45.779+00:00 — tnt (@246tnt)

Content

but 0.14mm seem unlikely to make much of a difference
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message-1536022897561436251

2026-08-09T14:46:36.704+00:00 — Essen (@essen__)

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Thanks, off to read the datasheet then 🫡
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message-1536024019466321960

2026-08-09T14:51:04.187+00:00 — Essen (@essen__)

Content

I also really wondering when the mezannines disconnected.
Because they might have done so during the "reflow" step in the packaging house and have been perfectly fine when JLC delivered them.
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message-1536024543087304814

2026-08-09T14:53:09.028+00:00 — tnt (@246tnt)

Content

Do we have microscope shots of the failure ?
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message-1536024961917919352

2026-08-09T14:54:48.885+00:00 — Essen (@essen__)

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Don't know, but this is what I have (was shared https://discord.com/channels/1361349522684510449/1408134567491145728/1515658100030312499 )

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message-1536025226284892501

2026-08-09T14:55:51.915+00:00 — tnt (@246tnt)

Content

The pins are still gold, they never wetted and they're bent.
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message-1536025293956055100

2026-08-09T14:56:08.049+00:00 — tnt (@246tnt)

Content

The  connectors were damaged before soldering.

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message-1536025389745307669

2026-08-09T14:56:30.887+00:00 — Essen (@essen__)

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Thanks, you are a badass tnt 💪
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message-1536031299574435862

2026-08-09T15:19:59.9+00:00 — RebelMike (@rebelmike)

Content

Potentially some vias near the pads should be moved back a bit if the goal is to have none under the epoxy.

That might be easier if you move to something more similar to the pad frame you posted in the TT discord.
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message-1536031875078951013

2026-08-09T15:22:17.111+00:00 — RebelMike (@rebelmike)

Content

I suspect it will be difficult to make the larger dies work with no vias inside the pad ring, although reducing the size of the pads should give you a bit more space
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message-1536032509932871741

2026-08-09T15:24:48.472+00:00 — namibj

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oh yeah, if they're assembled by JLCPCB do take the footprints they have on their easyeda for the part, at least drawing-wise
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message-1536033051744669736

2026-08-09T15:26:57.65+00:00 — Essen (@essen__)

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It defiantly will but my current plan is to first see if I can get these changes approved before taking such a departure. For clarity of reading he is referencing to my automatic CoB footprint generator  (https://discord.com/channels/1009193568256135208/1009193776155205696/1535851539502075936).

I will move the vias further out 🫡
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message-1536033191155081336

2026-08-09T15:27:30.888+00:00 — namibj

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I have a feeling it might be better to have the PCB-side bond pads not be as wide in favor of them being allowed closer; after all, the machien does reliably hit the far smaller passivation openings on the dies....

Unless that means the die would need to be aligned accurately enough to the die ahead of the wire bonding machine getting it's turn; AFAIK that's a premium offer of the factory (alignment by machine to be substantially more precise)

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message-1536033565819801730

2026-08-09T15:29:00.215+00:00 — Essen (@essen__)

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Difficult for sure, but I don't think it will be impossible, they use 4 layers PCBs unlike the 2 layers here, I think I can make it work.
Also, I have no intention of modifying the pad sizes. The pads where just bigger on the test I posted, it was just a trial run for the algo.
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message-1536033727526998146

2026-08-09T15:29:38.769+00:00 — namibj

Content

anyways, go have fun, best luck to ya!

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message-1536033819042517022

2026-08-09T15:30:00.588+00:00 — Essen (@essen__)

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I think the issue there might be JLC's requirements for wire width.
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message-1536034133644415006

2026-08-09T15:31:15.595+00:00 — namibj

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I'm literally basing it on the spacing between pads; and the trace width I see between the vias and the pads, on the red layer here: https://discord.com/channels/1361349522684510449/1408134567491145728/1536016323061223484

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message-1536060160110366751

2026-08-09T17:14:40.788+00:00 — Essen (@essen__)

Content

Mezzanine footprint:
Assuming connector is : https://www.lcsc.com/product-detail/C19089236.html?spm=wm.fly.bg.1.xh&lcsc_vid=QwRcU1cHRFULBFdQRFgIVVxQQQJWUVYHRAMNVlJQRAAxVlNeQVNXUlRTT1lfVTsOAxUeFF5JWBYZEEoKFBINSQcJGk4eFQsCAgIaSgADAwAHC0slRlheX11UTlNADxALGw%3D%3D

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message-1536060582791487579

2026-08-09T17:16:21.563+00:00 — Essen (@essen__)

Content

The default mezannine is perfectly inline with the datasheet
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message-1536072712877908028

2026-08-09T18:04:33.601+00:00 — Essen (@essen__)

Content

Updated layout, moved via on left side further away

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message-1536073067154116783

2026-08-09T18:05:58.067+00:00 — Essen (@essen__)

Content

DRC is clear
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message-1536078107159822477

2026-08-09T18:25:59.698+00:00 — RebelMike (@rebelmike)

Content

Looks good, though where have all the ground vias gone?
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message-1536131794997350410

2026-08-09T21:59:19.876+00:00 — namibj

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I did not say the datasheet foorprint, I meant the foorprint they drew for their easyeda CAD which has in that process been greenlit by their engineers for production usage on their PCBA process.
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message-1536131907761209394

2026-08-09T21:59:46.761+00:00 — namibj

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"who needs ground vias"
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message-1536141705974128710

2026-08-09T22:38:42.837+00:00 — Essen (@essen__)

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Oups, thanks for catching that, might have gone a bit to far in my removing them, let me add some back
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message-1536160048177225838

2026-08-09T23:51:35.959+00:00 — Tim 'mithro' Ansell (@mithro_)

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4 layer PCBs are almost the same cost as 2 layer PCBs in my experience.
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message-1536160350330822686

2026-08-09T23:52:47.998+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Essen - if you want to be really fancy, you should work out how to draw the bond wires in 3d between the pads on the ICs and the PCB pads.
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message-1536160544665636865

2026-08-09T23:53:34.331+00:00 — Tim 'mithro' Ansell (@mithro_)

Content

@Essen - there are a whole bunch of academic papers about the pathway the bond machine is supposed to follow for good bonds.
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message-1536185390359117845

2026-08-10T01:32:18.006+00:00 — Essen (@essen__)

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Bring on the papers: if you have any to recommend I will read them.
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message-1536186486280421458

2026-08-10T01:36:39.294+00:00 — Essen (@essen__)

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Haha, that is much too fancy for me, I am a simple girl. I just deal in expensive crystals.
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message-1536203916235247686

2026-08-10T02:45:54.919+00:00 — Essen (@essen__)

Content

Gnd via's re-added.

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message-1536205308119220235

2026-08-10T02:51:26.77+00:00 — Essen (@essen__)

Content

undid change on mezannine connectors: back to default 0.66mm
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message-1536249923618476032

2026-08-10T05:48:43.934+00:00 — tnt (@246tnt)

Content

But your ground is terrible ... look at the path it needs to take to go from a ground pin to the connector ... in theory that should be like your best/shortest path.
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message-1536413839879569418

2026-08-10T16:40:04.616+00:00 — Essen (@essen__)

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Less wimpy gnd, does this look passable for you @tnt ?

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message-1536418124830875830

2026-08-10T16:57:06.228+00:00 — Essen (@essen__)

Content

gnd vias an filling added back :

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message-1536502461529980928

2026-08-10T22:32:13.664+00:00 — namibj

Content

I think it'd be good to have industry experience guided input on whether and if so, how, PTH/via structures (notably, with what possibly constraints on covering/tenting) are ok/problematic to have under the bond wires in the glob coverage zone.

I'm _pretty sure_ the observed bubbling was from COBs that had fairly narrow top-open bottom-closed holes there; I would not be surprised if in practice those (and huge openings that easily drip glob material) are the only problematic hole types to have under the glob.
And a spam of gnd vias at the central north and south would be much better than these 4 isolated ones, especially for acting as the EM wave return path of the IO connections which for just that IIRC doesn't even need the die's own ground bonds to be as numerous.
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