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Thread: IO ESD

9 Discord messages from 📐 - Designing/🕰️-analog/threads/io-esd.md.

Category: 📐 - Designing Parent channel: #🕰️-analog Thread ID: 1534564700904226986

Messages: 9

message-1534567405492109392

2026-08-05T14:23:00.353+00:00 — tnt (@246tnt)

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message-1534567412681408664

2026-08-05T14:23:02.067+00:00 — tnt (@246tnt)

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Ok, there are some small diodes on the input path after the resistor. But still, the main clamp are the actual drive transistors AFAICT.
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message-1534570915252408443

2026-08-05T14:36:57.145+00:00 — Brunny (@brunny95)

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The small diodes are standard (from what I've seen). Usually the path is: ESD main protections (GT mos or similar) - resistor - "small diodes" - core of the circuit
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message-1534571111357091971

2026-08-05T14:37:43.9+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

Content

If properly designed output drivers can indeed also be used as ESD protection. This is using the so-called snap-back behavior. I believe [this](https://siliconvlsi.com/explain-the-snapback-phenomenon-in-nmos-devices/) should explain something. I used 0.18um TSMC when @imec and both IO NMOS and PMOS were designed to have that capability.

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message-1534571909847580734

2026-08-05T14:40:54.275+00:00 — Chips4Makers aka Staf Verhaegen (@chips4makers)

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Content

It is known to me as secondary protection and the purpose is to get some extra voltage drop over the resistance during an ESD event to protect the connected gates.
The diode also has a capacitance so the R-C acts as a low-pass filter on the input though so high frequency stuff typically needs IO with custom ESD protection.
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message-1534572435775422515

2026-08-05T14:42:59.666+00:00 — tnt (@246tnt)

Content

Tx both, yeah I knew the secondary protection thing. But never heard of snapback.
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message-1534680256223645878

2026-08-05T21:51:26.064+00:00 — Leo Moser (mole99) (@mole99)

Content

Here are the ESD guidelines from the PDK: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_14_4.html
It seems like the snapback behavior is indeed used for ESD protection.
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message-1535352491695276072

2026-08-07T18:22:39.49+00:00 — namibj

Content

There are ESD implants available specifically only for thick oxide area's sd-diffusion.
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message-1535353672127746128

2026-08-07T18:27:20.927+00:00 — namibj

Content

There's also a trick were you employ something like a gate-triggered TRIAC that's constructed to bascially experience a safe and depending on details maybe or maybe-not power-cycle-requiring latchup to clamp the ESD voltage below what a passive diodes-to-PDN-rails arrangement could do, to be useful whenever thin-oxide devices are used to interact with pads.

An example that comes to mind would be e.g. DDR3 which is nominally 1.5V and fairly intense on the IO power draw due to combination of frequency, receive-side-termination, and ofc sheer wire count.
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