Category: π - Designing
Parent channel: #π°οΈ-analog
Thread ID: 1510747067734036540
Messages: 11
message-1510781231346749550
2026-05-31T23:05:14.511+00:00 β Thomas Dexter (@tdextrous)
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</details>message-1510781246588981350
2026-05-31T23:05:18.145+00:00 β Thomas Dexter (@tdextrous)
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661042976646103116 - Nickname: Thomas Dexter
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Content
Could use a resistor connecting vdd to a mos diode, or a widlar source.
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</details>message-1510891971055452242
2026-06-01T06:25:16.915+00:00 β tnt (@246tnt)
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Content
That's what I usually do but I was hoping for something with a bit less Vdd dependence ...
Here say I make by 30 uA at 3.3V nominal. Voltage across nmos will be say ~ 1.5V so I have R = (3.3 - 1.5) / 30u = ~ 60k. When going to 5V, the 1.5V drop is much less significant so I have 3.5V across resistor and not 1.8V anymore and I go to 58 uA. Simulating it's actually a bit worse than that and then if you had corners, you go even more off.
So I was hoping for something that at least reduces the Vdd dependence somewha.t
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</details>message-1510892417488912516
2026-06-01T06:27:03.353+00:00 β tnt (@246tnt)
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And AFAICT the widlar source does nothing to help that.
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</details>message-1510932836671291432
2026-06-01T09:07:40.037+00:00 β tnt (@246tnt)
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</details>message-1510932877267697685
2026-06-01T09:07:49.716+00:00 β tnt (@246tnt)
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That's what I think I'll end up with.
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</details>message-1510932978145165423
2026-06-01T09:08:13.767+00:00 β tnt (@246tnt)
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Bigger that I would have liked, but should be decent enough.
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</details>message-1510939985954734151
2026-06-01T09:36:04.559+00:00 β tnt (@246tnt)
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or actually might use the same topology but in nmos, makes it a bit smaller.
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</details>message-1511005421027197071
2026-06-01T13:56:05.496+00:00 β namibj
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262706220073222144 - Nickname: namibj
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Stack mos diodes; tap resistor off that intermediate into a current mirror? You have headroom at these Vdd's
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</details>message-1511009306596610139
2026-06-01T14:11:31.888+00:00 β tnt (@246tnt)
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Content
Problem is solved. The above works.
This is a temp sweep from 15C to 50C (realistic operating range) with VDD from 3 to 5. Typical corner. And this goes from 31uA to 37uA.
Sweeping across all transitor and resistor corners and vdd and temp, I get from 22uA to 55uA which is good enough for this application.
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</details>message-1511010195319296100
2026-06-01T14:15:03.776+00:00 β namibj
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Yay
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