---
page_id: wsd-standard-voltage-sram-macros-6762b13f
type: context-page
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template_id: discord-page
template_version: template-0.1.0
title: "Thread: Standard Voltage & SRAM Macros"
slug: wsd-standard-voltage-sram-macros-6762b13f
route: /evidence/i-information/questions/threads/standard-voltage-sram-macros
section: reference
access: public
summary: 24 Discord messages from ℹ️ - Information/⁉️-questions/threads/standard-voltage-sram-macros.md.
status: published
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md_url: /evidence/i-information/questions/threads/standard-voltage-sram-macros.md
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tags: [discord, wafer-space, archive]
last_updated: 2026-08-19
talk_url: /evidence/i-information/questions/threads/standard-voltage-sram-macros.talk.md
talk_route: /evidence/i-information/questions/threads/standard-voltage-sram-macros/talk
---
# Thread: Standard Voltage & SRAM Macros
Category: **ℹ️ - Information**
Parent channel: **#⁉️-questions**
Thread ID: `1532458465379750028`
Messages: **24**
## message-1532458465379750028
**2026-07-30T18:42:49.848+00:00 — Florian S. (@fstolz95)**
- Message ID: `1532458465379750028`
- Author ID: `919250960944078938`
- Nickname: Florian S.
- User name: fstolz95
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532458465379750028
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
Hi, I am currently preparing a university lab course where we will hopefully target and tapeout on wafer.space. I noticed that the provided PDK seems to be both 5V or 3.3V. I do not have any real preference here, but if I download the project template and simply paste in my verilog will it generate a 5V or a 3.3V design? A bit unrelated to this: Are any of the SRAM macros silicon proven?
Thanks 🙂
```
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---
## message-1532464097570848900
**2026-07-30T19:05:12.667+00:00 — Essen (@essen__)**
- Message ID: `1532464097570848900`
- Author ID: `509798510170865675`
- Nickname: Essen
- User name: essen__
- Type: `Reply`
- Edited: 2026-07-30T19:08:09.548+00:00
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532464097570848900
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
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- https://discord.com/channels/1361349522684510449/1532458465379750028/1532458465379750028
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**Content**
```text
The `gf180mcu_ocd_io` SRAM macro targets 3.3V and the `gf180mcu_fd_ip_sram` 5V.
You might be able to use them at different voltages but you will want to check that.
By default template assumes you are working at 5V.
As for if the SRAM has been silicon proven **you will want to confirm** with others but I think the answer is yes.
@Tim Edwards would you be so kind as to confirm that the `gf180mcu_ocd_io` SRAMs you sent out as part of ws1 are working as intended ?
```
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---
## message-1532487223281324042
**2026-07-30T20:37:06.266+00:00 — namibj**
- Message ID: `1532487223281324042`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532487223281324042
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
the foundry SCL works down to 1.8V nominal at a speed penalty, to be clear.
AFAIK there's several of the actually-dense 3v3-transistor-based SRAM configurations on the currently-in-production chips, and the timeline plans are such that they'll be silicon-proven before the deadline for the next Run.
It's therefore IMO reasonable to hedge your plans with a configuration that has less memory configured and have both layouts hardened to just submit the one that's confirmed-superior right before the deadline.
```
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---
## message-1532487799302000960
**2026-07-30T20:39:23.6+00:00 — namibj**
- Message ID: `1532487799302000960`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532487799302000960
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
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**Content**
```text
The SRAM he tested works as expected; harness limitations kept him from pushing the speed at the upper areas of the operating voltage range; tnt posted a matrix of speed vs. voltage but due to speed difficulty reasons that stops at something like 2.5V or maybe 2.8V or so, well shy of the 3.3V.
```
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---
## message-1532487921918017738
**2026-07-30T20:39:52.834+00:00 — namibj**
- Message ID: `1532487921918017738`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532487921918017738
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**Content**
```text
IIRC retention is down to somewhere around 800~1000 mV.
```
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## message-1532489138572628030
**2026-07-30T20:44:42.907+00:00 — Essen (@essen__)**
- Message ID: `1532489138572628030`
- Author ID: `509798510170865675`
- Nickname: Essen
- User name: essen__
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532489138572628030
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
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Nice.
How did I miss that, do you recall where did he post that ?
```
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---
## message-1532490118471090437
**2026-07-30T20:48:36.533+00:00 — namibj**
- Message ID: `1532490118471090437`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532490118471090437
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**Content**
```text
I think TT discord
```
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## message-1532490350688604222
**2026-07-30T20:49:31.898+00:00 — Tim Edwards (@rtimothyedwards_19428)**
- Message ID: `1532490350688604222`
- Author ID: `1365118310701600900`
- Nickname: Tim Edwards
- User name: rtimothyedwards_19428
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532490350688604222
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**Content**
```text
As far as I know, the Tiny Tapeout GF180MCU version still uses the 5V padframe I/O and synthesizes to the original foundry 5V 7-track library. All of the 3.3V stuff has been done on custom chips.
```
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---
## message-1532495140802007233
**2026-07-30T21:08:33.95+00:00 — namibj**
- Message ID: `1532495140802007233`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532495140802007233
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
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**Content**
```text
Yes, but there was some trial entity of the fancy thin oxide sram, or at least one of those thin oxide sram's, which was tested.... IIRC.
Could be confused, could have been something else he had measured there.
There is no thin oxide SCL proven before Run2 dies undergo testing to that extend, and AFAIK there are no structures that had been designed to allow any sort of comprehensive test coverage of the SCL itself to "qualify" it for future production-targeted tapeouts. (Part of why I had hoped to get the e-test design working, but oh well, next tapeout: put an ability to e-test under DC conditions all necessary cells de-embedded to the LEF pins, so that RC extraction and modeling can take it from there to figure out the appropriate content for the liberty specs. AFAIK should work on at least most non-dynamic-logic gates; might have minor complications with flip-flops I guess, unless they work down to visible clock rise times.)
```
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---
## message-1532497704742289599
**2026-07-30T21:18:45.241+00:00 — tnt (@246tnt)**
- Message ID: `1532497704742289599`
- Author ID: `596068704471482370`
- Nickname: tnt
- User name: 246tnt
- Type: `Reply`
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No we use your IOs.
```
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---
## message-1532498215847592026
**2026-07-30T21:20:47.098+00:00 — tnt (@246tnt)**
- Message ID: `1532498215847592026`
- Author ID: `596068704471482370`
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We run both core at 3v3 but separate domains and you can run IO at 5v if you want. Core is 3v3 only. We use the standard foundry 7T and run it at 3v3.
```
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---
## message-1532498337679413343
**2026-07-30T21:21:16.145+00:00 — Florian S. (@fstolz95)**
- Message ID: `1532498337679413343`
- Author ID: `919250960944078938`
- Nickname: Florian S.
- User name: fstolz95
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**Content**
```text
Thanks for the insights 🙂
For simplicity I will probably target 5V. However I am still in the design drafting phase so I don’t know yet if SRAM is required, but as it will probably be processor related having the option of something like a on die SRAM cache sounds interesting 🙂
```
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---
## message-1532498627170275450
**2026-07-30T21:22:25.165+00:00 — tnt (@246tnt)**
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- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
I didn't do any tests on the SRAM ... the shmoo plots I posted are for my sky130 register file , nothing to do with gf180 sram.
```
**Reactions**
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---
## message-1532532591033585814
**2026-07-30T23:37:22.781+00:00 — namibj**
- Message ID: `1532532591033585814`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532532591033585814
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Reply/reference**
- https://discord.com/channels/1361349522684510449/1532458465379750028/1532498627170275450
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```text
ohhhh sorry for confusing the two.
```
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---
## message-1532542813911384075
**2026-07-31T00:18:00.105+00:00 — Tim Edwards (@rtimothyedwards_19428)**
- Message ID: `1532542813911384075`
- Author ID: `1365118310701600900`
- Nickname: Tim Edwards
- User name: rtimothyedwards_19428
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532542813911384075
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
I have the 3.3V SRAM on my desk but I have not done the full test over all bits at different frequencies yet. I did some spot tests and it was reading and writing up to 100MHz, which was the limit of my Analog Discovery 2's pattern generator.
```
**Reactions**
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---
## message-1532682666220978176
**2026-07-31T09:33:43.494+00:00 — Leo Moser (mole99) (@mole99)**
- Message ID: `1532682666220978176`
- Author ID: `323371864074485771`
- Nickname: Leo Moser (mole99)
- User name: mole99
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532682666220978176
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
@Florian S. You can configure the template to use all-3.3V IPs: https://github.com/wafer-space/gf180mcu-project-template#select-different-ip-libraries
This will use Tim's 3.3V SRAMs.
On ws-run2, we also had a few SRAMs generated using Staf's SRAM compiler (ID FS01-FS03): https://github.com/wafer-space/ws-run2
Of course, they still need to be verified once the chips come back :)
```
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---
## message-1532694419164233878
**2026-07-31T10:20:25.614+00:00 — RebelMike (@rebelmike)**
- Message ID: `1532694419164233878`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532694419164233878
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
Maybe a bit of a table describing the capabilities and current state/risk of the different IP libraries would be useful to have somewhere. My understanding:
SCLs:
- gf180mcu_fd_sc_mcu7t5v0 - foundry provided, safe, works at 5V or 3V3. Slow.
- gf180mcu_fd_sc_mcu9t5v0 - foundry provided, safe, works at 5V or 3V3. Faster than 7t but takes more area.
- gf180mcu_as_sc_mcu7t3v3 - community provided, not tested, high risk, works at 3V3 only. Fast.
PADs:
- gf180mcu_fd_io - foundry provided, safe, works at 5V or 3V3 but connects core and IO power domains together.
- gf180mcu_ocd_io - community provided, tested on run 1, low risk, works at 5V or 3V3 but keeps core and IO power domains separate, so you could e.g. run IO at 5V and core at 3V3.
SRAMs:
- gf180mcu_fd_ip_sram - foundry provided, safe, works at 5V or 3V3. 128, 256 and 512 bytes.
- gf180mcu_ocd_ip_sram - community provided, initial testing from run 1 looks good, medium risk, works at 3V3 only. Smaller area. 64, 128, 256, 512 and 1024 bytes.
```
**Reactions**
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---
## message-1532743047828345056
**2026-07-31T13:33:39.591+00:00 — Essen (@essen__)**
- Message ID: `1532743047828345056`
- Author ID: `509798510170865675`
- Nickname: Essen
- User name: essen__
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532743047828345056
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
@RebelMike great post 👍
```
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---
## message-1532766086821576777
**2026-07-31T15:05:12.515+00:00 — namibj**
- Message ID: `1532766086821576777`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532766086821576777
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
AFAIK Staf's SRAM is far superior in density to the others; I'd like to see a comparison table though that at least covers the macro parametrizations supported by the others.
And if there are any additional ones, those that are on Run2 masks without a verilog-level drop-in equivalent in the others.
And then a highlight/marking of all hardened SRAM cells that are taped out in Run1 and those that are merely getting taped out on Run2.
```
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---
## message-1532776575609737447
**2026-07-31T15:46:53.237+00:00 — Essen (@essen__)**
- Message ID: `1532776575609737447`
- Author ID: `509798510170865675`
- Nickname: Essen
- User name: essen__
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532776575609737447
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
@Tim Edwards if you are willing to send me over a board with your ws1 SRAM I can hook up an FPGA to test it over 100MHz.
Alternatively, depending on what FPGA you have I can set you up with the bitstream.
```
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---
## message-1532788544186220676
**2026-07-31T16:34:26.768+00:00 — Tim Edwards (@rtimothyedwards_19428)**
- Message ID: `1532788544186220676`
- Author ID: `1365118310701600900`
- Nickname: Tim Edwards
- User name: rtimothyedwards_19428
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532788544186220676
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
I don't have a "proper" dev board with an FPGA. I used the simple breakout board and an Analog Discovery 2. That didn't have enough digital lines for the job, so I ordered an Analog Discovery 3. There was some snafu at Digilent so by the time I received it, I was busy with other things. Otherwise, it's sitting on my desk all wired up and just waiting to be tested. I would send you parts but right now I have just two working parts and two breakout boards. I think all of the other parts are missing at least one pin critical to getting full functionality.
```
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---
## message-1532789984220680283
**2026-07-31T16:40:10.099+00:00 — Essen (@essen__)**
- Message ID: `1532789984220680283`
- Author ID: `509798510170865675`
- Nickname: Essen
- User name: essen__
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532789984220680283
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Reply/reference**
- https://discord.com/channels/1361349522684510449/1532458465379750028/1532788544186220676
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```text
Thanks for the update.
The FPGA bitstream offer is on the table if you need it in the future.
```
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---
## message-1532847448366514409
**2026-07-31T20:28:30.619+00:00 — namibj**
- Message ID: `1532847448366514409`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532847448366514409
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Reply/reference**
- https://discord.com/channels/1361349522684510449/1532458465379750028/1532789984220680283
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**Content**
```text
Maybe he could give you remote access to the Analog Discovery 3, as I'm guessing it's just a list of pins and whatever information about the power configuration needs explaining?
```
**Reactions**
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---
## message-1532858245222240317
**2026-07-31T21:11:24.79+00:00 — namibj**
- Message ID: `1532858245222240317`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1532458465379750028/1532858245222240317
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/standard-voltage-sram-macros/2026-07/2026-07.json
**Content**
```text
Ahhh, just caught up in the other chat; there's good time until things need to happen anyways, so no need to rush Tim on this.
```
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---