---
page_id: wsd-sram-rules-aa7c7192
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title: "Thread: SRAM rules"
slug: wsd-sram-rules-aa7c7192
route: /evidence/i-information/questions/threads/sram-rules
section: reference
access: public
summary: 10 Discord messages from ℹ️ - Information/⁉️-questions/threads/sram-rules.md.
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---

# Thread: SRAM rules

Category: **ℹ️ - Information**
Parent channel: **#⁉️-questions**
Thread ID: `1444023934251962418`

Messages: **10**

## message-1444023934251962418

**2025-11-28T17:55:34.593+00:00 — tnt (@246tnt)**

- Message ID: `1444023934251962418`
- Author ID: `596068704471482370`
- Nickname: tnt
- User name: 246tnt
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1444023934251962418/1444023934251962418
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sram-rules/2025-11/2025-11.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sram-rules/2025-11/2025-11.json

**Content**

```text
Are the SRAM rules only valid for foundry provided cell ? What if I want to design my own memory array or dual port cell or stuff like that, can I use them ?
```

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## message-1444043397395648593

**2025-11-28T19:12:54.968+00:00 — Leo Moser (mole99) (@mole99)**

- Message ID: `1444043397395648593`
- Author ID: `323371864074485771`
- Nickname: Leo Moser (mole99)
- User name: mole99
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1444023934251962418/1444043397395648593
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sram-rules/2025-11/2025-11.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sram-rules/2025-11/2025-11.json

**Content**

```text
Yes, I think that should be possible.
Afaik it's not the cells that are detected, but rather the SRAM marker layer.
However, as you probably know, there's no guarantee your cells will work after production, since the SRAM cells in the PDK were probably carefully designed to violate the normal core rules.
```

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## message-1444043702996697158

**2025-11-28T19:14:07.829+00:00 — Leo Moser (mole99) (@mole99)**

- Message ID: `1444043702996697158`
- Author ID: `323371864074485771`
- Nickname: Leo Moser (mole99)
- User name: mole99
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1444023934251962418/1444043702996697158
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sram-rules/2025-11/2025-11.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sram-rules/2025-11/2025-11.json

**Content**

```text
In fact, @Tim Edwards  already shrinked the 5V SRAM cells.
```

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## message-1444043966369632256

**2025-11-28T19:15:10.622+00:00 — tnt (@246tnt)**

- Message ID: `1444043966369632256`
- Author ID: `596068704471482370`
- Nickname: tnt
- User name: 246tnt
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1444023934251962418/1444043966369632256
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sram-rules/2025-11/2025-11.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sram-rules/2025-11/2025-11.json

**Content**

```text
I know he did but they are still 6T cells, I'm thinking about doing the same register file that I did on sky130, or a dual port cell, or rom or other things like that.
```

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## message-1444044603459108975

**2025-11-28T19:17:42.516+00:00 — Leo Moser (mole99) (@mole99)**

- Message ID: `1444044603459108975`
- Author ID: `323371864074485771`
- Nickname: Leo Moser (mole99)
- User name: mole99
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1444023934251962418/1444044603459108975
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sram-rules/2025-11/2025-11.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sram-rules/2025-11/2025-11.json

**Content**

```text
Yes, as long as you place the SRAM marker layer you can use the SRAM 3.3V/5V rules, as I understand it.
```

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## message-1444094873014898879

**2025-11-28T22:37:27.712+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1444094873014898879`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1444023934251962418/1444094873014898879
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sram-rules/2025-11/2025-11.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sram-rules/2025-11/2025-11.json

**Content**

```text
When using the SRAM cells DRC rules there are normally a bunch of requirements around the layout of the cells that are not specified in DRC decks and such.
```

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## message-1444095064996446209

**2025-11-28T22:38:13.484+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1444095064996446209`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
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```text
My understanding is that they can violate the rules due to the tuning to make the regular patterns print better.
```

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## message-1444231058567467070

**2025-11-29T07:38:36.878+00:00 — Leo Moser (mole99) (@mole99)**

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- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sram-rules/2025-11/2025-11.json

**Content**

```text
These rules are documented here:
- https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_11_1.html
- https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_11_2.html

So it should be possible to submit your own custom cells based on these rules, but there is no guarantee that they will work as expected.
```

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## message-1444370539190812773

**2025-11-29T16:52:51.65+00:00 — Tim Edwards (@rtimothyedwards_19428)**

- Message ID: `1444370539190812773`
- Author ID: `1365118310701600900`
- Nickname: Tim Edwards
- User name: rtimothyedwards_19428
- Type: `Default`
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**Content**

```text
Since I created the 3.3V SRAM core cell myself, we'll put that theory to the test.
```

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## message-1444505562740953220

**2025-11-30T01:49:23.773+00:00 — Tim 'mithro' Ansell (@mithro_)**

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Yeap! I'm interested to see how things go, I don't quite have the same pull with GF now I'm not Google.
```

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