---
page_id: wsd-sdf-annotation-issues-with-icarus-f718dd75
type: context-page
schema_version: 1
template_id: discord-page
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title: "Thread: SDF annotation issues with Icarus"
slug: wsd-sdf-annotation-issues-with-icarus-f718dd75
route: /evidence/i-information/questions/threads/sdf-annotation-issues-with-icarus
section: reference
access: public
summary: 12 Discord messages from ℹ️ - Information/⁉️-questions/threads/sdf-annotation-issues-with-icarus.md.
status: published
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md_url: /evidence/i-information/questions/threads/sdf-annotation-issues-with-icarus.md
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tags: [discord, wafer-space, archive]
last_updated: 2026-08-19
talk_url: /evidence/i-information/questions/threads/sdf-annotation-issues-with-icarus.talk.md
talk_route: /evidence/i-information/questions/threads/sdf-annotation-issues-with-icarus/talk
---

# Thread: SDF annotation issues with Icarus

Category: **ℹ️ - Information**
Parent channel: **#⁉️-questions**
Thread ID: `1504595042323533845`

Messages: **12**

## message-1504595042323533845

**2026-05-14T21:23:32.114+00:00 — ProfessorGeek101 (@professorgeek101)**

- Message ID: `1504595042323533845`
- Author ID: `316007131721760771`
- Nickname: ProfessorGeek101
- User name: professorgeek101
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1504595042323533845
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

**Content**

```text
Hi everyone! I’m working on STA gate-level simulation for a GF180 LibreLane/Wafer.Space project and I’m running into SDF annotation issues with Icarus.

Our post-PNR netlist is using the 3.3V standard-cell library:

`gf180mcu_as_sc_mcu7t3v3`

The SDF contains entries like:

`(IOPATH A Y (...))`

for cells such as:

`gf180mcu_as_sc_mcu7t3v3__inv_2`
`gf180mcu_as_sc_mcu7t3v3__buff_2`

But the Verilog model I have for `gf180mcu_as_sc_mcu7t3v3.v` appears to be functional-only. For example, the cells only have assignments like:

`assign Y = !A;`
`assign Y = A;`

and I do not see `specify` / `endspecify` timing blocks. Because of that, Icarus reports errors like:

`Unable to match ModPath A -> Y`

The smoke test still passes functionally, but SDF annotation is not clean.

Is there a timing-capable Verilog model for `gf180mcu_as_sc_mcu7t3v3` with `specify` blocks? Or is timed GLS expected to be done with a different GF180 standard-cell library like `gf180mcu_fd_sc_mcu7t5v`?

Any guidance would be appreciated!
```

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## message-1504619720631128204

**2026-05-14T23:01:35.881+00:00 — Lofty (@ravenslofty)**

- Message ID: `1504619720631128204`
- Author ID: `1187141985530818611`
- Nickname: Lofty
- User name: ravenslofty
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1504619720631128204
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

**Content**

```text
um, you are aware that you're trying to work with a third-party PDK, right?

Tholin's doing excellent work, but a one-person standard cell library is going to have teething issues like this.
```

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## message-1504727703071494305

**2026-05-15T06:10:40.901+00:00 — Leo Moser (mole99) (@mole99)**

- Message ID: `1504727703071494305`
- Author ID: `323371864074485771`
- Nickname: Leo Moser (mole99)
- User name: mole99
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1504727703071494305
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

**Content**

```text
@Tholin would probably appreciate your contribution of specify timing blocks in the [repository](https://github.com/AvalonSemiconductors/gf180mcu_as_sc_mcu7t3v3).
```

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---

## message-1504834929723441283

**2026-05-15T13:16:45.727+00:00 — namibj**

- Message ID: `1504834929723441283`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1504834929723441283
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

**Content**

```text
By understanding is also that there's currently suspicion on the 3v3 SCL from Tholin (maybe though not the same one, but I don't see why it would not be (effectively) the same) having an issue that causes high power draw and possibly (somewhat) worse at least at/near startup.

@Tholin , if you can confirm the suspicious heating happens from a cold static start (no clocks or the like!), and happen to have the taped-out GDS for me, I'd like to try getting (low-crosstalk-fidelity) PEX out of it and the get Xyce to see how it comes up during it's POR until it (hopefully) stabilizes.
And see if it triggers and alarms (in particular about power draw, though I fear localized heating might be hard to figure due to the PEX likely not allowing sufficiently-functional thermal connectivity extraction) in the process of the simulation about safe operating areas and/or can at least _somewhat_ point to where the (I presume static) current is going.

If there'd be some special sequence for the external lines to follow to do the turning-on until it exhibits the suspicious power draw, please do share.

I think it'd be more worth it than trying full-die ttsky26a PEX into Xyce especially given that needs me to select a project via (iirc) digital waveforms
```

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## message-1504836132284797071

**2026-05-15T13:21:32.44+00:00 — tnt (@246tnt)**

- Message ID: `1504836132284797071`
- Author ID: `596068704471482370`
- Nickname: tnt
- User name: 246tnt
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1504836132284797071
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

**Content**

```text
AFAIK Tholin's current chip doesn't use his 3v3 SCL.
```

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## message-1504836147401199646

**2026-05-15T13:21:36.044+00:00 — Tholin (@tholin)**

- Message ID: `1504836147401199646`
- Author ID: `220639106915368960`
- Nickname: Tholin
- User name: tholin
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1504836147401199646
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

**Content**

```text
I am using the 5V SCL only
```

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## message-1504845926320177335

**2026-05-15T14:00:27.52+00:00 — namibj**

- Message ID: `1504845926320177335`
- Author ID: `262706220073222144`
- Nickname: namibj
- User name: namibj
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1504845926320177335
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

**Content**

```text
Ohhhh sorry sounded like you had tested (some of) it somewhere on that die already.
```

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## message-1506001678418055278

**2026-05-18T18:33:00.293+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1506001678418055278`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1506001678418055278
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/Information/questions/sdf-annotation-issues-with-icarus/2026-05/2026-05.json

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**Content**

```text
I think @Tim Edwards has test deisgns with tholin's 3v3 SCL?
```

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## message-1517238639195586664

**2026-06-18T18:44:40.515+00:00 — Jason Yang (@.pogeg)**

- Message ID: `1517238639195586664`
- Author ID: `236632873782738944`
- Nickname: Jason Yang
- User name: .pogeg
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1517238639195586664
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-06/2026-06.json

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**Content**

```text
Currently trying out SDF annotated gate simulations as well.
Would adding specify timing blocks be useful if Librelane can generate SDF annotations from STA  for you?
```

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## message-1517413638397493280

**2026-06-19T06:20:03.576+00:00 — Leo Moser (mole99) (@mole99)**

- Message ID: `1517413638397493280`
- Author ID: `323371864074485771`
- Nickname: Leo Moser (mole99)
- User name: mole99
- Type: `Reply`
- Discord message: https://discord.com/channels/1361349522684510449/1504595042323533845/1517413638397493280
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/%E2%81%89%EF%B8%8F-questions/sdf-annotation-issues-with-icarus/2026-06/2026-06.json

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**Content**

```text
I don't understand the question. LibreLane already generates SDF timing data, gf180mcu_as_sc_mcu7t3v3 just needs the specify blocks.
If you would like to add them, it would probably be a good idea to gate them behind an `` `ifndef FUNCTIONAL`` same as in sky130.
```

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## message-1517414238274981969

**2026-06-19T06:22:26.598+00:00 — Jason Yang (@.pogeg)**

- Message ID: `1517414238274981969`
- Author ID: `236632873782738944`
- Nickname: Jason Yang
- User name: .pogeg
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Since Librelane can already generate SDF timing data for you, would there be a point in adding the specify blocks in the Verilog models
```

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## message-1517414859648794785

**2026-06-19T06:24:54.745+00:00 — Leo Moser (mole99) (@mole99)**

- Message ID: `1517414859648794785`
- Author ID: `323371864074485771`
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The specify blocks in the Verilog models act as placeholders that the simulator populates with the SDF data. Often they are just simply empty triplets `(0.0,0.0,0.0)`.
```

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    ]
  }
}
```

</details>

---