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title: "Thread: Small Risc-V cores"
slug: wsd-small-risc-v-cores-8f11ba75
route: /evidence/i-information/general/threads/small-risc-v-cores
section: reference
access: public
summary: 15 Discord messages from ℹ️ - Information/general/threads/small-risc-v-cores.md.
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---

# Thread: Small Risc-V cores

Category: **ℹ️ - Information**
Parent channel: **#general**
Thread ID: `1419342801732239360`

Messages: **15**

## message-1419404965390319636

**2025-09-21T19:28:35.018+00:00 — RebelMike (@rebelmike)**

- Message ID: `1419404965390319636`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `21`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419404965390319636
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Reply/reference**
- https://discord.com/channels/1361349522684510449/1361349523724570941/1419342801732239360
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**Content**

```text

```

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## message-1419404968133398580

**2025-09-21T19:28:35.672+00:00 — RebelMike (@rebelmike)**

- Message ID: `1419404968133398580`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419404968133398580
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
We've realised that the biggest constraint is really the size of the pads.  You're going to want a QSPI interface to some RAM and flash, so that's 7 or preferably 12 IOs.  And then 4 or 8 IOs for actually doing something.  By the time you've made that pad ring you might as well put at least enough RAM in it for registers.

But yes, I believe SERV can be configured to store registers in external RAM, that will be extremely slow though!

I think going for RV32E (only 15 registers) makes sense.  Also if you support the compressed instructions (which is good to save flash bandwidth if you have no/minimal icache) they mostly can only use registers that are in RV32E anyway.
```

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## message-1419405295297368064

**2025-09-21T19:29:53.674+00:00 — RebelMike (@rebelmike)**

- Message ID: `1419405295297368064`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419405295297368064
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
I put together a spreadsheet for possible pad setups on a subdivided chip.  I don't know if the "pad strip" idea (pads on one side only) works in practice. https://docs.google.com/spreadsheets/d/1qEPO6t-Uz7HYwtpl9eECe0vx1UJSmiynZBl_LVMHF0k/edit?gid=0#gid=0
```

**Embeds**

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    "title": "gf180 subdivision",
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## message-1419405825990197268

**2025-09-21T19:32:00.201+00:00 — Tholin (@tholin)**

- Message ID: `1419405825990197268`
- Author ID: `220639106915368960`
- Nickname: Tholin
- User name: tholin
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419405825990197268
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
I believe smaller pads are theoretically possible if you're willing to reduce output drive strength and reduce the effectiveness of the ESD protection.
```

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## message-1419406647432057026

**2025-09-21T19:35:16.048+00:00 — tnt (@246tnt)**

- Message ID: `1419406647432057026`
- Author ID: `596068704471482370`
- Nickname: tnt
- User name: 246tnt
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419406647432057026
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
Technically nothing forces you to make a ring ... you could have a "strip"of pads on one side only.
```

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## message-1419406827476488324

**2025-09-21T19:35:58.974+00:00 — tnt (@246tnt)**

- Message ID: `1419406827476488324`
- Author ID: `596068704471482370`
- Nickname: tnt
- User name: 246tnt
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419406827476488324
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
(I mean from a functional stand point, that might not be directly supported in the tooling)
```

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## message-1419406997798780960

**2025-09-21T19:36:39.582+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1419406997798780960`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419406997798780960
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
There is also this thing called "circuit under pads"
```

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## message-1419407610578210969

**2025-09-21T19:39:05.68+00:00 — tnt (@246tnt)**

- Message ID: `1419407610578210969`
- Author ID: `596068704471482370`
- Nickname: tnt
- User name: 246tnt
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419407610578210969
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
Is that allowed here ? And compatible with the bonding method ?  I know in both ihp and sky, placing anything active under the pad is a not an option.  And on sky in early mpw some people had high failure rate when bonding because there was some stuff under the pad that was getting crushed.
```

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## message-1419407695055945839

**2025-09-21T19:39:25.821+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1419407695055945839`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419407695055945839
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_3.html
```

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## message-1419407781353750570

**2025-09-21T19:39:46.396+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1419407781353750570`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Default`
- Edited: 2025-09-21T19:49:58.104+00:00
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419407781353750570
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
> Active circuits are allowed when ball-type wire-bonding process is used and when bumping/flip chip technology is used. No circuit under pad is allowed when wedge-type wire-bonding process is used. The following additional rules apply to designs when active circuits are used under the pad.
```

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## message-1419410756029382739

**2025-09-21T19:51:35.614+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1419410756029382739`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419410756029382739
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
15 pins == 4 for spi bus, 3 for power, 8 for I/O?
```

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## message-1419412077134741575

**2025-09-21T19:56:50.59+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1419412077134741575`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419412077134741575
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
BTW I expect it'll take us a while to figure out what options make sense
```

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## message-1419413258393227575

**2025-09-21T20:01:32.224+00:00 — RebelMike (@rebelmike)**

- Message ID: `1419413258393227575`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419413258393227575
- Archive source: https://discord.wafer.space/wafer-space/%E2%84%B9%EF%B8%8F%20-%20Information/general/small-risc-v-cores/2025-09/2025-09.json
- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

**Content**

```text
I was thinking the 15 would be 7 for QSPI, 2 for power, clock, reset, 4 for IO.  But actually I think you could get 16 in that width and have an extra ground.
```

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## message-1419430918749163712

**2025-09-21T21:11:42.781+00:00 — Tim 'mithro' Ansell (@mithro_)**

- Message ID: `1419430918749163712`
- Author ID: `169786952432746498`
- Nickname: Tim 'mithro' Ansell
- User name: mithro_
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419430918749163712
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- Archive source: https://discord.wafer.space/wafer-space/Voice%20Channels/general/small-risc-v-cores/2025-09/2025-09.json

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```text
I tend to think of 10 I/O as a good number as it ends up with a byte and 2 "control/signal lines"
```

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## message-1419442227767148584

**2025-09-21T21:56:39.061+00:00 — RebelMike (@rebelmike)**

- Message ID: `1419442227767148584`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1419342801732239360/1419442227767148584
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**Content**

```text
Yeah, only 4 GPIOs is a bit sad.  Going to pins on 2 sides and 3x3 division might be a better option.  Or 5x2 with a single strip but the other way.
```

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