---
page_id: wsd-3v3-cell-library-95355d0d
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title: "Thread: 3v3 cell library"
slug: wsd-3v3-cell-library-95355d0d
route: /evidence/designing/digital/threads/3v3-cell-library
section: reference
access: public
summary: 6 Discord messages from 📐 - Designing/💻-digital/threads/3v3-cell-library.md.
status: published
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tags: [discord, wafer-space, archive]
last_updated: 2026-08-19
talk_url: /evidence/designing/digital/threads/3v3-cell-library.talk.md
talk_route: /evidence/designing/digital/threads/3v3-cell-library/talk
---

# Thread: 3v3 cell library

Category: **📐 - Designing**
Parent channel: **#💻-digital**
Thread ID: `1509460314155122759`

Messages: **6**

## message-1509460323315355700

**2026-05-28T07:36:25.495+00:00 — RebelMike (@rebelmike)**

- Message ID: `1509460323315355700`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1509460314155122759/1509460323315355700
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%8F%97%EF%B8%8F%20-%20Designing/digital/3v3-cell-library/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%93%90%20-%20Designing/%F0%9F%92%BB-digital/3v3-cell-library/2026-05/2026-05.json

**Content**

```text
Hi @Tholin, I’m looking to use your cell library in the next run. I was doing an initial port last night and saw there aren’t latch or clock gate cells. This isn’t a show stopper, but especially a latch would be good to have.
Do you have any plans to add them?
```

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---

## message-1509561262307147828

**2026-05-28T14:17:31.226+00:00 — Tholin (@tholin)**

- Message ID: `1509561262307147828`
- Author ID: `220639106915368960`
- Nickname: Tholin
- User name: tholin
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1509460314155122759/1509561262307147828
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%8F%97%EF%B8%8F%20-%20Designing/digital/3v3-cell-library/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%93%90%20-%20Designing/%F0%9F%92%BB-digital/3v3-cell-library/2026-05/2026-05.json

**Content**

```text
There are latch cells in the library, but you have to manually instantiate them as they lack characterization data.
```

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## message-1509561298927747343

**2026-05-28T14:17:39.957+00:00 — Tholin (@tholin)**

- Message ID: `1509561298927747343`
- Author ID: `220639106915368960`
- Nickname: Tholin
- User name: tholin
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1509460314155122759/1509561298927747343
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%8F%97%EF%B8%8F%20-%20Designing/digital/3v3-cell-library/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%93%90%20-%20Designing/%F0%9F%92%BB-digital/3v3-cell-library/2026-05/2026-05.json

**Content**

```text
You have to exclude all paths through the latches in STA
```

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---

## message-1509561369677004820

**2026-05-28T14:17:56.825+00:00 — Tholin (@tholin)**

- Message ID: `1509561369677004820`
- Author ID: `220639106915368960`
- Nickname: Tholin
- User name: tholin
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1509460314155122759/1509561369677004820
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%8F%97%EF%B8%8F%20-%20Designing/digital/3v3-cell-library/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%93%90%20-%20Designing/%F0%9F%92%BB-digital/3v3-cell-library/2026-05/2026-05.json

**Content**

```text
You’re on your own for making the timing work
```

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---

## message-1509638596741566635

**2026-05-28T19:24:49.192+00:00 — RebelMike (@rebelmike)**

- Message ID: `1509638596741566635`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1509460314155122759/1509638596741566635
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%8F%97%EF%B8%8F%20-%20Designing/digital/3v3-cell-library/2026-05/2026-05.json
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%93%90%20-%20Designing/%F0%9F%92%BB-digital/3v3-cell-library/2026-05/2026-05.json

**Content**

```text
Awesome, thanks - I see them there now.  The way this particular thing is using them timing shouldn't matter.
```

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## message-1513972857619615865

**2026-06-09T18:27:37.512+00:00 — RebelMike (@rebelmike)**

- Message ID: `1513972857619615865`
- Author ID: `691780627338625077`
- Nickname: RebelMike
- User name: rebelmike
- Type: `Default`
- Discord message: https://discord.com/channels/1361349522684510449/1509460314155122759/1513972857619615865
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%8F%97%EF%B8%8F%20-%20Designing/digital/3v3-cell-library/2026-06/2026-06.json
- Archive source: https://discord.wafer.space/wafer-space/%F0%9F%93%90%20-%20Designing/%F0%9F%92%BB-digital/3v3-cell-library/2026-06/2026-06.json

**Content**

```text
One thing I've only just spotted on these latches is the output is inverted (at least according to the verilog and the lib, so I assume it really is).
That was surprising to me!
```

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