---
page_id: curated-analog-verification
type: context-page
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title: Analog Layout, Verification, and PEX
slug: curated-analog-verification
route: /analog-design/layout-verification-and-pex
section: reference
access: public
summary: Analog layout checking, DRC, LVS, and parasitic extraction guidance.
status: published
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home_href: /
md_url: /analog-design/layout-verification-and-pex.md
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tags: [wafer-space, knowledge-base, curated]
last_updated: 2026-08-19
talk_url: /analog-design/layout-verification-and-pex.talk.md
talk_route: /analog-design/layout-verification-and-pex/talk
---

# Analog Layout, Verification, and PEX

This page owns analog layout verification and parasitic extraction. It does not redefine process options or the submission sequence.

## Current summary

The archive's explicit tapeout guidance is to trust KLayout DRC. Magic DRC may report false positives and was not required for tapeout. **Decision, 2026-03-16, by Leo Moser.** ([archive message](/evidence/designing/project-template/threads/chore-update-to-librelane-dev-55-w#message-1483013259635327016); [Discord](https://discord.com/channels/1361349522684510449/1482918666042347791/1483013259635327016))

The later analog-flow summary says precheck uses KLayout DRC. Designers may use Magic or KLayout for layout. It names Magic plus Netgen, or KLayout, as LVS routes. **Confirmed guidance, 2026-06-14.** ([archive message](/evidence/designing/analog#message-1515650076645523457); [Discord](https://discord.com/channels/1361349522684510449/1408135265427394661/1515650076645523457))

Do not call Magic and KLayout DRC equivalent. A clean Magic result can be useful, but the archive assigns tapeout authority to KLayout. For the full signoff meaning, see [Precheck and Signoff](/submission-procedures/precheck-and-signoff).

## PEX and resistor models

The public resistor model list did not include pwell or isosub resistors in the cited question. Leo Moser said Magic PEX can still extract their resistance. **Confirmed tool behavior reported 2026-06-08.** This is not a compact-model claim. ([archive message](/evidence/i-information/questions/threads/are-there-spice-models-for-pwell-resistors#message-1513436381781950605); [Discord](https://discord.com/channels/1361349522684510449/1513073805289848942/1513436381781950605))

## Practical order

1. Run layout checks in the chosen editor.
2. Run the wafer.space KLayout precheck and treat its DRC result as the acceptance result described in the archive. ([archive message](/evidence/designing/project-template/threads/chore-update-to-librelane-dev-55-w#message-1483013259635327016); [Discord](https://discord.com/channels/1361349522684510449/1482918666042347791/1483013259635327016))
3. Run LVS with a supported route named in the archive. ([archive message](/evidence/designing/analog#message-1515650076645523457); [Discord](https://discord.com/channels/1361349522684510449/1408135265427394661/1515650076645523457))
4. When pwell or isosub resistance matters, the archive reports that Magic can extract it during PEX. ([archive message](/evidence/i-information/questions/threads/are-there-spice-models-for-pwell-resistors#message-1513436381781950605); [Discord](https://discord.com/channels/1361349522684510449/1513073805289848942/1513436381781950605))

## Related pages

- [Analog Design](/analog-design)
- [Analog I/O and ESD](/analog-design/io-and-esd)
- [Precheck and Signoff](/submission-procedures/precheck-and-signoff)
- [DRC and LVS Troubleshooting](/troubleshooting/drc-and-lvs)

## Sources

- `1483013259635327016` — 2026-03-16T08:05:14.151Z — Leo Moser (mole99) — [archive message](/evidence/designing/project-template/threads/chore-update-to-librelane-dev-55-w#message-1483013259635327016); [Discord](https://discord.com/channels/1361349522684510449/1482918666042347791/1483013259635327016) — KLayout is the trusted tapeout DRC; Magic DRC is not required.
- `1513436381781950605` — 2026-06-08T06:55:51.705Z — Leo Moser (mole99) — [archive message](/evidence/i-information/questions/threads/are-there-spice-models-for-pwell-resistors#message-1513436381781950605); [Discord](https://discord.com/channels/1361349522684510449/1513073805289848942/1513436381781950605) — Magic PEX extraction of pwell and isosub resistance.
- `1515650076645523457` — 2026-06-14T09:32:17.689Z — Leo Moser (mole99) — [archive message](/evidence/designing/analog#message-1515650076645523457); [Discord](https://discord.com/channels/1361349522684510449/1408135265427394661/1515650076645523457) — Layout, DRC, and LVS tool routes.